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Re: Re: Atmel DataFlash commands?
- From: Stanislav Meduna <stano at meduna dot org>
- To: John Dallaway <john at dallaway dot org dot uk>
- Cc: eCos Discussion <ecos-discuss at ecos dot sourceware dot org>
- Date: Sun, 21 Jun 2009 11:06:08 +0200
- Subject: Re: [ECOS] Re: Atmel DataFlash commands?
- References: <4A3CF4A6.email@example.com> <4A3DB20A.firstname.lastname@example.org>
John Dallaway wrote:
> It looks like the existing read command opcodes in the DataFlash driver
> refer to an older SCK/CLK mode which is not supported in newer devices.
> Can you determine whether we need to continue to support the old SCK/CLK
> mode from the timing diagrams?
Hmm.. the older Inactive Clock Polarity Low mode actually differs from
SPI Mode 0 exactly in the way I have observed - the first data bit
is put to the SO after 64th falling clock edge in the SPI mode
and after 65th edge in the older one.
So the answer depends on 1) whether someone uses a hardware
that only does the older mode and cannot do SPI 0/3 and
2) how to do the transition so that working code out there
does not break in a quite unpleasant way.
I'd guess we'll need a configuration option for the mode here...
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