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Re: Re: Atmel DataFlash commands?
Stanislav Meduna wrote:
> John Dallaway wrote:
>> It looks like the existing read command opcodes in the DataFlash driver
>> refer to an older SCK/CLK mode which is not supported in newer devices.
>> Can you determine whether we need to continue to support the old SCK/CLK
>> mode from the timing diagrams?
> Hmm.. the older Inactive Clock Polarity Low mode actually differs from
> SPI Mode 0 exactly in the way I have observed - the first data bit
> is put to the SO after 64th falling clock edge in the SPI mode
> and after 65th edge in the older one.
> So the answer depends on 1) whether someone uses a hardware
> that only does the older mode and cannot do SPI 0/3 and
> 2) how to do the transition so that working code out there
> does not break in a quite unpleasant way.
The only contributed board support which uses this driver is for the
Atmel AT91EB55 evaluation board which uses an AT45DB321 DataFlash part.
The original version of this part did not support the newer "SPI Mode
> I'd guess we'll need a configuration option for the mode here...
Yes. It seems best to add a CYGOPT_DEVS_FLASH_ATMEL_DATAFLASH_ICP_READ
option which is disabled by default and must be enabled to select the
older "Inactive Clock Polarity High/Low" read commands. We can tweak the
AT91EB55 HAL to require that this option is enabled.
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