Polling status/data from the FIFO generates quite a bit of traffic
on the chip's bus - I don't know how exactly the APB and AHB/APB
bridge work. I mean the speed you are demanding is maybe
too much for the worst case that can happen on the bus
(arbitrations etc). Add to that that you probably need
an interrupt to tell you there is first data, interrupt latency
and driver reaction time - maybe this is too much for a real
application.
I think for this case the DMA is surely a better idea.
See also http://permalink.gmane.org/gmane.comp.hardware.arm.lpc2100/49688 -
someone had problems even using the DMA ...
Why this runs more 3 times slower if there is nothing but
this thread running with disabled interrupts, I have no idea...