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Caches Init in MIPS32 4Kc
- From: Elad Yosef <elad dot yosef at gmail dot com>
- To: ecos-discuss at ecos dot sourceware dot org
- Date: Mon, 3 Jan 2011 17:41:44 +0200
- Subject: [ECOS] Caches Init in MIPS32 4Kc
I have ported the RedBoot for MIPS32 4Kc from the Atlas to my platform.
I have the peripherals working (UART + Ethernet).
The memory layout changed to fit my target and now I want to start
using the cache.
My code runs from Kseg0 and KO in Config0 is 0.
>From I found in the code I see the cache initialization is not fully
implemented for this CPU.
The only think that is done on the cache is some invalidate action.
for the i-cache:
cache 0x8 (address)
for the d-cache:
cache 0x9 (address)
address runs from 0x80000000 up to 0x80004000 in 0x10 steps.
Is it enough to initialize the cache?
Am I missing any configuration?
I couldn't find any implementation for XCACHE_ENABLE
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