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Re: Caches Init in MIPS32 4Kc

Hi Elad,

I've ported eCos to PMC-Sierra MSP8510 which is a MIPS64 based CPU. I would
suggest using a simple MMU setup to have the full control over the cached area.
Simply jumping to 0x8xxxxxxx will work, but you need to setup the cache flags in
the config register.

I've been using eCos on that CPU for year's now and have added nice MMU stuff
like code write protection aso. I can help you with some setup files if you like.


On 03.01.2011 16:41, Elad Yosef wrote:
> Hi,
> I have ported the RedBoot for MIPS32 4Kc from the Atlas to my platform.
> I have the peripherals working (UART + Ethernet).
> The memory layout changed to fit my target and now I want to start
> using the cache.
> My code runs from Kseg0 and KO in Config0 is 0.
> From I found in the code I see the cache initialization is not fully
> implemented for this CPU.
> The only think that is done on the cache is some invalidate action.
> for the i-cache:
> cache 0x8 (address)
> for the d-cache:
> cache 0x9 (address)
> address runs from 0x80000000 up to 0x80004000 in 0x10 steps.
> Is it enough to initialize the cache?
> Am I missing any configuration?
> I couldn't find any implementation for XCACHE_ENABLE
> Thank
> Elad

Dipl.-Ing. Stefan Sommerfeld
Senior Engineer Software

MikroM GmbH -
Tel/Fax: +49-30-398839-0/29

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