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AT91 SPI driver and SPI modes
- From: Daniel Helgason <dhelgason at shaw dot ca>
- To: ecos-discuss at ecos dot sourceware dot org
- Date: Tue, 11 Jan 2011 12:54:45 -0800
- Subject: [ECOS] AT91 SPI driver and SPI modes
I noticed in spi_at91.c line 540 that the SPI clock phase is apparently
set incorrectly. The bit in the SPI_CSR0 register is called NCPHA and is
inverted from what you would expect. The "N" indicates negative logic, I
think. The datasheet for at91sam9g20 bears this out.
The result is that when using the CYG_SPI_DEVICE_ON_BUS(n) macro,
the .cl_pol and .cl_pha members do not select the correct SPI mode. I
noticed this when using SPI flash on one of our boards.
Have other developers using AT91 devices noticed this? Maybe people just
tried various combination of clock polarity and phase until things
| Daniel Helgason <firstname.lastname@example.org>
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