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Re: AT91 SPI driver and SPI modes

Hi Daniel,

We have noticed the same. I have a patch for a fix that I mean to submit. (Actually I have quite a lot of AT91 patches, just not found any time to check them and submit them).


On 11/01/2011 20:54, Daniel Helgason wrote:

I noticed in spi_at91.c line 540 that the SPI clock phase is apparently
set incorrectly. The bit in the SPI_CSR0 register is called NCPHA and is
inverted from what you would expect. The "N" indicates negative logic, I
think. The datasheet for at91sam9g20 bears this out.

The result is that when using the CYG_SPI_DEVICE_ON_BUS(n) macro,
the .cl_pol and .cl_pha members do not select the correct SPI mode. I
noticed this when using SPI flash on one of our boards.

Have other developers using AT91 devices noticed this? Maybe people just
tried various combination of clock polarity and phase until things


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