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MIPS32 4Kc - Interrupt enable and base address for exceptions
- From: Elad Yosef <elad dot yosef at gmail dot com>
- To: ecos-discuss at ecos dot sourceware dot org
- Date: Tue, 18 Jan 2011 11:21:11 +0200
- Subject: [ECOS] MIPS32 4Kc - Interrupt enable and base address for exceptions
MIPS32 4Kc has 2 base addresses for exceptions
bootstrap - 0xBFC00000
normal - 0x80000000
The selection of the base address is by BEV bit in the status register.
In the Boot stage it makes sense that the BEV will select the bootstrap.
but when the application is running from RAM i want it to use the
normal base (mapped to my RAM)
My RedBoot works fine, downloads the application by tftp to RAM and jumps to it.
My application init code is also running well, until the exit from
The eCos default - Is that point the scheduler goes to action and
interrupts are enabled.
At that point I see that my CPU still using the bootstrap base for
which leads to unexpected results.
My question is- Is there some configuration option i need to select in
order to use the "normal" base?
In case there isn't such, At which point on the code should I set the
BEV in the status register?
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