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Re: MIPS32 4Kc - Interrupt enable and base address for exceptions
I was sure that the eCos code already clears the BEV in status register.
Once I clear it, it all works great.
I'll just add some code to clear BEV
On Tue, Jan 18, 2011 at 3:30 PM, Stefan Sommerfeld <firstname.lastname@example.org> wrote:
> Hi Elad,
>> MIPS32 4Kc has 2 base addresses for exceptions
>> bootstrap - 0xBFC00000
>> normal - ? ? 0x80000000
>> The selection of the base address is by BEV bit in the status register.
>> In the Boot stage it makes sense that the BEV will select the bootstrap.
>> but when the application is running from RAM i want it to use the
>> normal base (mapped to my RAM)
>> My RedBoot works fine, downloads the application by tftp to RAM and jumps to it.
>> My application init code is also running well, until the exit from
>> The eCos default - Is that point the scheduler goes to action and
>> interrupts are enabled.
>> At that point I see that my CPU still using the bootstrap base for
>> which leads to unexpected results.
>> My question is- Is there some configuration option i need to select in
>> order to use the "normal" base?
>> In case there isn't such, At which point on the code should I set the
>> BEV in the status register?
> I use normal vectors too. Here are the things you need to do:
> - you need the code for the vectors at address 0, so copy the current code (from
> your eCos to address 0x00000000)
> - store DCache or invalidate it (depending on cached or uncached memory access)
> - set BEV to normal base
> You must make sure you don't use the first 1KB from memory, so you wont alter
> you vectors code.
> But think of what you're doing. This will not gain to much, because you can set
> all interrupts to memory base routines without BEV. eCos will quickly jump to
> the routine from the interrupt vectors table. You can also make your FLASH cachable.
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