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Re: Re: Different section placement for kernel and application
- From: Martin RÃsch <martin dot roesch at neratec dot com>
- To: "discuss, eCos" <ecos-discuss at ecos dot sourceware dot org>
- Date: Mon, 31 Jan 2011 14:30:14 +0100 (CET)
- Subject: Re: [ECOS] Re: Different section placement for kernel and application
On 2011-01-28, Grant Edwards <firstname.lastname@example.org> wrote:
> I'm curious why you want to do this. What benefit does it provide?
I have to link a C++ Application to eCos (with FreeBSD Stack and uSTL) on a STM32 derived board.
The footprint is to big to run it from the internal flash. So we decided to run it from external RAM.
Unfortunately the performance regarding IRQ handling of a RAM Application is too bad:
Using the timers test from the STM32 variant HAL, I've set only TIM1 active and then varied the update
interrupt period. It turned out, that with a period of 20msec. the IRQ handler run into an Assertion in
the post_dsr() function:
ASSERT FAIL: <5>intr.cxxvoid Cyg_Interrupt::post_dsr() DSR list is not empty but its head is 0
Doing the same test with a ROM Application, the period can be lowered to 50usec.
So I'm trying to move the eCos library that contains the ISRs, DSRs etc. to the Internal Flash while keeping
the rest of the application (that has no ISRs and DSRs) still in the external RAM.
I hope this Setup will improve the IRQ handling.
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