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Re: Change exceptions and interrupts Base for MIPS32


Hi,
In the MIPS32 4KEc there is another register in the Co-Processor
EBase register - CP0 register #15 select 1

The BEV bit defines whether the vectors are in RAM or bootstrap only.

The RAM Base is always 0x8000:0000
the Bootstrap Base is always 0xBFC0:0000
The offsets (utlb, reset, other, int) for each location are constant.

My flash is in other address range.
The offsets are the like in RAM, but the base address is not RAM

For example:
Base - 0xB200:0000 == My rom_vectors location in flash
other_vector offset == 0x180 (see MIPS 4KEc user manual)

other_vector should be in 0xB200:0180

Thanks

Elad

On Wed, Feb 2, 2011 at 11:58 AM, Nick Garnett <nickg@ecoscentric.com> wrote:
> Elad Yosef <elad.yosef@gmail.com> writes:
>
>> Hi,
>> My target is MIPS32 4KEc (not the 4Kc)
>> In this CPU, I can configure the base address for exceptions/interrupts.
>>
>> The fetch/reset address is always 0xBFC0:0000 and resides inside a ROM
>> The ROM is very small. The ROM code only enables the flash device and
>> jumps to the RedBoot code in the flash (reset_vector code)
>>
>> The Flash device is not mapped to ?0xBFC0:0000, according to my platform.
>>
>> My issue here is:
>> Where is the best location to update the base address?
>>
>> variant_init? platfrom_init ? or even in earlier stage inside _start ?
>
> The location of the vectors is controlled by the BEV bit in the status
> register. If you take a look at the arch.inc header you will see that
> the initial value of this register is defined by INITIAL_SR. If your
> platform HAL defines this in its platform.inc then it will override
> the default and allow you to clear the BEV bit. There is no need for
> extra code.
>
>
> --
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> eCosCentric Limited ? ?http://www.eCosCentric.com ? ? ? The eCos experts
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