? at572d740-dk2 ? jtst ? mypatch.txt Index: var/current/cdl/hal_arm_at91.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl,v retrieving revision 1.6 diff -u -r1.6 hal_arm_at91.cdl --- var/current/cdl/hal_arm_at91.cdl 20 Feb 2004 18:45:04 -0000 1.6 +++ var/current/cdl/hal_arm_at91.cdl 7 Jun 2004 13:45:09 -0000 @@ -78,7 +78,7 @@ display "AT91 variant used" flavor data default_value {"R40807"} - legal_values {"R40807" "R40008" "M42800A" "M55800A" } + legal_values {"R40807" "R40008" "M42800A" "M55800A" "JTST" "JPMC"} description "The AT91 microcontroller family has several variants, the main differences being the amount of on-chip SRAM, peripherals and their layout. This option allows the @@ -128,7 +128,7 @@ cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_SPEED { display "CPU clock speed" flavor data - default_value {CYGHWR_HAL_ARM_AT91 == "R40008" ? 66000000 : 32768000} + default_value {CYGHWR_HAL_ARM_AT91 == "R40008" ? 66000000 : CYGHWR_HAL_ARM_AT91 == "JTST" || CYGHWR_HAL_ARM_AT91 == "JPMC" ? 50000000 : 32768000} } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { @@ -164,7 +164,7 @@ display "Diagnostic serial port baud rate" flavor data legal_values 9600 19200 38400 57600 115200 - default_value 38400 + default_value {CYGHWR_HAL_ARM_AT91 == "JTST" || CYGHWR_HAL_ARM_AT91 == "JPMC" ? 115200 : 38400} description " This option selects the baud rate used for the diagnostic port." } @@ -173,7 +173,7 @@ display "GDB serial port baud rate" flavor data legal_values 9600 19200 38400 57600 115200 - default_value 38400 + default_value {CYGHWR_HAL_ARM_AT91 == "JTST" || CYGHWR_HAL_ARM_AT91 == "JPMC" ? 115200 : 38400} description " This option controls the baud rate used for the GDB connection." } Index: var/current/include/var_arch.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_arch.h,v retrieving revision 1.1 diff -u -r1.1 var_arch.h --- var/current/include/var_arch.h 24 Jun 2003 08:42:26 -0000 1.1 +++ var/current/include/var_arch.h 7 Jun 2004 13:45:09 -0000 @@ -81,8 +81,10 @@ HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_SCDR, 1); \ CYG_MACRO_END -#else +#elif defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) +#else #error Unknown AT91 variant #endif Index: var/current/include/var_io.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v retrieving revision 1.7 diff -u -r1.7 var_io.h --- var/current/include/var_io.h 24 May 2004 08:41:47 -0000 1.7 +++ var/current/include/var_io.h 7 Jun 2004 13:45:10 -0000 @@ -44,7 +44,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors:jskov, gthomas, tkoeller, tdrury, nickg +// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, amichelotti // Date: 2001-07-12 // Purpose: AT91 variant specific registers // Description: @@ -57,6 +57,122 @@ #include //============================================================================= +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + +// mapping diopsis internal resources +#define AT91_USART0 0xFFFC0000 +#define AT91_USART1 0xFFFC4000 +#define AT91_SPI0 0xFFFC8000 +#define AT91_SPI1 0xFFFCC000 + +#define AT91_PIO 0xFFFF0000 +#define AT91_AIC 0xFFFFF000 +#define AT91_TC 0xFFFEC000 +#define AT91_EBI 0xFFFE4000 +#define AT91_WD 0xFFFF8000 +#define AT91_CLKGEN 0xFFF00000 // clock divider +#define AT91_ADDA 0xFFF08000 // ADDA Analog Digital Digital Analog + + +// SPI interface +#define AT91_SPI_CR 0x0 // control register +#define AT91_SPI_MR 0x4 // mode register +#define AT91_SPI_RDR 0x8 // receive data register +#define AT91_SPI_TDR 0x8 // trasmit data register +#define AT91_SPI_SR 0x10 // status register +#define AT91_SPI_IER 0x14 // interrupt register +#define AT91_SPI_IDR 0x18 // interrupt disable register +#define AT91_SPI_IMR 0x10 // interrupt mask register +#define AT91_SPI_CSR0 0x30 // chip select 0 +#define AT91_SPI_CSR1 0x34 // chip select 1 +#define AT91_SPI_CSR2 0x38 // chip select 2 +#define AT91_SPI_CSR3 0x3C // chip select 3 + + +// CLOCK divider interface + +#define AT91_CLKGEN_CPTMAX0 0x0 //counter 0 +#define AT91_CLKGEN_CPTMAX1 0x4 //counter 1 +#define AT91_CLKGEN_CPTMAX2 0x8 //.. +#define AT91_CLKGEN_CPTMAX3 0xC +#define AT91_CLKGEN_CPTMAX4 0x10 +#define AT91_CLKGEN_CPTMAX5 0x14 +#define AT91_CLKGEN_CPTMAX6 0x18 +#define AT91_CLKGEN_CPTMAX7 0x1C +#define AT91_CLKGEN_CPTMAX8 0x20 +#define AT91_CLKGEN_CLKENABLE 0x24 // enable clocks out, wronly +#define AT91_CLKGEN_CLKDISABLE 0x28 // disable clocks out, wronly + +// ADDA Analog Digital Digital Analog interface + +#define AT91_ADDA_CR 0x0 // adda configuration +#define AT91_ADDA_ADCL0 0x20 // ADC input channel0 LEFT +#define AT91_ADDA_ADCR0 0x24 // ADC input channel0 RIGHT +#define AT91_ADDA_ADCL1 0x28 // ADC input channel1 LEFT +#define AT91_ADDA_ADCR1 0x2C // ADC input channel1 RIGHT +#define AT91_ADDA_ADCL2 0x30 // ADC input channel2 LEFT +#define AT91_ADDA_ADCR2 0x34 // ADC input channel2 RIGHT +#define AT91_ADDA_ADCL3 0x38 // ADC input channel3 LEFT +#define AT91_ADDA_ADCR3 0x3C // ADC input channel3 RIGHT + +#define AT91_ADDA_DACL0 0x20 // DAC output channel0 LEFT +#define AT91_ADDA_DACR0 0x24 // DAC output channel0 RIGHT +#define AT91_ADDA_DACL1 0x28 // DAC output channel1 LEFT +#define AT91_ADDA_DACR1 0x2C // DAC output channel1 RIGHT +#define AT91_ADDA_DACL2 0x30 // DAC output channel2 LEFT +#define AT91_ADDA_DACR2 0x34 // DAC output channel2 RIGHT +#define AT91_ADDA_DACL3 0x38 // DAC output channel3 LEFT +#define AT91_ADDA_DACR4 0x3C // DAC output channel3 RIGHT + + +///// MAGIC DSP +// Magic Data Memory Left BASE 40 bit width (64 bit aligned) +#define AT91_MAARDML 0x00410000 +// Magic Data Memory Right BASE 40 bit width (64 bit aligned) +#define AT91_MAARDMR 0x00420000 +// Magic Parm Left Base (arm interchange memory) 40 bit width (64 bit aligned) +#define AT91_MAARPARML 0x00490000 +// Magic Parm Right Base (arm interchange memory) 40 bit width (64 bit aligned) +#define AT91_MAARPARMR 0x004A0000 +// Magic Program Memory +#define AT91_MAARPM 0x00430000 + +// Magic Global Controller registers +#define AT91_MAARGSR 0x00450000 +#define AT91_MAARGSR_SAR 0x0 // start magic program address +#define AT91_MAARGSR_CONF 0x4 // magic configuration +#define AT91_MAARGSR_STAT 0x8 // magic status rdonly +#define AT91_MAARGSR_EXC 0xC // magic exception rdonly +#define AT91_MAARGSR_EXC_MSK 0x10 // magic exception mask +#define AT91_MAARGSR_PC 0x14 // magic program counter +#define AT91_MAARGSR_QCS 0x18 // magic condition stack Q +#define AT91_MAARGSR_ICS 0x1C // magic condition stack I +#define AT91_MAARGSR_PMS 0x20 // magic pma stack +#define AT91_MAARGSR_DMA_TYPE 0x24 // magic dma type +#define AT91_MAARGSR_DMA_LEN 0x28 // magic dma len +#define AT91_MAARGSR_DMA_MOD 0x2C // magic modifier/stride +#define AT91_MAARGSR_DMA_BADD 0x30 // magic dma buffer address (internal address) +#define AT91_MAARGSR_DMA_XADD 0x34 // magic dma external address +#define AT91_MAARGSR_DMA_START 0x38 // magic start dma +#define AT91_MAARGSR_STEP_MODE 0x3C // magic single cycle mode + + + +// Magic MAAR (MAgic ARm interface) Controller registers base +#define AT91_MAARCSE 0x00460000 +#define AT91_MAARCSE_CMD 0x0 // command register +#define AT91_MAARCSE_CMD_RUN 0x1 // run +#define AT91_MAARCSE_SR 0x4 // status register +#define AT91_MAARCSE_EXC 0x8 // exception register +#define AT91_MAARCSE_EXC_MSK 0xC // mask exception register + + +// usarts are connected to clock divider +#define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud))) + +#endif + // USART #ifndef AT91_USART0 @@ -135,8 +251,9 @@ #define AT91_US_TPR 0x38 // Transmit pointer register #define AT91_US_TCR 0x3c // Transmit counter register +#ifndef AT91_US_BAUD #define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2) - +#endif //============================================================================= // PIO @@ -610,8 +727,9 @@ #endif +#elif defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) #else - #error Unknown AT91 variant #endif Index: var/current/src/at91_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/at91_misc.c,v retrieving revision 1.7 diff -u -r1.7 at91_misc.c --- var/current/src/at91_misc.c 28 Oct 2003 18:09:07 -0000 1.7 +++ var/current/src/at91_misc.c 7 Jun 2004 13:45:10 -0000 @@ -82,10 +82,15 @@ // Disable counter HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); - +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC + AT91_TC_CMR_CLKS_MCK8); // 1 MHz from CLOCKGEN +#else // Set registers HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC AT91_TC_CMR_CLKS_MCK32); // 1 MHz +#endif HAL_WRITE_UINT32(timer+AT91_TC_RC, period); // Start timer @@ -127,7 +132,12 @@ // void hal_delay_us(cyg_int32 usecs) { - CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2; +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + CYG_ADDRESS timer = AT91_TC+AT91_TC_TC1; // Use timer counter 1, timer counter2 it's used with AD/DA converter +#else + CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2; +#endif cyg_uint32 stat; cyg_uint64 ticks; @@ -140,7 +150,12 @@ HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); // Set registers +#if defined(CYGHWR_HAL_ARM_AT91_JTST) || \ + defined(CYGHWR_HAL_ARM_AT91_DJPMC) + HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK8); // MCK8 =1 points to clockgen => 1MHz +#else HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz +#endif HAL_WRITE_UINT32(timer+AT91_TC_RA, 0); HAL_WRITE_UINT32(timer+AT91_TC_RC, ticks); @@ -188,7 +203,7 @@ // No valid interrrupt source, treat as spurious interrupt if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX) irq_num = CYGNUM_HAL_INTERRUPT_NONE; - + return irq_num; }