--- var_io.h	2004-07-29 22:41:52.000000000 +0200
+++ /opt/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h	2004-07-24 00:21:46.000000000 +0200
@@ -135,7 +135,7 @@
 #define AT91_US_TPR 0x38  // Transmit pointer register
 #define AT91_US_TCR 0x3c  // Transmit counter register
 
-#define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
+#define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud)))
 
 //=============================================================================
 // PIO
@@ -295,8 +295,8 @@
 #define AT91_TC_CCR_CLKEN  0x01
 #define AT91_TC_CCR_CLKDIS 0x02
 #define AT91_TC_CCR_TRIG   0x04
-// Channel Mode Register
 #define AT91_TC_CMR		   0x04
+// Capture mode definitions
 #define AT91_TC_CMR_CLKS	   0
 #define AT91_TC_CMR_CLKS_MCK2      (0<<0)
 #define AT91_TC_CMR_CLKS_MCK8      (1<<0)
@@ -311,7 +311,6 @@
 #define AT91_TC_CMR_BURST_XC0      (1<<4)
 #define AT91_TC_CMR_BURST_XC1      (2<<4)
 #define AT91_TC_CMR_BURST_XC2      (3<<4)
-// Capture mode definitions
 #define AT91_TC_CMR_LDBSTOP        (1<<6)
 #define AT91_TC_CMR_LDBDIS         (1<<7)
 #define AT91_TC_CMR_TRIG_NONE      (0<<8)
@@ -329,53 +328,7 @@
 #define AT91_TC_CMR_LDRB_TIOA_NEG  (1<<16)
 #define AT91_TC_CMR_LDRB_TIOA_POS  (2<<16)
 #define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<16)
-// Waveform mode definitions
-#define AT91_TC_CMR_CPCSTOP        (1<<6)
-#define AT91_TC_CMR_CPCDIS	   (1<<7)
-#define AT91_TC_CMR_EEVTEDG_NONE   (0<<8)
-#define AT91_TC_CMR_EEVTEDG_NEG    (1<<8)
-#define AT91_TC_CMR_EEVTEDG_POS    (2<<8)
-#define AT91_TC_CMR_EEVTEDG_BOTH   (3<<8)
-#define AT91_TC_CMR_EEVT_TIOB	   (0<<10)
-#define AT91_TC_CMR_EEVT_XC0       (1<<10)
-#define AT91_TC_CMR_EEVT_XC1       (2<<10)
-#define AT91_TC_CMR_EEVT_XC2       (3<<10)
-#define AT91_TC_CMR_ENETRG	   (1<<12)
-#define AT91_TC_CMR_CPCTRG	   (1<<14)
-#define AT91_TC_CMR_WAVE	   (1<<15)
-#define AT91_TC_CMR_ACPA_NONE	   (0<<16)
-#define AT91_TC_CMR_ACPA_SET	   (1<<16)
-#define AT91_TC_CMR_ACPA_CLEAR	   (2<<16)
-#define AT91_TC_CMR_ACPA_TOGGLE	   (3<<16)
-#define AT91_TC_CMR_ACPC_NONE	   (0<<18)
-#define AT91_TC_CMR_ACPC_SET	   (1<<18)
-#define AT91_TC_CMR_ACPC_CLEAR	   (2<<18)
-#define AT91_TC_CMR_ACPC_TOGGLE	   (3<<18)
-#define AT91_TC_CMR_AEEVT_NONE	   (0<<20)
-#define AT91_TC_CMR_AEEVT_SET	   (1<<20)
-#define AT91_TC_CMR_AEEVT_CLEAR	   (2<<20)
-#define AT91_TC_CMR_AEEVT_TOGGLE   (3<<20)
-#define AT91_TC_CMR_ASWTRG_NONE	   (0<<22)
-#define AT91_TC_CMR_ASWTRG_SET	   (1<<22)
-#define AT91_TC_CMR_ASWTRG_CLEAR   (2<<22)
-#define AT91_TC_CMR_ASWTRG_TOGGLE  (3<<22)
-#define AT91_TC_CMR_BCPB_NONE	   (0<<24)
-#define AT91_TC_CMR_BCPB_SET	   (1<<24)
-#define AT91_TC_CMR_BCPB_CLEAR	   (2<<24)
-#define AT91_TC_CMR_BCPB_TOGGLE	   (3<<24)
-#define AT91_TC_CMR_BCPC_NONE	   (0<<26)
-#define AT91_TC_CMR_BCPC_SET	   (1<<26)
-#define AT91_TC_CMR_BCPC_CLEAR	   (2<<26)
-#define AT91_TC_CMR_BCPC_TOGGLE	   (3<<26)
-#define AT91_TC_CMR_BEEVT_NONE	   (0<<28)
-#define AT91_TC_CMR_BEEVT_SET	   (1<<28)
-#define AT91_TC_CMR_BEEVT_CLEAR	   (2<<28)
-#define AT91_TC_CMR_BEEVT_TOGGLE   (3<<28)
-#define AT91_TC_CMR_BSWTRG_NONE	   (0<<30)
-#define AT91_TC_CMR_BSWTRG_SET	   (1<<30)
-#define AT91_TC_CMR_BSWTRG_CLEAR   (2<<30)
-#define AT91_TC_CMR_BSWTRG_TOGGLE  (3<<30)
-
+// Waveform mode definitions [missing]
 #define AT91_TC_CV      0x10
 #define AT91_TC_RA      0x14
 #define AT91_TC_RB      0x18
@@ -620,6 +573,43 @@
 //=============================================================================
 // Watchdog
 
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+#ifndef AT91_ST
+#define AT91_ST             0xFFFF8000
+#endif
+
+#define AT91_ST_CR           0x00000000
+#define AT91_ST_CR_WDRST     0x00000001
+
+#define AT91_ST_PIMR         0x00000004
+#define AT91_ST_PIMR_PIV_MSK 0x0000ffff
+
+#define AT91_ST_WDMR         0x00000008
+#define AT91_ST_WDMR_EXTEN   0x00020000
+#define AT91_ST_WDMR_RSTEN   0x00010000
+#define AT91_ST_WDMR_WDV_MSK 0x0000ffff
+
+#define AT91_ST_RTMR         0x0000000C
+#define AT91_ST_RTMR_RTP_MSK 0x0000ffff
+
+#define AT91_ST_SR           0x00000010
+#define AT91_ST_IER          0x00000014
+#define AT91_ST_IDR          0x00000018
+#define AT91_ST_IMR          0x0000001C
+
+#define AT91_ST_PITS         0x00000001
+#define AT91_ST_WDOVF        0x00000002
+#define AT91_ST_RTTINC       0x00000004
+#define AT91_ST_ALMS         0x00000008
+
+#define AT91_ST_RTAR          0x00000020
+#define AT91_ST_RTAR_ALMV_MSK 0x00ffffff
+
+#define AT91_ST_CRTR          0x00000024
+#define AT91_ST_CRTR_ALMV_MSK 0x00ffffff
+
+#else
+
 #ifndef AT91_WD
 #define AT91_WD             0xFFFF8000
 #endif
@@ -638,7 +628,7 @@
 #define AT91_WD_CR_RSTKEY   0x0000C071
 #define AT91_WD_SR          0x0C
 #define AT91_WD_SR_WDOVF    0x00000001
-
+#endif
 
 //-----------------------------------------------------------------------------
 // end of var_io.h