--- watchdog_at91.cxx	2004-08-05 11:33:26.000000000 +0200
+++ /opt/ecos/ecos/packages/devs/watchdog/arm/at91/current/src/watchdog_at91.cxx	2004-08-04 20:22:20.000000000 +0200
@@ -73,13 +73,15 @@
 
 //==========================================================================
 
-#define MCLK_FREQUENCY_KHZ  (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
-#define MAX_TICKS     	    0x0000ffff
-#define BASE_TICKS    	    (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
 
 #if defined(CYGHWR_HAL_ARM_AT91_R40008) || \
     defined(CYGHWR_HAL_ARM_AT91_R40807)
 
+#define MCLK_FREQUENCY_KHZ  (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
+#define MAX_TICKS     	    0x0000ffff
+#define BASE_TICKS    	    (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
 #if   BASE_TICKS / 8 <= MAX_TICKS
 #define DIVIDER 0
 #define DIV_FACTOR 8
@@ -96,8 +98,15 @@
 #error Desired resolution beyond hardware capabilities
 #endif
 
+#define TICKS 	    ((BASE_TICKS / DIV_FACTOR) | 0xfff)
+#define RESOLUTION  ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+
 #elif defined(CYGHWR_HAL_ARM_AT91_M55800A)
 
+#define MCLK_FREQUENCY_KHZ  (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
+#define MAX_TICKS     	    0x0000ffff
+#define BASE_TICKS    	    (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
 #if   BASE_TICKS / 32 <= MAX_TICKS
 #define DIVIDER 0
 #define DIV_FACTOR 32
@@ -114,17 +123,32 @@
 #error Desired resolution beyond hardware capabilities
 #endif
 
+#define TICKS 	    ((BASE_TICKS / DIV_FACTOR) | 0xfff)
+#define RESOLUTION  ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+#elif defined(CYGHWR_HAL_ARM_AT91_M42800A)
+
+#define SCLK_FREQUENCY_HZ  32800     // Slow clock in hertz
+#define MAX_TICKS     	    0x0000ffff
+#define BASE_TICKS    	    (SCLK_FREQUENCY_HZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS/1000)
+
+#if BASE_TICKS/128  > MAX_TICKS
+#error Desired resolution beyond hardware capabilities
+#endif
+
+#define TICKS ((BASE_TICKS / 128) & 0xffff)
+#define RESOLUTION  ((cyg_uint64) (TICKS * 128) * 1000000000 / SCLK_FREQUENCY_HZ)
 
 #endif
 
-#define TICKS 	    ((BASE_TICKS / DIV_FACTOR) | 0xfff)
-#define RESOLUTION  ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+
 
 //==========================================================================
 
 #if defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT)
 
 #define OMRVAL	(AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN)
+#define WDMRFLG (AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN)
+#define IERFLG  0
 
 void
 Cyg_Watchdog::init_hw(void)
@@ -140,6 +164,8 @@
 //==========================================================================
 
 #define OMRVAL	(AT91_WD_OMR_OKEY | AT91_WD_OMR_IRQEN | AT91_WD_OMR_WDEN)
+#define WDMRFLG 0
+#define IERFLG  (AT91_ST_WDOVF)
 #define INT_PRIO    7
 
 //==========================================================================
@@ -168,7 +194,7 @@
     0,
     isr,
     NULL
-  );
+  ) CYGBLD_ATTRIB_INIT_PRI( CYG_INIT_DRIVERS );
 
 //==========================================================================
 
@@ -200,9 +226,14 @@
 {
   CYG_REPORT_FUNCTION();
   CYG_REPORT_FUNCARGVOID();
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+  /* Re-arm watchdog timer */
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_CR, AT91_ST_CR_WDRST);
 
+#else
   /* Write magic code to reset the watchdog. */
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
+#endif
   CYG_REPORT_RETURN();
 }
 
@@ -218,6 +249,11 @@
   CYG_REPORT_FUNCTION();
   CYG_REPORT_FUNCARGVOID();
   
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_WDMR, TICKS | WDMRFLG );
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_IER, IERFLG );
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_CR, AT91_ST_CR_WDRST  );
+#else
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY);
   HAL_WRITE_UINT32(
     AT91_WD + AT91_WD_CMR,
@@ -225,6 +261,7 @@
   );
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, OMRVAL);
+#endif 
   CYG_REPORT_RETURN();
 }