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IQ80321 fix
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Mon, 12 Aug 2002 11:30:33 -0400
- Subject: IQ80321 fix
Checked in work around for BIOS timeout (on some PCI-X motherboards) while
scrubbing SDRAM.
--Mark
Index: hal/arm/xscale/iq80321/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80321/current/ChangeLog,v
retrieving revision 1.5
diff -u -p -5 -r1.5 ChangeLog
--- hal/arm/xscale/iq80321/current/ChangeLog 15 Jul 2002 20:06:58 -0000 1.5
+++ hal/arm/xscale/iq80321/current/ChangeLog 12 Aug 2002 15:28:43 -0000
@@ -1,5 +1,16 @@
+2002-08-12 Mark Salter <msalter@redhat.com>
+
+ * include/hal_platform_setup.h: Do some ATU initialization
+ before scrubbing, so PC BIOS can continue booting during
+ time consuming scrub.
+
+ * src/iq80321_pci.c (cyg_hal_plf_pci_init): Always set ATUCMD
+ register. Moved some ATU initialization to hal_platform_setup.h.
+ (cyg_hal_plf_wait_for_bios): Moved some ATU initialization to
+ hal_platform_setup.h.
+
2002-07-15 Mark Salter <msalter@redhat.com>
* include/pkgconf/mlt_arm_xscale_iq80321_rom.mlt: Add mmu_tables section.
* include/pkgconf/mlt_arm_xscale_iq80321_rom.ldi: Regenerated.
* include/pkgconf/mlt_arm_xscale_iq80321_rom.h: Ditto.
Index: hal/arm/xscale/iq80321/current/include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h,v
retrieving revision 1.2
diff -u -p -5 -r1.2 hal_platform_setup.h
--- hal/arm/xscale/iq80321/current/include/hal_platform_setup.h 23 May 2002 23:02:32 -0000 1.2
+++ hal/arm/xscale/iq80321/current/include/hal_platform_setup.h 12 Aug 2002 15:28:43 -0000
@@ -754,10 +754,37 @@ icache_boundary:
mov r1, #0x8 // enable ECC, disable reporting
str r1, [r0]
no_ecc1:
+#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+ // Minimally setup ATU and release "retry" bit.
+ ldr r1, =ATU_IATVR2
+ mov r0, #SDRAM_PHYS_BASE
+ str r0, [r1]
+ ldr r0, =0xffffffff
+ sub r1, r4, #1
+ sub r0, r0, r1
+ bic r0, r0, #0x3f
+ ldr r1, =ATU_IALR2
+ str r0, [r1]
+ ldr r0, =((0xFFFFFFFF - ((64 * 1024 * 1024) - 1)) & 0xFFFFFFC0)
+ ldr r1, =ATU_IALR1
+ str r0, [r1]
+ mov r0, #0xc
+ ldr r1, =ATU_IABAR1
+ str r0, [r1]
+ mov r0, #0
+ ldr r1, =ATU_IAUBAR1
+ str r0, [r1]
+ ldr r1, =ATU_PCSR
+ ldr r0, [r1]
+ and r13, r0, #4 // save retry bit for later
+ bic r0, r0, #4
+ str r0, [r1]
+#endif
+
// scrub init
mov r12, r4 // size of memory to scrub
mov r8, r4 // save DRAM size
mov r0, #0
mov r1, #0
@@ -841,10 +868,16 @@ icache_boundary:
// Save SDRAM size
ldr r1, =hal_dram_size /* [see hal_intr.h] */
str r8, [r1]
+#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+ // Save boot time retry flag.
+ ldr r1, =hal_pcsr_cfg_retry
+ str r13, [r1]
+#endif
+
// Move mmu tables into RAM so page table walks by the cpu
// don't interfere with FLASH programming.
ldr r0, =mmu_table
add r2, r0, #0x4000 // End of tables
mov r1, #SDRAM_BASE
@@ -907,10 +940,12 @@ icache_boundary:
#define PLATFORM_SETUP1
#endif
#define PLATFORM_VECTORS _platform_vectors
.macro _platform_vectors
+ .globl hal_pcsr_cfg_retry
+hal_pcsr_cfg_retry: .long 0 // Boot-time value of PCSR Retry bit.
.endm
/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
Index: hal/arm/xscale/iq80321/current/src/iq80321_pci.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80321/current/src/iq80321_pci.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 iq80321_pci.c
--- hal/arm/xscale/iq80321/current/src/iq80321_pci.c 23 May 2002 23:02:33 -0000 1.2
+++ hal/arm/xscale/iq80321/current/src/iq80321_pci.c 12 Aug 2002 15:28:44 -0000
@@ -89,33 +89,31 @@ cyg_uint32 hal_pci_inbound_window_mask;
// Outbound Translate Window 1 - Unused.
// Outbound IO Window - Unused.
//
+#ifdef CYG_HAL_STARTUP_ROM
#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+// state of retry bit in PCSR prior to bit being cleared at sdram scrub time.
+extern int hal_pcsr_cfg_retry;
+
// Wait for BIOS to configure Verde PCI.
// Returns true if BIOS done, false if timeout
bool
cyg_hal_plf_wait_for_bios(void)
{
int delay = 200; // 20 seconds, tops
- // 64-bit prefetchable
- *ATU_IABAR1 = CYG_PRI_CFG_BAR_MEM_TYPE_64 | CYG_PRI_CFG_BAR_MEM_PREFETCH;
- *ATU_IAUBAR1 = 0;
-
- // clear RETRY
- *ATU_PCSR &= ~PCSR_CFG_RETRY;
-
while (delay-- > 0) {
if (*ATU_ATUCMD & CYG_PCI_CFG_COMMAND_MEMORY)
return true;
hal_delay_us(100000);
}
return false;
}
#endif // CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
+#endif // CYG_HAL_STARTUP_ROM
void
cyg_hal_plf_pci_init(void)
{
cyg_uint32 dram_limit = (0xFFFFFFFF - (hal_dram_size - 1)) & 0xFFFFFFC0;
@@ -123,29 +121,17 @@ cyg_hal_plf_pci_init(void)
// Enable NIC through GPIO pin. This may not have an effect depending
// on switch settings.
*GPIO_GPOE &= ~(1 << IQ80321_GBE_GPIO_PIN);
*GPIO_GPOD |= (1 << IQ80321_GBE_GPIO_PIN);
- // Inbound window 2 is used for SDRAM access.
- // set inbound ATU translate value register to base of local DRAM
- *ATU_IATVR2 = SDRAM_PHYS_BASE;
-
- // set inbound ATU limit register to include all of installed DRAM.
- // This value used as a mask.
- // Allow pci access to all memory
- *ATU_IALR2 = dram_limit;
-
hal_pci_inbound_window_mask = ~dram_limit;
- // set inbound ATU limit 1 to reserve 64MB for outbound window 0.
- *ATU_IALR1 = (0xFFFFFFFF - ((64 * 1024 * 1024) - 1)) & 0xFFFFFFC0;
-
+#ifdef CYG_HAL_STARTUP_ROM
#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
- if (!(*ATU_PCSR & PCSR_CFG_RETRY) || !cyg_hal_plf_wait_for_bios())
+ if (!hal_pcsr_cfg_retry || !cyg_hal_plf_wait_for_bios())
#endif // CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
{
-#ifdef CYG_HAL_STARTUP_ROM
// 64-bit prefetchable
*ATU_IABAR2 = SDRAM_PHYS_BASE | \
CYG_PRI_CFG_BAR_MEM_TYPE_64 | \
CYG_PRI_CFG_BAR_MEM_PREFETCH;
*ATU_IAUBAR2 = 0;
@@ -154,18 +140,19 @@ cyg_hal_plf_pci_init(void)
// by inbound window 1
*ATU_IABAR1 = _PCI_MEM_BASE | \
CYG_PRI_CFG_BAR_MEM_TYPE_64 | \
CYG_PRI_CFG_BAR_MEM_PREFETCH;
- // allow ATU to act as a bus master, respond to PCI memory accesses,
- // and assert S_SERR#
- *ATU_ATUCMD = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
-#endif // CYG_HAL_STARTUP_ROM
}
+#endif // CYG_HAL_STARTUP_ROM
+
+ // allow ATU to act as a bus master, respond to PCI memory accesses,
+ // and assert S_SERR#
+ *ATU_ATUCMD = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
hal_pci_alloc_base_memory = *ATU_IABAR1 & CYG_PRI_CFG_BAR_MEM_MASK;
hal_pci_alloc_base_io = _PCI_IO_BASE;
hal_pci_inbound_window_base = *ATU_IABAR2 & CYG_PRI_CFG_BAR_MEM_MASK;