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Add Adder platform
- From: Gary Thomas <gthomas at ecoscentric dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 25 Nov 2002 16:16:32 -0700
- Subject: Add Adder platform
Plus lots of changes to make PPC/QUICC support more generalized.
Index: NEWS
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/NEWS,v
retrieving revision 1.57
diff -u -5 -p -r1.57 NEWS
--- NEWS 15 Nov 2002 18:05:20 -0000 1.57
+++ NEWS 25 Nov 2002 19:01:35 -0000
@@ -1,5 +1,6 @@
+* Add support for Analogue & Micro Adder (PowerPC 850) boards
* Update MN10300 ASB2303 HAL to support RedBoot
* New package for application level profiling (histogram only)
* Support for NPWR Linux Engine (Xscale IOP310) from Team ASA
* Support for Allied Telesyn TS1000 (PowerPC 855T based design)
* Yoshinori Sato has contributed a watchdog driver for the Hitachi H8/300H.
Index: ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ChangeLog,v
retrieving revision 1.86
diff -u -5 -p -r1.86 ChangeLog
--- ChangeLog 14 Nov 2002 23:49:08 -0000 1.86
+++ ChangeLog 25 Nov 2002 18:46:54 -0000
@@ -1,5 +1,10 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * ecos.db: Add support for A&M "Adder" (PowerPC 850)
+ Split PowerPC QUICC ethernet driver into generic+platform.
+
2002-11-14 Gary Thomas <gthomas@ecoscentric.com>
* ecos.db: Add application profiling package.
2002-11-14 Mark Salter <msalter@redhat.com>
Index: ecos.db
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ecos.db,v
retrieving revision 1.79
diff -u -5 -p -r1.79 ecos.db
--- ecos.db 15 Nov 2002 00:27:21 -0000 1.79
+++ ecos.db 25 Nov 2002 20:36:51 -0000
@@ -481,10 +481,20 @@ package CYGPKG_DEVS_FLASH_VIPER {
description "
This package contains hardware support for FLASH memory
on the A&M PowerPC/8xx VIPER platform."
}
+package CYGPKG_DEVS_FLASH_POWERPC_ADDER {
+ alias { "FLASH memory support for A&M Adder PowerPC/85x" flash_adder }
+ directory devs/flash/powerpc/adder
+ script flash_adder.cdl
+ hardware
+ description "
+ This package contains hardware support for FLASH memory
+ on the A&M PowerPC/8xx ADDER platform."
+}
+
package CYGPKG_DEVS_FLASH_MN10300_STB {
alias { "FLASH memory support for Matsushita MN10300 STB" flash_stb }
directory devs/flash/mn10300/stb
script flash_stb.cdl
hardware
@@ -1169,10 +1179,18 @@ package CYGPKG_DEVS_ETH_POWERPC_QUICC {
directory devs/eth/powerpc/quicc
script quicc_eth_drivers.cdl
description "Ethernet driver for PowerPC QUICC (MPC8xx) based boards."
}
+package CYGPKG_DEVS_ETH_POWERPC_MBX {
+ alias { "MBX ethernet driver specifics" mbx_eth_driver }
+ hardware
+ directory devs/eth/powerpc/mbx
+ script mbx_eth_drivers.cdl
+ description "Ethernet driver specifics for Motorola MBX PowerPC (MPC8xx) based boards."
+}
+
package CYGPKG_DEVS_ETH_POWERPC_FEC {
alias { "FEC ethernet driver" fec_eth_driver }
hardware
directory devs/eth/powerpc/fec
script fec_eth_drivers.cdl
@@ -1185,10 +1203,18 @@ package CYGPKG_DEVS_ETH_POWERPC_VIPER {
directory devs/eth/powerpc/viper
script viper_eth_drivers.cdl
description "Ethernet driver specifics for A&M Viper (MPC8xxT) based boards."
}
+package CYGPKG_DEVS_ETH_POWERPC_ADDER {
+ alias { "A&M Adder ethernet driver" adder_eth_driver }
+ hardware
+ directory devs/eth/powerpc/adder
+ script adder_eth_drivers.cdl
+ description "Ethernet driver specifics for A&M Adder (MPC85x) based boards."
+}
+
package CYGPKG_DEVS_ETH_INTEL_I82559 {
alias { "Intel 82559 ethernet driver"
devs_eth_intel_i82559 i82559_eth_driver }
hardware
directory devs/eth/intel/i82559
@@ -2489,10 +2515,20 @@ package CYGPKG_HAL_POWERPC_VIPER {
description "
The VIPER HAL package provides the support needed to run
eCos on a A&M VIPER board equipped with a PowerPC processor."
}
+package CYGPKG_HAL_POWERPC_ADDER {
+ alias { "A&M Adder PPC85x board" hal_powerpc_adder powerpc_adder_hal }
+ directory hal/powerpc/adder
+ script hal_powerpc_adder.cdl
+ hardware
+ description "
+ The ADDER HAL package provides the support needed to run
+ eCos on a A&M ADDER board equipped with a PowerPC processor."
+}
+
package CYGPKG_HAL_QUICC {
alias { "Motorola MBX860/821 QUICC support" hal_quicc quicc_hal quicc }
directory hal/powerpc/quicc
script hal_powerpc_quicc.cdl
hardware
@@ -3678,10 +3714,11 @@ target mbx {
CYGPKG_HAL_POWERPC_MPC8xx
CYGPKG_HAL_POWERPC_MBX
CYGPKG_HAL_QUICC
CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
CYGPKG_DEVS_ETH_POWERPC_QUICC
+ CYGPKG_DEVS_ETH_POWERPC_MBX
CYGPKG_DEVS_FLASH_MBX
CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
}
description "
The mbx target provides the packages needed to run
@@ -3701,10 +3738,27 @@ target viper {
CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
}
description "
The viper target provides the packages needed to run
eCos on a A&M Viper PPC860 board."
+}
+
+target adder {
+ alias { "A&M Adder PPC850 board" adder850 }
+ packages { CYGPKG_HAL_POWERPC
+ CYGPKG_HAL_POWERPC_MPC8xx
+ CYGPKG_HAL_POWERPC_ADDER
+ CYGPKG_HAL_QUICC
+ CYGPKG_DEVS_FLASH_POWERPC_ADDER
+ CYGPKG_DEVS_FLASH_AMD_AM29XXXXX
+ CYGPKG_DEVS_ETH_POWERPC_QUICC
+ CYGPKG_DEVS_ETH_POWERPC_ADDER
+ }
+# CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
+ description "
+ The adder target provides the packages needed to run
+ eCos on a A&M Adder PPC850 board."
}
target psim {
alias { "PowerPC simulator" ppc_sim powerpc_sim }
packages { CYGPKG_HAL_POWERPC
Index: devs/eth/powerpc/adder/current/cdl/adder_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/adder/current/cdl/adder_eth_drivers.cdl
diff -N devs/eth/powerpc/adder/current/cdl/adder_eth_drivers.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/adder/current/cdl/adder_eth_drivers.cdl 20 Nov 2002 13:02:16 -0000
@@ -0,0 +1,71 @@
+#====================================================================
+#
+# adder_eth_drivers.cdl
+#
+# Hardware specifics for A&M Adder ethernet
+#
+#====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas, hmt
+# Original data: gthomas
+# Contributors: gthomas
+# Date: 2001-02-14
+#
+#####DESCRIPTIONEND####
+#
+#====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_ADDER {
+ display "A&M Adder (MPC8xxT) ethernet support"
+ description "Hardware specifics for A&M Adder ethernet"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_POWERPC
+ active_if CYGPKG_HAL_POWERPC_MPC8xx
+ active_if CYGPKG_HAL_POWERPC_ADDER
+
+ requires CYGPKG_DEVS_ETH_POWERPC_QUICC
+
+ compile adder_eth.c
+
+ include_dir cyg/io
+ define_proc {
+ puts $::cdl_system_header "#define CYGDAT_DEVS_QUICC_ETH_INL <cyg/io/adder_eth.inl>"
+ }
+}
Index: devs/eth/powerpc/adder/current/include/adder_eth.inl
===================================================================
RCS file: devs/eth/powerpc/adder/current/include/adder_eth.inl
diff -N devs/eth/powerpc/adder/current/include/adder_eth.inl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/adder/current/include/adder_eth.inl 25 Nov 2002 20:27:23 -0000
@@ -0,0 +1,97 @@
+#ifndef CYGONCE_DEVS_ADDER_ETH_INL
+#define CYGONCE_DEVS_ADDER_ETH_INL
+//==========================================================================
+//
+// adder_eth.inl
+//
+// Hardware specifics for A&M Adder ethernet support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2002-11-19
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+extern int _adder_get_leds(void);
+extern void _adder_set_leds(int);
+extern bool _adder_reset_phy(void);
+
+#define _get_led() _adder_get_leds()
+#define _set_led(v) _adder_set_leds(v)
+
+#define LED_TxACTIVE 2
+#define LED_RxACTIVE 1
+
+// Reset the PHY - analagous to hardware reset
+#define QUICC_ETH_RESET_PHY() \
+ if (!_adder_reset_phy()) { \
+ diag_printf("Can't reset PHY or get link\n"); \
+ }
+
+// Port layout - uses SCC2
+#define QUICC_ETH_INT CYGNUM_HAL_INTERRUPT_CPM_SCC2
+#define QUICC_ETH_SCC 1 // SCC2
+#define QUICC_CPM_SCCx QUICC_CPM_SCC2
+
+// Fixed bits
+#define QUICC_ETH_PA_RXD 0x0004 // Rx Data on Port A
+#define QUICC_ETH_PA_TXD 0x0008 // Tx Data on Port A
+#define QUICC_ETH_PC_COLLISION 0x0040 // Collision detect
+#define QUICC_ETH_PC_Rx_ENABLE 0x0080 // Rx Enable (RENA)
+
+// These depend on how the PHY is wired to the CPU
+#define QUICC_ETH_PA_Tx_CLOCK 0x0200 // Tx Clock = CLK2
+#define QUICC_ETH_PA_Rx_CLOCK 0x0800 // Rx Clock = CLK4
+#define QUICC_ETH_SICR_MASK 0xFF00 // SI Clock Route - important bits
+#define QUICC_ETH_SICR_ENET (7<<11)|(5<<8) // Rx=CLK4, Tx=CLK2
+#define QUICC_ETH_SICR_ENABLE 0x4000 // Enable SCC2 to use NMSI
+
+// The TENA signal can appear on either port B or C
+//#define QUICC_ETH_PC_Tx_ENABLE 0x0002 // Tx Enable (TENA)
+#define QUICC_ETH_PB_Tx_ENABLE 0x2000 // Tx Enable (TENA)
+
+
+#endif // CYGONCE_DEVS_ADDER_ETH_INL
+// ------------------------------------------------------------------------
Index: devs/eth/powerpc/adder/current/src/adder_eth.c
===================================================================
RCS file: devs/eth/powerpc/adder/current/src/adder_eth.c
diff -N devs/eth/powerpc/adder/current/src/adder_eth.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/adder/current/src/adder_eth.c 25 Nov 2002 20:37:49 -0000
@@ -0,0 +1,279 @@
+//==========================================================================
+//
+// adder_eth.c
+//
+// Ethernet device driver specifics for Analogue & Micro Adder (PPC850)
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####BSDCOPYRIGHTBEGIN####
+//
+// -------------------------------------------
+//
+// Portions of this software may have been derived from OpenBSD or other sources,
+// and are covered by the appropriate copyright disclaimers included herein.
+//
+// -------------------------------------------
+//
+//####BSDCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2002-11-25
+// Purpose:
+// Description: platform driver specifics for A&M Adder
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// Ethernet device driver support for PHY on Adder/MPC850
+
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/diag.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/drv_api.h>
+
+#include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics
+#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
+
+// MII interface
+#define MII_Start 0x40000000
+#define MII_Read 0x20000000
+#define MII_Write 0x10000000
+#define MII_Cmd 0x30000000
+#define MII_Phy(phy) (phy << 23)
+#define MII_Reg(reg) (reg << 18)
+#define MII_TA 0x00020000
+
+// Transceiver mode
+#define PHY_BMCR 0x00 // Register number
+#define PHY_BMCR_RESET 0x8000
+#define PHY_BMCR_LOOPBACK 0x4000
+#define PHY_BMCR_100MB 0x2000
+#define PHY_BMCR_AUTO_NEG 0x1000
+#define PHY_BMCR_POWER_DOWN 0x0800
+#define PHY_BMCR_ISOLATE 0x0400
+#define PHY_BMCR_RESTART 0x0200
+#define PHY_BMCR_FULL_DUPLEX 0x0100
+#define PHY_BMCR_COLL_TEST 0x0080
+
+#define PHY_BMSR 0x01 // Status register
+#define PHY_BMSR_AUTO_NEG 0x0020
+#define PHY_BMSR_LINK 0x0004
+
+// Bits in port D - used for 2 wire MII interface
+#define MII_DATA 0x1000
+#define MII_CLOCK 0x0800
+
+#define MII_SET_DATA(val) \
+ if (val) { \
+ eppc->pio_pddat |= MII_DATA; \
+ } else { \
+ eppc->pio_pddat &= ~MII_DATA; \
+ }
+
+#define MII_GET_DATA() \
+ ((eppc->pio_pddat & MII_DATA) != 0)
+
+#define MII_SET_CLOCK(val) \
+ if (val) { \
+ eppc->pio_pddat |= MII_CLOCK; \
+ } else { \
+ eppc->pio_pddat &= ~MII_CLOCK; \
+ }
+
+static cyg_uint32
+phy_cmd(cyg_uint32 cmd)
+{
+ volatile EPPC *eppc = (volatile EPPC *)eppc_base();
+ cyg_uint32 retval;
+ int i, off;
+ bool is_read = ((cmd & MII_Cmd) == MII_Read);
+
+ // Set both bits as output
+ eppc->pio_pddir |= MII_DATA | MII_CLOCK;
+
+ // Preamble
+ for (i = 0; i < 32; i++) {
+ MII_SET_CLOCK(0);
+ MII_SET_DATA(1);
+ CYGACC_CALL_IF_DELAY_US(1);
+ MII_SET_CLOCK(1);
+ CYGACC_CALL_IF_DELAY_US(1);
+ }
+
+ // Command/data
+ for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
+ MII_SET_CLOCK(0);
+ MII_SET_DATA((cmd >> off) & 0x00000001);
+ CYGACC_CALL_IF_DELAY_US(1);
+ MII_SET_CLOCK(1);
+ CYGACC_CALL_IF_DELAY_US(1);
+ }
+
+ retval = cmd;
+
+ // If read, fetch data register
+ if (is_read) {
+ retval >>= 16;
+
+ MII_SET_CLOCK(0);
+ eppc->pio_pddir &= ~MII_DATA; // Data bit is now input
+ CYGACC_CALL_IF_DELAY_US(1);
+ MII_SET_CLOCK(1);
+ CYGACC_CALL_IF_DELAY_US(1);
+ MII_SET_CLOCK(0);
+ CYGACC_CALL_IF_DELAY_US(1);
+
+ for (i = 0, off = 15; i < 16; i++, off--) {
+ MII_SET_CLOCK(1);
+ retval <<= 1;
+ retval |= MII_GET_DATA();
+ CYGACC_CALL_IF_DELAY_US(1);
+ MII_SET_CLOCK(0);
+ CYGACC_CALL_IF_DELAY_US(1);
+ }
+ }
+
+ // Set both bits as output
+ eppc->pio_pddir |= MII_DATA | MII_CLOCK;
+
+ // Postamble
+ for (i = 0; i < 32; i++) {
+ MII_SET_CLOCK(0);
+ MII_SET_DATA(1);
+ CYGACC_CALL_IF_DELAY_US(1);
+ MII_SET_CLOCK(1);
+ CYGACC_CALL_IF_DELAY_US(1);
+ }
+
+ return retval;
+}
+
+//
+// PHY unit access (via MII channel)
+//
+static void
+phy_write(int reg, int addr, unsigned short data)
+{
+ phy_cmd(MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
+}
+
+static bool
+phy_read(int reg, int addr, unsigned short *val)
+{
+ cyg_uint32 ret;
+
+ ret = phy_cmd(MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA);
+ *val = ret;
+ return true;
+}
+
+bool
+_adder_reset_phy(void)
+{
+ volatile EPPC *eppc = (volatile EPPC *)eppc_base();
+ int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
+ bool phy_ok;
+ unsigned short phy_state = 0;
+ int phy_unit = -1;
+ int i;
+
+ // Reset PHY (transceiver)
+ eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip
+ CYGACC_CALL_IF_DELAY_US(15000); // > 10ms
+ eppc->pip_pbdat |= 0x00004000; // Enable PHY chip
+
+ phy_ok = false;
+
+ // Try and discover how this PHY is wired
+ for (i = 0; i < 0x20; i++) {
+ phy_read(PHY_BMCR, i, &phy_state);
+ if ((phy_state & PHY_BMCR_RESET) == 0) {
+ phy_unit = i;
+ break;
+ }
+ }
+ if (phy_unit < 0) {
+ diag_printf("QUICC ETH - Can't locate PHY\n");
+ return false;
+ } else {
+#if 0
+ diag_printf("QUICC ETH - using PHY %d\n", phy_unit);
+#endif
+ }
+ if (phy_read(PHY_BMSR, phy_unit, &phy_state)) {
+ if ((phy_state & PHY_BMSR_LINK) != PHY_BMSR_LINK) {
+ unsigned short reset_mode;
+ phy_write(PHY_BMCR, phy_unit, PHY_BMCR_RESET);
+ for (i = 0; i < 10; i++) {
+ phy_ok = phy_read(PHY_BMCR, phy_unit, &phy_state);
+ if (!phy_ok) break;
+ if (!(phy_state & PHY_BMCR_RESET)) break;
+ }
+ if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
+ diag_printf("QUICC/ETH: Can't get PHY unit to soft reset: %x\n", phy_state);
+ return false;
+ }
+ reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG | PHY_BMCR_FULL_DUPLEX;
+ phy_write(PHY_BMCR, phy_unit, reset_mode);
+ while (phy_timeout-- >= 0) {
+ phy_ok = phy_read(PHY_BMSR, phy_unit, &phy_state);
+ if (phy_ok && (phy_state & PHY_BMSR_LINK)) {
+ break;
+ } else {
+ CYGACC_CALL_IF_DELAY_US(10000); // 10ms
+ }
+ }
+ if (phy_timeout <= 0) {
+ diag_printf("** QUICC/ETH Warning: PHY LINK UP failed\n");
+ }
+ }
+ else {
+ diag_printf("** QUICC/ETH Info: PHY LINK already UP \n");
+ }
+ }
+
+ return phy_ok;
+}
+
Index: devs/eth/powerpc/mbx/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/mbx/current/ChangeLog
diff -N devs/eth/powerpc/mbx/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/mbx/current/ChangeLog 25 Nov 2002 18:48:21 -0000
@@ -0,0 +1,44 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * include/mbx_eth.inl:
+ * cdl/mbx_eth_drivers.cdl: New package - platform specifics for
+ Motorola MBX (PowerPC 860) board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+
+
Index: devs/eth/powerpc/mbx/current/cdl/mbx_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/mbx/current/cdl/mbx_eth_drivers.cdl
diff -N devs/eth/powerpc/mbx/current/cdl/mbx_eth_drivers.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/mbx/current/cdl/mbx_eth_drivers.cdl 19 Nov 2002 17:08:31 -0000
@@ -0,0 +1,69 @@
+#====================================================================
+#
+# mbx_eth_drivers.cdl
+#
+# Hardware specifics for Motorola MBX ethernet
+#
+#====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas, hmt
+# Original data: gthomas
+# Contributors: gthomas
+# Date: 2001-02-14
+#
+#####DESCRIPTIONEND####
+#
+#====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_MBX {
+ display "Motorola MBX (MPC8xxT) ethernet support"
+ description "Hardware specifics for Motorola MBX ethernet"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_POWERPC
+ active_if CYGPKG_HAL_POWERPC_MPC8xx
+ active_if CYGPKG_HAL_POWERPC_MBX
+
+ requires CYGPKG_DEVS_ETH_POWERPC_QUICC
+
+ include_dir cyg/io
+ define_proc {
+ puts $::cdl_system_header "#define CYGDAT_DEVS_QUICC_ETH_INL <cyg/io/mbx_eth.inl>"
+ }
+}
Index: devs/eth/powerpc/mbx/current/include/mbx_eth.inl
===================================================================
RCS file: devs/eth/powerpc/mbx/current/include/mbx_eth.inl
diff -N devs/eth/powerpc/mbx/current/include/mbx_eth.inl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/mbx/current/include/mbx_eth.inl 25 Nov 2002 23:08:06 -0000
@@ -0,0 +1,99 @@
+#ifndef CYGONCE_DEVS_MBX_ETH_INL
+#define CYGONCE_DEVS_MBX_ETH_INL
+//==========================================================================
+//
+// mbx_eth.inl
+//
+// Hardware specifics for Motorola MBX ethernet support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2002-11-19
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define _get_led()
+#define _set_led(v)
+
+#define LED_TxACTIVE 7
+#define LED_RxACTIVE 6
+#define LED_IntACTIVE 5
+
+#if 0
+// Fetch ESA from on-board EEPROM
+extern int _mbx_fetch_VPD(int, void *, int);
+#define QUICC_ETH_FETCH_ESA(_ok_) \
+ _ok_ = _mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr));
+#endif
+
+// Reset/enable any external hardware
+#define QUICC_ETH_ENABLE() \
+ *MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN; /* Enable ethernet, TP mode */
+
+
+// Port layout - uses SCC1
+#define QUICC_ETH_PA_RXD 0x0001 // Rx Data on Port A
+#define QUICC_ETH_PA_TXD 0x0002 // Tx Data on Port A
+#define QUICC_ETH_PA_Tx_CLOCK 0x0200 // Tx Clock = CLK2
+#define QUICC_ETH_PA_Rx_CLOCK 0x0800 // Rx Clock = CLK4
+#define QUICC_ETH_PC_Tx_ENABLE 0x0001 // Tx Enable (TENA)
+#define QUICC_ETH_PC_COLLISION 0x0010 // Collision detect
+#define QUICC_ETH_PC_Rx_ENABLE 0x0020 // Rx Enable (RENA)
+#define QUICC_ETH_SICR_MASK 0x00FF // SI Clock Route - important bits
+#define QUICC_ETH_SICR_ENET (7<<3)|(5<<0) // Rx=CLK4, Tx=CLK2
+#define QUICC_ETH_SICR_ENABLE 0x0040 // Enable SCC1 to use NMSI
+#define QUICC_ETH_INT CYGNUM_HAL_INTERRUPT_CPM_SCC1
+#define QUICC_ETH_SCC 0 // SCC1
+#define QUICC_CPM_SCCx QUICC_CPM_SCC1
+
+#define MBX_CTL1 (cyg_uint8 *)0xFA100000 // System control register
+#define MBX_CTL1_ETEN 0x80 // 1 = Enable ethernet tranceiver
+#define MBX_CTL1_ELEN 0x40 // 1 = Enable ethernet loopback
+#define MBX_CTL1_EAEN 0x20 // 1 = Auto select ethernet interface
+#define MBX_CTL1_TPEN 0x10 // 0 = AUI, 1 = TPI
+#define MBX_CTL1_FDDIS 0x08 // 1 = Disable full duplex (if TP mode)
+
+
+#endif // CYGONCE_DEVS_MBX_ETH_INL
+// ------------------------------------------------------------------------
Index: devs/eth/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.15
diff -u -5 -p -r1.15 ChangeLog
--- devs/eth/powerpc/quicc/current/ChangeLog 9 Aug 2002 00:15:29 -0000 1.15
+++ devs/eth/powerpc/quicc/current/ChangeLog 25 Nov 2002 18:49:01 -0000
@@ -1,5 +1,10 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * src/quicc_eth.h:
+ * src/if_quicc.c: Split platform specifics into separate packages.
+
2002-08-08 Gary Thomas <gthomas@ecoscentric.com>
2002-08-08 Luoqi Chen <lchen@onetta.com>
* src/if_quicc.c (quicc_eth_send): Need to flush cache to force
out data, not invalidate it.
Index: devs/eth/powerpc/quicc/current/src/if_quicc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c,v
retrieving revision 1.14
diff -u -5 -p -r1.14 if_quicc.c
--- devs/eth/powerpc/quicc/current/src/if_quicc.c 9 Aug 2002 00:15:29 -0000 1.14
+++ devs/eth/powerpc/quicc/current/src/if_quicc.c 25 Nov 2002 20:08:39 -0000
@@ -128,11 +128,32 @@ ETH_DRV_SC(quicc_eth0_sc,
NETDEVTAB_ENTRY(quicc_netdev,
"quicc_eth",
quicc_eth_init,
&quicc_eth0_sc);
-extern int _mbx_fetch_VPD(int, void *, int);
+// LED activity [exclusive of hardware bits]
+#ifndef _get_led
+#define _get_led()
+#define _set_led(v)
+#endif
+#ifndef LED_TxACTIVE
+#define LED_TxACTIVE 7
+#define LED_RxACTIVE 6
+#define LED_IntACTIVE 5
+#endif
+
+static void
+set_led(int bit)
+{
+ _set_led(_get_led() | (1<<bit));
+}
+
+static void
+clear_led(int bit)
+{
+ _set_led(_get_led() & ~(1<<bit));
+}
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
static cyg_interrupt quicc_eth_interrupt;
static cyg_handle_t quicc_eth_interrupt_handle;
#endif
@@ -141,12 +162,12 @@ static void quicc_eth_int(struc
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// This ISR is called when the ethernet interrupt occurs
static int
quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
{
- cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
- cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
+ cyg_drv_interrupt_mask(QUICC_ETH_INT);
+ cyg_drv_interrupt_acknowledge(QUICC_ETH_INT);
return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
}
#endif
// Deliver function (ex-DSR) handles the ethernet [logical] processing
@@ -154,11 +175,11 @@ static void
quicc_eth_deliver(struct eth_drv_sc * sc)
{
quicc_eth_int(sc);
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Allow interrupts to happen again
- cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
+ cyg_drv_interrupt_unmask(QUICC_ETH_INT);
#endif
}
//
// Initialize the interface - performed at system startup
@@ -176,15 +197,17 @@ quicc_eth_init(struct cyg_netdevtab_entr
volatile struct ethernet_pram *enet_pram;
volatile struct scc_regs *scc;
int TxBD, RxBD;
int cache_state;
int i;
- bool esa_ok;
+ bool esa_ok = false;
+
+#ifdef QUICC_ETH_FETCH_ESA
+ QUICC_ETH_FETCH_ESA(esa_ok);
+#endif
- // Fetch the board address from the VPD
-#define VPD_ETHERNET_ADDRESS 0x08
- if (_mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)) == 0) {
+ if (!esa_ok) {
#if defined(CYGPKG_REDBOOT) && \
defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config("quicc_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
@@ -202,41 +225,42 @@ quicc_eth_init(struct cyg_netdevtab_entr
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Set up to handle interrupts
- cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_CPM_SCC1,
+ cyg_drv_interrupt_create(QUICC_ETH_INT,
CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data item passed to interrupt handler
(cyg_ISR_t *)quicc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&quicc_eth_interrupt_handle,
&quicc_eth_interrupt);
cyg_drv_interrupt_attach(quicc_eth_interrupt_handle);
- cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
- cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
+ cyg_drv_interrupt_acknowledge(QUICC_ETH_INT);
+ cyg_drv_interrupt_unmask(QUICC_ETH_INT);
#endif
- qi->pram = enet_pram = &eppc->pram[0].enet_scc;
- qi->ctl = scc = &eppc->scc_regs[0]; // Use SCC1
+ qi->pram = enet_pram = &eppc->pram[QUICC_ETH_SCC].enet_scc;
+ qi->ctl = scc = &eppc->scc_regs[QUICC_ETH_SCC]; // Use SCCx
// Shut down ethernet, in case it is already running
scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
memset((void *)enet_pram, 0, sizeof(*enet_pram));
- TxBD = 0x2C00; // FIXME
- RxBD = TxBD + CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc);
+ TxBD = cyg_hal_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc));
+ RxBD = cyg_hal_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM * sizeof(struct cp_bufdesc));
txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
+ qi->txactive = 0;
RxBUF = &quicc_eth_rxbufs[0][0];
TxBUF = &quicc_eth_txbufs[0][0];
// setup buffer descriptors
@@ -257,26 +281,26 @@ quicc_eth_init(struct cyg_netdevtab_entr
txbd++;
}
txbd--;
txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
- // Set up parallel ports for connection to MC68160 ethernet tranceiver
- eppc->pio_papar |= (QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
- eppc->pio_padir &= ~(QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
- eppc->pio_paodr &= ~QUICC_MBX_PA_TXD;
-
- eppc->pio_pcpar &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
- eppc->pio_pcdir &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
- eppc->pio_pcso |= (QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
+ // Set up parallel ports for connection to ethernet tranceiver
+ eppc->pio_papar |= (QUICC_ETH_PA_RXD | QUICC_ETH_PA_TXD);
+ eppc->pio_padir &= ~(QUICC_ETH_PA_RXD | QUICC_ETH_PA_TXD);
+ eppc->pio_paodr &= ~QUICC_ETH_PA_TXD;
+
+ eppc->pio_pcpar &= ~(QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
+ eppc->pio_pcdir &= ~(QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
+ eppc->pio_pcso |= (QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
- eppc->pio_papar |= (QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
- eppc->pio_padir &= ~(QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
+ eppc->pio_papar |= (QUICC_ETH_PA_Tx_CLOCK | QUICC_ETH_PA_Rx_CLOCK);
+ eppc->pio_padir &= ~(QUICC_ETH_PA_Tx_CLOCK | QUICC_ETH_PA_Rx_CLOCK);
// Set up clock routing
- eppc->si_sicr &= ~QUICC_MBX_SICR_MASK;
- eppc->si_sicr |= QUICC_MBX_SICR_ENET;
- eppc->si_sicr &= ~QUICC_MBX_SICR_SCC1_ENABLE;
+ eppc->si_sicr &= ~QUICC_ETH_SICR_MASK;
+ eppc->si_sicr |= QUICC_ETH_SICR_ENET;
+ eppc->si_sicr &= ~QUICC_ETH_SICR_ENABLE;
// Set up DMA mode
eppc->dma_sdcr = 0x0001;
// Initialize shared PRAM
@@ -337,20 +361,20 @@ quicc_eth_init(struct cyg_netdevtab_entr
enet_pram->taddr_h = 0;
enet_pram->taddr_m = 0;
enet_pram->taddr_l = 0;
// Initialize the CPM (set up buffer pointers, etc).
- eppc->cp_cr = QUICC_CPM_SCC1 | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
+ eppc->cp_cr = QUICC_CPM_SCCx | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
// Clear any pending interrupt/exceptions
scc->scc_scce = 0xFFFF;
// Enable interrupts
scc->scc_sccm = QUICC_SCCE_INTS;
- // Set up SCC1 to run in ethernet mode
+ // Set up SCCx to run in ethernet mode
scc->scc_gsmr_h = 0;
scc->scc_gsmr_l = QUICC_SCC_GSML_TCI | QUICC_SCC_GSML_TPL_48 |
QUICC_SCC_GSML_TPP_01 | QUICC_SCC_GSML_MODE_ENET;
// Sync delimiters
@@ -358,23 +382,37 @@ quicc_eth_init(struct cyg_netdevtab_entr
// Protocol specifics (as if GSML wasn't enough)
scc->scc_psmr = QUICC_PMSR_ENET_CRC | QUICC_PMSR_SEARCH_AFTER_22 |
QUICC_PMSR_RCV_SHORT_FRAMES;
- // Configure board interface
- *MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN; // Enable ethernet, TP mode
+#ifdef QUICC_ETH_ENABLE
+ QUICC_ETH_ENABLE();
+#endif
+
+#ifdef QUICC_ETH_RESET_PHY
+ QUICC_ETH_RESET_PHY();
+#endif
// Enable ethernet interface
- eppc->pio_pcpar |= QUICC_MBX_PC_Tx_ENABLE;
- eppc->pio_pcdir &= ~QUICC_MBX_PC_Tx_ENABLE;
+#ifdef QUICC_ETH_PC_Tx_ENABLE
+ eppc->pio_pcpar |= QUICC_ETH_PC_Tx_ENABLE;
+ eppc->pio_pcdir &= ~QUICC_ETH_PC_Tx_ENABLE;
+#else
+ eppc->pip_pbpar |= QUICC_ETH_PB_Tx_ENABLE;
+ eppc->pip_pbdir |= QUICC_ETH_PB_Tx_ENABLE;
+#endif
if (cache_state)
HAL_DCACHE_ENABLE();
// Initialize upper level driver
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
+ // Set LED state
+ clear_led(LED_TxACTIVE);
+ clear_led(LED_RxACTIVE);
+
return true;
}
//
// This function is called to shut down the interface.
@@ -429,13 +467,12 @@ quicc_eth_control(struct eth_drv_sc *sc,
//
static int
quicc_eth_can_send(struct eth_drv_sc *sc)
{
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
- volatile struct cp_bufdesc *txbd = qi->txbd;
- return ((txbd->ctrl & QUICC_BD_CTL_Ready) == 0);
+ return (qi->txactive < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM);
}
//
// This routine is called to send data to the hardware.
static void
@@ -478,11 +515,11 @@ quicc_eth_send(struct eth_drv_sc *sc, st
bp = txbd->buffer;
for (i = 0; i < sg_len; i++) {
memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
bp += sg_list[i].len;
}
- // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
+ // Note: the MPC8xx does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
if (cache_state) {
HAL_DCACHE_FLUSH(txbd->buffer, txbd->length); // Make sure no stale data
}
// Send it on it's way
@@ -490,10 +527,12 @@ quicc_eth_send(struct eth_drv_sc *sc, st
if (txbd->length < IEEE_8023_MIN_FRAME) {
ctrl |= QUICC_BD_TX_PAD;
}
txbd->ctrl = ctrl | QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int |
QUICC_BD_TX_LAST | QUICC_BD_TX_TC;
+ qi->txactive++;
+ set_led(LED_TxACTIVE);
}
//
// This function is called when a packet has been received. It's job is
// to prepare to unload the packet from the hardware. Once the length of
@@ -508,11 +547,13 @@ quicc_eth_RxEvent(struct eth_drv_sc *sc)
volatile struct cp_bufdesc *rxbd;
rxbd = qi->rnext;
while ((rxbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
qi->rxbd = rxbd; // Save for callback
+ set_led(LED_RxACTIVE);
(sc->funs->eth_drv->recv)(sc, rxbd->length);
+ clear_led(LED_RxACTIVE);
rxbd->ctrl |= QUICC_BD_CTL_Ready;
if (rxbd->ctrl & QUICC_BD_CTL_Wrap) {
rxbd = qi->rbase;
} else {
rxbd++;
@@ -535,11 +576,11 @@ quicc_eth_recv(struct eth_drv_sc *sc, st
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
unsigned char *bp;
int i, cache_state;
bp = (unsigned char *)qi->rxbd->buffer;
- // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
+ // Note: the MPC8xx does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
if (cache_state) {
HAL_DCACHE_INVALIDATE(qi->rxbd->buffer, qi->rxbd->length); // Make sure no stale data
}
for (i = 0; i < sg_len; i++) {
@@ -565,10 +606,13 @@ quicc_eth_TxEvent(struct eth_drv_sc *sc,
if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
txbd = qi->tbase;
} else {
txbd++;
}
+ if (--qi->txactive == 0) {
+ clear_led(LED_TxACTIVE);
+ }
}
// Remember where we left off
qi->tnext = (struct cp_bufdesc *)txbd;
}
@@ -597,7 +641,7 @@ quicc_eth_int(struct eth_drv_sc *sc)
// Interrupt vector
//
static int
quicc_eth_int_vector(struct eth_drv_sc *sc)
{
- return (CYGNUM_HAL_INTERRUPT_CPM_SCC1);
+ return (QUICC_ETH_INT);
}
Index: devs/eth/powerpc/quicc/current/src/quicc_eth.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/src/quicc_eth.h,v
retrieving revision 1.3
diff -u -5 -p -r1.3 quicc_eth.h
--- devs/eth/powerpc/quicc/current/src/quicc_eth.h 23 May 2002 23:00:47 -0000 1.3
+++ devs/eth/powerpc/quicc/current/src/quicc_eth.h 25 Nov 2002 20:01:46 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -70,10 +71,11 @@ struct quicc_eth_info {
volatile struct scc_regs *ctl; // SCC control registers
volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use
struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor
struct cp_bufdesc *tnext, *rnext; // Next descriptor to check for interrupt
int txsize, rxsize; // Length of individual buffers
+ int txactive; // Count of active Tx buffers
unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM];
};
// SCC registers - ethernet mode
@@ -153,27 +155,10 @@ struct quicc_eth_info {
#define QUICC_BD_TX_RL 0x0040 // Retransmit limit exceeded
#define QUICC_BD_TX_RC 0x003C // Retry count
#define QUICC_BD_TX_UN 0x0002 // Tx underrun
#define QUICC_BD_TX_CSL 0x0001 // Carrier lost
-// MBX specific "wiring" - aux connections to MX68160 Ethernet support chip
-#define QUICC_MBX_PA_RXD 0x0001 // Rx Data on Port A
-#define QUICC_MBX_PA_TXD 0x0002 // Tx Data on Port A
-#define QUICC_MBX_PA_Tx_CLOCK 0x0200 // Tx Clock = CLK2
-#define QUICC_MBX_PA_Rx_CLOCK 0x0800 // Rx Clock = CLK4
-#define QUICC_MBX_PC_Tx_ENABLE 0x0001 // Tx Enable (TENA)
-#define QUICC_MBX_PC_COLLISION 0x0010 // Collision detect
-#define QUICC_MBX_PC_Rx_ENABLE 0x0020 // Rx Enable (RENA)
-#define QUICC_MBX_SICR_MASK 0x00FF // SI Clock Route - important bits
-#define QUICC_MBX_SICR_ENET (7<<3)|(5<<0) // Rx=CLK4, Tx=CLK2
-#define QUICC_MBX_SICR_SCC1_ENABLE 0x0040 // Enable SCC1 to use NMSI
-
-#define MBX_CTL1 (cyg_uint8 *)0xFA100000 // System control register
-#define MBX_CTL1_ETEN 0x80 // 1 = Enable ethernet tranceiver
-#define MBX_CTL1_ELEN 0x40 // 1 = Enable ethernet loopback
-#define MBX_CTL1_EAEN 0x20 // 1 = Auto select ethernet interface
-#define MBX_CTL1_TPEN 0x10 // 0 = AUI, 1 = TPI
-#define MBX_CTL1_FDDIS 0x08 // 1 = Disable full duplex (if TP mode)
+#include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics
#define IEEE_8023_MAX_FRAME 1518 // Largest possible ethernet frame
#define IEEE_8023_MIN_FRAME 64 // Smallest possible ethernet frame
Index: devs/flash/amd/am29xxxxx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/amd/am29xxxxx/current/ChangeLog,v
retrieving revision 1.17
diff -u -5 -p -r1.17 ChangeLog
--- devs/flash/amd/am29xxxxx/current/ChangeLog 11 Oct 2002 20:09:24 -0000 1.17
+++ devs/flash/amd/am29xxxxx/current/ChangeLog 25 Nov 2002 23:11:22 -0000
@@ -1,5 +1,13 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * include/flash_am29xxxxx_parts.inl (CYGHWR_DEVS_FLASH_AMD_AM29DL640D):
+ Now tested in 16 bit configurations.
+
+ * include/flash_am29xxxxx.inl: Fix problems with CYGNUM_FLASH_16AS8.
+ The definition was inconsistent/confusing.
+
2002-10-11 Gary Thomas <gary@mlbassoc.com>
* include/flash_am29xxxxx_parts.inl:
* include/flash_am29xxxxx.inl: Better support for devices with
"bootblock" sections - some newer devices have more than one!
Index: devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl,v
retrieving revision 1.16
diff -u -5 -p -r1.16 flash_am29xxxxx.inl
--- devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl 11 Oct 2002 20:09:24 -0000 1.16
+++ devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx.inl 18 Nov 2002 16:18:43 -0000
@@ -87,10 +87,16 @@
#define FLASH_Sector_Erase_Timer FLASHWORD( 0x08 )
#define FLASH_unlocked FLASHWORD( 0x00 )
#ifndef CYGNUM_FLASH_16AS8
+#define _16AS8 0
+#else
+#define _16AS8 CYGNUM_FLASH_16AS8
+#endif
+
+#if (_16AS8 == 0)
# define FLASH_Setup_Addr1 (0x555)
# define FLASH_Setup_Addr2 (0x2AA)
# define FLASH_VendorID_Addr (0)
# define FLASH_DeviceID_Addr (1)
# define FLASH_DeviceID_Addr2 (0x0e)
Index: devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl,v
retrieving revision 1.9
diff -u -5 -p -r1.9 flash_am29xxxxx_parts.inl
--- devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 11 Oct 2002 20:09:24 -0000 1.9
+++ devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 18 Nov 2002 15:39:13 -0000
@@ -478,11 +478,10 @@
},
banked : false
},
#endif
#ifdef CYGHWR_DEVS_FLASH_AMD_AM29LV320D
-#warning *** Untested ***
{ // AM29LV320DT
device_id : FLASHWORD(0x01F6),
block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
block_count: 64,
device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
@@ -500,11 +499,11 @@
_LAST_BOOTBLOCK
},
banked : false
},
{ // AM29LV320D
- device_id : FLASHWORD(0x01F9),
+ device_id : FLASHWORD(0x22F9),
block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
block_count: 64,
device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
bootblock : true,
Index: devs/flash/powerpc/adder/current/ChangeLog
===================================================================
RCS file: devs/flash/powerpc/adder/current/ChangeLog
diff -N devs/flash/powerpc/adder/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/adder/current/ChangeLog 25 Nov 2002 18:49:50 -0000
@@ -0,0 +1,41 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * src/adder_flash.c:
+ * cdl/flash_adder.cdl: New package - platform specific support
+ for Analogue & Micro Adder (PowerPC 850) boards.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/powerpc/adder/current/cdl/flash_adder.cdl
===================================================================
RCS file: devs/flash/powerpc/adder/current/cdl/flash_adder.cdl
diff -N devs/flash/powerpc/adder/current/cdl/flash_adder.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/adder/current/cdl/flash_adder.cdl 25 Nov 2002 20:28:39 -0000
@@ -0,0 +1,74 @@
+# ====================================================================
+#
+# flash_adder.cdl
+#
+# FLASH memory - Hardware support on A&M PowerPC/8xx Adder
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 2001-01-19
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_POWERPC_ADDER {
+ display "A&M Adder (PowerPC/860) FLASH memory support"
+
+ parent CYGPKG_IO_FLASH
+ active_if CYGPKG_IO_FLASH
+ requires CYGPKG_HAL_POWERPC_ADDER
+
+ implements CYGHWR_IO_FLASH_DEVICE
+
+ compile adder_flash.c
+
+ # Arguably this should do in the generic package
+ # but then there is a logic loop so you can never enable it.
+ cdl_interface CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED {
+ display "Generic AMD flash driver required"
+ }
+
+ implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
+ requires CYGHWR_DEVS_FLASH_AMD_AM29LV320D
+
+}
+
Index: devs/flash/powerpc/adder/current/src/adder_flash.c
===================================================================
RCS file: devs/flash/powerpc/adder/current/src/adder_flash.c
diff -N devs/flash/powerpc/adder/current/src/adder_flash.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/adder/current/src/adder_flash.c 25 Nov 2002 18:49:50 -0000
@@ -0,0 +1,74 @@
+//==========================================================================
+//
+// adder_flash.c
+//
+// Flash programming support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2000-10-20
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//--------------------------------------------------------------------------
+// Device properties
+
+#define CYGNUM_FLASH_INTERLEAVE (1)
+#define CYGNUM_FLASH_SERIES (1)
+#define CYGNUM_FLASH_WIDTH (16)
+#define CYGNUM_FLASH_BASE (0xFE000000)
+#define CYGNUM_FLASH_16AS8 (0)
+
+//--------------------------------------------------------------------------
+// Platform specific extras
+#define CYGHWR_FLASH_AM29XXXXX_NO_WRITE_PROTECT // This feature fails :-(
+
+//--------------------------------------------------------------------------
+// Now include the driver code.
+#include "cyg/io/flash_am29xxxxx.inl"
+
+// ------------------------------------------------------------------------
+// EOF adder_flash.c
Index: hal/powerpc/adder/current/ChangeLog
===================================================================
RCS file: hal/powerpc/adder/current/ChangeLog
diff -N hal/powerpc/adder/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/ChangeLog 25 Nov 2002 18:53:58 -0000
@@ -0,0 +1,59 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * src/redboot_linux_exec.c:
+ * src/hal_diag.c:
+ * src/hal_aux.c:
+ * src/adder.S:
+ * misc/redboot_ROMRAM.ecm:
+ * include/pkgconf/mlt_powerpc_adder_romram.mlt:
+ * include/pkgconf/mlt_powerpc_adder_romram.ldi:
+ * include/pkgconf/mlt_powerpc_adder_romram.h:
+ * include/pkgconf/mlt_powerpc_adder_rom.mlt:
+ * include/pkgconf/mlt_powerpc_adder_rom.ldi:
+ * include/pkgconf/mlt_powerpc_adder_rom.h:
+ * include/pkgconf/mlt_powerpc_adder_ram.mlt:
+ * include/pkgconf/mlt_powerpc_adder_ram.ldi:
+ * include/pkgconf/mlt_powerpc_adder_ram.h:
+ * include/plf_stub.h:
+ * include/plf_regs.h:
+ * include/plf_intr.h:
+ * include/plf_cache.h:
+ * include/hal_diag.h:
+ * cdl/hal_powerpc_adder.cdl: New package - platform specifics for
+ Analogue & Micro Adder (PowerPC 850) boards.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
===================================================================
RCS file: hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
diff -N hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 25 Nov 2002 22:15:03 -0000
@@ -0,0 +1,323 @@
+# ====================================================================
+#
+# hal_powerpc_adder.cdl
+#
+# PowerPC/ADDER board HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): jskov
+# Original data: hmt
+# Contributors: gthomas
+# Date: 1999-11-02
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_POWERPC_ADDER {
+ display "A&M ADDER PowerPC evaluation board"
+ parent CYGPKG_HAL_POWERPC
+ requires CYGPKG_HAL_POWERPC_MPC8xx
+ define_header hal_powerpc_adder.h
+ include_dir cyg/hal
+ description "
+ The ADDER HAL package provides the support needed to run
+ eCos on a A&M ADDER board equipped with a PowerPC processor."
+
+ compile hal_diag.c hal_aux.c adder.S
+
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGNUM_HAL_QUICC_SMC2
+ implements CYGNUM_HAL_QUICC_SCC3
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_powerpc_quicc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_adder.h>"
+
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 850\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"A&M ADDER\""
+ puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ legal_values {"RAM" "ROM" "ROMRAM"}
+ default_value {"RAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ This option is used to control where the application program will
+ run, either from RAM or ROM (flash) memory. ROM based applications
+ must be self contained, while RAM applications will typically assume
+ the existence of a debug environment, such as GDB stubs."
+ }
+
+ cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED {
+ display "Development board clock speed (MHz)"
+ flavor data
+ legal_values { 47 }
+ default_value 47
+ description "
+ ADDER Development Boards have various system clock speeds
+ depending on the processor fitted. Select the clock speed
+ appropriate for your board so that the system can set the serial
+ baud rate correctly, amongst other things."
+ }
+
+ # Real-time clock/counter specifics
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants."
+ description "
+ Period is busclock/16/100."
+ flavor none
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ calculated 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ calculated 100
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ calculated { ((((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/4)/16)/100) }
+ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "powerpc-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-msoft-float -mcpu=860 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ description "
+ This option controls the global compiler flags which
+ are used to compile all packages by
+ default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-msoft-float -mcpu=860 -g -nostdlib -Wl,--gc-sections -Wl,-static" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM" }
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the platform CDL takes care of creating
+ an S-Record data file suitable for programming using
+ the board's EPPC-Bug firmware monitor."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) -O srec --change-address=0x02000000 $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGPKG_HAL_POWERPC_ADDER_OPTIONS {
+ display "ADDER build options"
+ flavor none
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+
+ cdl_option CYGPKG_HAL_POWERPC_ADDER_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the ADDER HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_POWERPC_ADDER_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the ADDER HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ cdl_option CYGPKG_HAL_POWERPC_ADDER_TESTS {
+ display "ADDER tests"
+ flavor data
+ no_define
+ calculated { "tests/addertime" }
+ description "
+ This option specifies the set of tests for the ADDER HAL."
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_adder_ram" : \
+ CYG_HAL_STARTUP == "ROMRAM" ? "powerpc_adder_romram" : \
+ "powerpc_adder_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_adder_ram.ldi>" : \
+ CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_powerpc_adder_romram.ldi>" : \
+ "<pkgconf/mlt_powerpc_adder_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_adder_ram.h>" : \
+ CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_powerpc_adder_romram.h>" : \
+ "<pkgconf/mlt_powerpc_adder_rom.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ cdl_option CYGSEM_REDBOOT_HAL_LINUX_BOOT {
+ active_if CYGBLD_BUILD_REDBOOT_WITH_EXEC
+ display "Support booting Linux via RedBoot"
+ flavor bool
+ default_value 1
+ description "
+ This option enables RedBoot to support booting of a Linux kernel."
+
+ compile -library=libextras.a redboot_linux_exec.c
+ }
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+# compile -library=libextras.a redboot_cmds.c
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+}
Index: hal/powerpc/adder/current/include/hal_diag.h
===================================================================
RCS file: hal/powerpc/adder/current/include/hal_diag.h
diff -N hal/powerpc/adder/current/include/hal_diag.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/hal_diag.h 25 Nov 2002 18:50:30 -0000
@@ -0,0 +1,70 @@
+#ifndef CYGONCE_HAL_HAL_DIAG_H
+#define CYGONCE_HAL_HAL_DIAG_H
+
+//=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg
+// Contributors:nickg
+// Date: 1998-03-02
+// Purpose: HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage: #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_HAL_DIAG_H
Index: hal/powerpc/adder/current/include/plf_cache.h
===================================================================
RCS file: hal/powerpc/adder/current/include/plf_cache.h
diff -N hal/powerpc/adder/current/include/plf_cache.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/plf_cache.h 25 Nov 2002 18:50:45 -0000
@@ -0,0 +1,65 @@
+#ifndef CYGONCE_PLF_CACHE_H
+#define CYGONCE_PLF_CACHE_H
+
+//=============================================================================
+//
+// plf_cache.h
+//
+// Platform HAL cache details
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov
+// Date: 2000-01-26
+// Purpose: Platform cache control API
+// Description: The macros defined here provide the platform specific
+// cache control operations / behavior.
+// Usage: Is included via the architecture cache header:
+// #include <cyg/hal/hal_cache.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//---------------------------------------------------------------------------
+// Initial cache enabling - controlled by common CDL
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_PLF_CACHE_H
+// End of plf_cache.h
Index: hal/powerpc/adder/current/include/plf_intr.h
===================================================================
RCS file: hal/powerpc/adder/current/include/plf_intr.h
diff -N hal/powerpc/adder/current/include/plf_intr.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/plf_intr.h 25 Nov 2002 18:51:15 -0000
@@ -0,0 +1,83 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+
+//==========================================================================
+//
+// plf_intr.h
+//
+// A&M Adder platform specific interrupt definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors: jskov
+// Date: 2000-06-13
+// Purpose: Define platform specific interrupt support
+//
+// Usage:
+// #include <cyg/hal/plf_intr.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+//--------------------------------------------------------------------------
+// Control-C support.
+
+// Defined by the quicc driver
+#include <cyg/hal/quicc/quicc_smc1.h>
+
+
+//----------------------------------------------------------------------------
+// Reset.
+
+// The ADDER does not have a watchdog (not one we can easily use for this
+// purpose anyway).
+#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
+
+#define HAL_PLATFORM_RESET_ENTRY 0xfe000100
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_PLF_INTR_H
+// End of plf_intr.h
Index: hal/powerpc/adder/current/include/plf_regs.h
===================================================================
RCS file: hal/powerpc/adder/current/include/plf_regs.h
diff -N hal/powerpc/adder/current/include/plf_regs.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/plf_regs.h 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,60 @@
+#ifndef CYGONCE_HAL_PLF_REGS_H
+#define CYGONCE_HAL_PLF_REGS_H
+
+//==========================================================================
+//
+// plf_regs.h
+//
+// PowerPC 8xx platform CPU definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2002-06-27
+// Purpose:
+// Description: Possibly override any platform assumptions
+//
+// Usage: Included via the variant+architecture register headers:
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#endif // CYGONCE_HAL_PLF_REGS_H
Index: hal/powerpc/adder/current/include/plf_stub.h
===================================================================
RCS file: hal/powerpc/adder/current/include/plf_stub.h
diff -N hal/powerpc/adder/current/include/plf_stub.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/plf_stub.h 25 Nov 2002 18:52:03 -0000
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov
+// Date: 1999-02-12
+// Purpose: Platform HAL stub support for PowerPC/ADDER board.
+// Usage: #include <cyg/hal/plf_stub.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/ppc_stub.h> // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+//----------------------------------------------------------------------------
+// Stub initializer.
+externC void hal_adder_set_led( int val );
+#ifdef CYG_HAL_STARTUP_ROM
+//# define HAL_STUB_PLATFORM_INIT() hal_adder_set_led( 4 )
+// to distinguish eCos stub ROM ready state from either CygMon or app.
+#endif
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.h
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.h
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.h 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,37 @@
+// eCos memory layout - Thu May 30 10:27:39 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x800000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vectors) [];
+#endif
+#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
+#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
+#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
+#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_for_rom) [];
+#endif
+#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom))
+#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x3cd00)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x800000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.ldi
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.ldi
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.ldi 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,31 @@
+// eCos memory layout - Thu May 30 10:27:39 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x800000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
+ CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
+ CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
+ CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x3cd00;
+ SECTION_vectors (ram, ALIGN (0x10), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.mlt
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.mlt
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.mlt
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_ram.mlt 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,17 @@
+version 0
+region ram 0 800000 0 !
+section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
+section reserved_vsr_table 200 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
+section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom !
+section reserved_for_rom 3cd00 10 0 0 0 1 0 1 vectors vectors !
+section vectors 0 10 0 1 0 1 0 1 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 1 0 1 data data !
+section data 0 8 0 1 0 1 0 1 sbss sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.h
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.h
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.h 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,35 @@
+// eCos memory layout - Thu May 30 10:21:41 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x800000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xfe000000)
+#define CYGMEM_REGION_rom_SIZE (0x800000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vectors) [];
+#endif
+#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
+#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
+#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
+#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x800000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.ldi
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.ldi
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.ldi 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,31 @@
+// eCos memory layout - Thu May 30 10:21:41 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x800000
+ rom : ORIGIN = 0xfe000000, LENGTH = 0x800000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_vectors (rom, 0xfe000000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
+ CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
+ CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
+ SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table))
+ SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.mlt
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.mlt
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.mlt
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_rom.mlt 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,17 @@
+version 0
+region ram 0 800000 0 !
+region rom fe000000 800000 1 !
+section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
+section reserved_vsr_table 200 1 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
+section reserved_virtual_table 100 1 0 0 0 1 0 0 data !
+section data 0 10 1 1 0 1 0 0 sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section vectors 0 1 0 1 1 1 1 1 fe000000 fe000000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 0 0 1 data !
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.h
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.h
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.h 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,17 @@
+// eCos memory layout - Thu May 30 10:05:45 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x800000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x800000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.ldi
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.ldi
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.ldi 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,27 @@
+// eCos memory layout - Thu May 30 10:05:45 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0, LENGTH = 0x800000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_vectors (ram, 0, LMA_EQ_VMA)
+ SECTION_text (ram, 0x3400, LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.mlt
===================================================================
RCS file: hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.mlt
diff -N hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.mlt
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/include/pkgconf/mlt_powerpc_adder_romram.mlt 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,13 @@
+version 0
+region ram 0 800000 0 !
+section vectors 0 1 0 1 1 0 1 0 0 0 !
+section text 0 1 0 1 1 1 1 1 3400 3400 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 1 0 1 data data !
+section data 0 8 0 1 0 1 0 1 sbss sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
Index: hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm
===================================================================
RCS file: hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm
diff -N hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm 25 Nov 2002 23:12:38 -0000
@@ -0,0 +1,106 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware adder ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_POWERPC current ;
+ package -hardware CYGPKG_HAL_POWERPC_MPC8xx current ;
+ package -hardware CYGPKG_HAL_POWERPC_ADDER current ;
+ package -hardware CYGPKG_HAL_QUICC current ;
+ package -hardware CYGPKG_DEVS_FLASH_POWERPC_ADDER current ;
+ package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_NS_DNS current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ user_value 0x00030000
+};
+
+cdl_option CYGOPT_REDBOOT_FIS_REDBOOT_BACKUP {
+ user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+ user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV320D {
+ inferred_value 1
+};
+
+
Index: hal/powerpc/adder/current/src/adder.S
===================================================================
RCS file: hal/powerpc/adder/current/src/adder.S
diff -N hal/powerpc/adder/current/src/adder.S
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/src/adder.S 25 Nov 2002 20:31:56 -0000
@@ -0,0 +1,471 @@
+##=============================================================================
+##
+## adder.S
+##
+## ADDER board hardware setup
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): hmt
+## Contributors:hmt, gthomas
+## Date: 1999-06-08
+## Purpose: ADDER board hardware setup
+## Description: This file contains any code needed to initialize the
+## hardware on a ADDER PPC860 board.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/hal/arch.inc> /* register symbols et al */
+#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
+ /* registers, IMM layout... */
+#include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
+
+#------------------------------------------------------------------------------
+# this is controlled with one define for tidiness:
+# (and it is undefined by default)
+
+//#define CYGPRI_RAM_START_PROGRAMS_UPMS
+
+#if defined(CYG_HAL_STARTUP_ROM) \
+ || defined(CYG_HAL_STARTUP_ROMRAM) \
+ || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
+# define CYGPRI_DO_PROGRAM_UPMS
+#endif
+
+/* The intention is that we only set up the UPMs in ROM start, be it actual
+ * ROM application start or Stub ROMs that we built from the same sources.
+ *
+ * The alternative approach - in which we have reliability doubts - is to
+ * program the UPMs with *old* timing data in StubROM start, then
+ * *reprogram* them with *new* timing data in RAM start - and of course
+ * program with *new* timing data in plain ROM application start.
+ * (Re-programming from new to new timing data fails - hence the suspicion
+ * of reprogramming _at_all_, hence this private configuration)
+ *
+ * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
+ * - programming the UPMs exactly once - is obtained. Define it to get the
+ * latter, untrusted behaviour.
+ */
+
+#------------------------------------------------------------------------------
+
+FUNC_START( hal_hardware_init )
+
+ # Throughout this routine, r4 is the base address of the control
+ # registers. r3 and r5 are scratch in general.
+
+ lwi r4,CYGARC_REG_IMM_BASE # base address of control registers
+ mtspr CYGARC_REG_IMMR,r4
+
+#define CACHE_UNLOCKALL 0x0a00
+#define CACHE_DISABLE 0x0400
+#define CACHE_INVALIDATEALL 0x0c00
+#define CACHE_ENABLE 0x0200
+#define CACHE_ENABLEBIT 0x8000
+
+#define CACHE_FORCEWRITETHROUGH 0x0100
+#define CACHE_NOWRITETHROUGH 0x0300
+#define CACHE_CLEAR_LE_SWAP 0x0700
+
+ # DATA CACHE
+ mfspr r3,CYGARC_REG_DC_CST /* clear error bits */
+ lis r3,CACHE_UNLOCKALL
+ sync
+ mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */
+
+ lis r3,CACHE_INVALIDATEALL
+ sync
+ mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */
+
+ lis r3,CACHE_DISABLE
+ sync
+ mtspr CYGARC_REG_DC_CST,r3 /* disable */
+
+ lis r3,CACHE_FORCEWRITETHROUGH
+ sync
+ mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */
+
+ lis r3,CACHE_CLEAR_LE_SWAP
+ sync
+ mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */
+ /* (dunno what this is, but it sounds like a bad thing) */
+
+ # INSTRUCTION CACHE (no writeback modes)
+ mfspr r3,CYGARC_REG_IC_CST /* clear error bits */
+ lis r3,CACHE_UNLOCKALL
+ mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */
+ isync
+ lis r3,CACHE_INVALIDATEALL
+ mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */
+ isync
+ lis r3,CACHE_DISABLE
+ mtspr CYGARC_REG_IC_CST,r3 /* disable */
+ isync
+
+ sync
+
+ /*
+ * SIU Initialization.
+ */
+ lwi r3,0x00610400
+ stw r3,SIUMCR(r4)
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+// Need to set the PC into the FLASH (ROM) before the address map changes
+ lwi r3,10f
+ lwi r5,0xFE000000
+ or r3,r3,r5
+ mtctr r3
+ bctr
+10:
+#endif
+
+ /*
+ * Enable bus monitor. Disable Watchdog timer.
+ */
+ lwi r3,0xffffff88
+ stw r3,SYPCR(r4)
+
+ /*
+ * Clear REFA & REFB. Enable but freeze timebase.
+ */
+ lwi r3,0x0000 // FIXME: should this be 0x0000 or 0x00C2
+ sth r3,TBSCR(r4)
+
+ /*
+ * Unlock some RTC registers (see section 5.11.2)
+ */
+ lwi r3,0x55ccaa33
+ stw r3,RTCSCK(r4)
+ stw r3,RTCK(r4)
+ stw r3,RTSECK(r4)
+ stw r3,RTCALK(r4)
+
+ /*
+ * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
+ */
+ li r3,0x0000 // FIXME: should this be 0x0000 or 0x00C3
+ sth r3,RTCSC(r4)
+
+ /*
+ * Clear periodic timer interrupt status.
+ * Enable periodic timer and stop it on freeze.
+ */
+ li r3,0x0001 // FIXME: should this be 0x0001 or 0x0083
+ sth r3,PISCR(r4)
+
+#ifdef CYGPRI_DO_PROGRAM_UPMS
+ /*
+ * Perform UPM programming by writing to its 64 RAM locations.
+ * Note that UPM initialization must be done before the Bank Register
+ * initialization. Otherwise, system may hang when writing to Bank
+ * Registers in certain cases.
+ */
+ lis r5,__upmtbl_start@h
+ ori r5,r5,__upmtbl_start@l
+ lis r6,__upmtbl_end@h
+ ori r6,r6,__upmtbl_end@l
+ sub r7,r6,r5 /* size of table */
+ srawi r7,r7,2 /* in words */
+
+ li r6,0x00000000 /* Command - OP=Write, UPMA, MAD=0 */
+ 1:
+ lwz r3,0(r5) /* get data from table */
+ stw r3,MDR(r4) /* store the data to MD register */
+ stw r6,MCR(r4) /* issue command to MCR register */
+ addi r5,r5,4 /* next entry in the table */
+ addi r6,r6,1 /* next MAD address */
+ cmpw r6,r7 /* done yet ? */
+ blt 1b
+#endif // CYGPRI_DO_PROGRAM_UPMS
+
+ /*
+ * Set refresh timer prescaler to divide by 8.
+ */
+ li r3,PTP_DIV32
+ sth r3,MPTPR(r4)
+
+ /*
+ * See Table 15-16 MPC860 User's Manual.
+ *
+// Set the value of Machine A Mode Register (MAMR) to $5E802114.
+// Field PTA (bits 0-7) = 94
+// Field PTAE (bit 8) = 1
+// Field AMA (bits 9-11) = 0
+// Field Reserved (bit 12) = 0
+// Field DSA (bits 13-14) = 0
+// Field Reserved (bit 15) = 0
+// Field G0CLA (bits 16-18) = 1
+// Field GPL_A4DIS (bit 19) = 0
+// Field RLFA (bits 20-23) = 1
+// Field WLFA (bits 24-27) = 1
+// Field TLFA (bits 28-31) = 4
+ */
+
+//
+// PTA field is (System Clock in MHz * Refresh rate in us) / Prescale
+// e.g. ((14*3.6864)*62.5)/32 => 100.8 => 101
+//
+#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 47)
+#define PLPRCR_PTX 0x00C // (47MHz/3.6864MHz)-1
+#define MAMR_PTA 94
+#endif
+#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 51)
+#define PLPRCR_PTX 0x00D // (51.6MHz/3.6864MHz)-1
+#define MAMR_PTA 101
+#endif
+#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 55)
+#define PLPRCR_PTX 0x00E // (55.3MHz/3.6864MHz)-1
+#define MAMR_PTA 108
+#endif
+#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 59)
+#define PLPRCR_PTX 0x00F // (58.9MHz/3.6864MHz)-1
+#define MAMR_PTA 116
+#endif
+#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 63)
+#define PLPRCR_PTX 0x010 // (62.7MHz/3.6864MHz)-1
+#define MAMR_PTA 123
+#endif
+//#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF)
+ lwi r3,0x00802114|(MAMR_PTA<<24)
+ stw r3,MAMR(r4)
+ stw r3,MBMR(r4)
+
+ /*
+ * Base Register initialization.
+ */
+
+ /* BOOT ROM */
+ lwi r3,0xFE000801 # 16-bit, GPCM
+ lwi r5,0xFF800774 # 7 wait states, up to 8MB
+ stw r3,BR0(r4)
+ stw r5,OR0(r4)
+
+ /* Misc I/O, 16 bit port */
+ lwi r3,0xFA100801
+ lwi r5,0xFFFF8730
+ stw r3,BR2(r4)
+ stw r5,OR2(r4)
+
+ /* ONBOARD DRAM */
+ lwi r3,0x00000081 # 32-bit, UPMA
+ lwi r5,0xFF800E00
+ stw r3,BR1(r4)
+ stw r5,OR1(r4)
+
+ /* DRAM DIMM BANK1 */
+ lwi r3,0x00000080 # 32-bit, UPMA, INVALID
+ lwi r5,0xFFFF87FC
+ stw r3,BR3(r4)
+ stw r5,OR3(r4)
+
+#if 0
+ /* NVRAM */
+ lwi r3,0xfa000401 # 8-bit, GPCM
+ lwi r5,0xffe00930
+ stw r3,BR4(r4)
+ stw r5,OR4(r4)
+
+ /* PCI BRIDGE MEM/IO */
+ lwi r3,0x80000001 # 32-bit, GPCM
+ lwi r5,0xa0000108
+ stw r3,BR5(r4)
+ stw r5,OR5(r4)
+
+ /* PCI BRIDGE REGISTERS */
+ lwi r3,0xfa210001 # 32-bit, GPCM
+ lwi r5,0xffff0108
+ stw r3,BR6(r4)
+ stw r5,OR6(r4)
+
+ /* FLASH */
+ lwi r3,0xfc000001 # 32-bit, GPCM
+ lwi r5,0xff800940
+ stw r3,BR7(r4)
+ stw r5,OR7(r4)
+#endif
+
+ /*
+ * SYSTEM CLOCK CONTROL REGISTER
+// Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
+// Field Reserved (bit 0) = 0
+// Field COM (bits 1-2) = 0
+// Field Reserved (bits 3-5) = 0
+// Field TBS (bit 6) = 0
+// Field RTDIV (bit 7) = 0
+// Field RTSEL (bit 8) = 0
+// Field CRQEN (bit 9) = 1
+// Field PRQEN (bit 10) = 0
+// Field Reserved (bits 11-12) = 0
+// Field EBDF (bits 13-14) = 0
+// Field Reserved (bits 15-16) = 0
+// Field DFSYNC (bits 17-18) = 0
+// Field DFBRG (bits 19-20) = 0
+// Field DFNL (bits 21-23) = 0
+// Field DFNH (bits 24-26) = 0
+// Field Reserved (bits 27-31) = 0
+ */
+ lwi r3,0x00400000
+ stw r3,SCCR(r4)
+
+ /*
+ * PLL, LOW POWER, AND RESET CONTROL REGISTER
+// Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
+// Field MF (bits 0-11) = 12
+// Field Reserved (bits 12-15) = 0
+// Field SPLSS (bit 16) = 0
+// Field TEXPS (bit 17) = 1
+// Field Reserved (bit 18) = 0
+// Field TMIST (bit 19) = 0
+// Field Reserved (bit 20) = 0
+// Field CSRC (bit 21) = 0
+// Field LPM (bits 22-23) = 0
+// Field CSR (bit 24) = 0
+// Field LOLRE (bit 25) = 0
+// Field FIOPD (bit 26) = 0
+// Field Reserved (bits 27-31) = 0
+ */
+ lwi r3,0x04000|(PLPRCR_PTX<<20)
+ stw r3,PLPRCR(r4)
+
+ lwi r3,0x40000
+ mtctr r3
+10: nop
+ bdnz 10b
+
+ /* SDRAM Initialization Sequence, UPMA, CS1 */
+ li r3,0
+ stw r3,MAR(r4)
+
+ lwi r3,0x80002115; /* run precharge from loc 21 (0x15) */
+ stw r3,MCR(r4)
+
+ lwi r3,0x80002830; /* run refresh 8 times */
+ stw r3,MCR(r4)
+
+ lwi r3,0x88; /* MR 88 for high range */
+ stw r3,MAR(r4)
+
+ lwi r3,0x80002116; /* run MRS pattern from loc 22 (0x16) */
+ stw r3,MCR(r4)
+
+ # mask interrupt sources in the SIU
+ lis r2,0
+ lwi r3,CYGARC_REG_IMM_SIMASK
+ stw r2,0(r3)
+
+ # set the decrementer to maxint
+ lwi r2,0
+ not r2,r2
+ mtdec r2
+
+ # and enable the timebase and decrementer to make sure
+ li r2,1 # TBEnable and not TBFreeze
+ lwi r3,CYGARC_REG_IMM_TBSCR
+ sth r2,0(r3)
+
+#ifdef CYG_HAL_STARTUP_ROM
+ # move return address to where the ROM is
+ mflr r3
+ lwi r4,0x00FFFFFF // CAUTION!! Assumes only low 16M for ROM
+ and r3,r3,r4
+ oris r3,r3,CYGMEM_REGION_rom>>16
+ mtlr r3
+#endif
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+ // Copy image from ROM to RAM
+ mflr r3
+ lwi r4,0xFE000000
+ lwi r5,0x01FFFFFF // ROM/FLASH base
+ and r3,r3,r5 // segment relative
+ lwi r6,_hal_hardware_init_done
+ mtlr r6
+ sub r6,r3,r6 // Absolute address
+ add r6,r6,r4 // FLASH address
+ lwi r7,0 // where to copy to
+ lwi r8,__ram_data_end
+10: lwz r5,0(r6)
+ stw r5,0(r7)
+ addi r6,r6,4
+ addi r7,r7,4
+ cmplw r7,r8
+ bne 10b
+#endif
+
+ blr
+FUNC_END( hal_hardware_init )
+
+
+#ifdef CYGPRI_DO_PROGRAM_UPMS
+# -------------------------------------------------------------------------
+# this table initializes the User Programmable Machine (UPM) nastiness
+# in the QUICC to control DRAM timing.
+
+__upmtbl_start:
+// single read (offset 0x00 in upm ram)
+ .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00
+ .long 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04
+// burst read (offset 0x08 in upm ram)
+ .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00
+ .long 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44
+ .long 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35
+ .long 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35
+// single write (offset 0x18 in upm ram)
+ .long 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47
+ .long 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
+// burst write (offset 0x20 in upm ram)
+ .long 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
+ .long 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04
+ .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
+ .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
+// refresh (offset 0x30 in upm ram)
+ .long 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04
+ .long 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
+ .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
+// exception (offset 0x3C in upm ram)
+ .long 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+__upmtbl_end:
+#endif // CYGPRI_DO_PROGRAM_UPMS
+
+#------------------------------------------------------------------------------
+# end of adder.S
Index: hal/powerpc/adder/current/src/hal_aux.c
===================================================================
RCS file: hal/powerpc/adder/current/src/hal_aux.c
diff -N hal/powerpc/adder/current/src/hal_aux.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/src/hal_aux.c 25 Nov 2002 20:07:45 -0000
@@ -0,0 +1,114 @@
+//=============================================================================
+//
+// hal_aux.c
+//
+// HAL auxiliary objects and code; per platform
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): hmt
+// Contributors:hmt
+// Date: 1999-06-08
+// Purpose: HAL aux objects: startup tables.
+// Description: Tables for per-platform initialization
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_powerpc_quicc.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_mem.h> // HAL memory definitions
+#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#include <cyg/hal/ppc_regs.h>
+#include <cyg/hal/quicc/ppc8xx.h>
+#include <cyg/hal/hal_if.h> // hal_if_init
+#include <cyg/hal/hal_io.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+// The memory map is weakly defined, allowing the application to redefine
+// it if necessary. The regions defined below are the minimum requirements.
+CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
+ // Mapping for the Adder 85x development boards
+ CYGARC_MEMDESC_CACHE( 0xfe000000, 0x00800000 ), // ROM region
+ CYGARC_MEMDESC_NOCACHE( 0xff000000, 0x00100000 ), // MCP registers
+ CYGARC_MEMDESC_NOCACHE( 0xfa000000, 0x00400000 ), // Control/Status+LEDs
+ CYGARC_MEMDESC_CACHE( CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
+
+ CYGARC_MEMDESC_TABLE_END
+};
+
+//--------------------------------------------------------------------------
+// Platform init code.
+void
+hal_platform_init(void)
+{
+ volatile EPPC *eppc = (volatile EPPC *)eppc_base();
+
+ // Special routing information for CICR
+ eppc->cpmi_cicr &= 0xFF0000; // Routing bits
+ eppc->cpmi_cicr |= 0x240000; // SCC2, SCC3 on "normal" bit positions
+
+ eppc->pip_pbpar &= ~0x0000400E; // PB29..30 AS GPIO
+ eppc->pip_pbdir |= 0x0000400E;
+ eppc->pip_pbdat = 0x00004000;
+
+ hal_if_init();
+
+ _adder_set_leds(0x1);
+}
+
+void
+_adder_set_leds(int pat)
+{
+ volatile EPPC *eppc = (volatile EPPC *)eppc_base();
+
+ eppc->pip_pbdat = (eppc->pip_pbdat & ~0x0000000E) | (pat << 1);
+}
+
+int
+_adder_get_leds(void)
+{
+ volatile EPPC *eppc = (volatile EPPC *)eppc_base();
+
+ return ((eppc->pip_pbdat & 0x0000000E) >> 1);
+}
+
+// EOF hal_aux.c
Index: hal/powerpc/adder/current/src/hal_diag.c
===================================================================
RCS file: hal/powerpc/adder/current/src/hal_diag.c
diff -N hal/powerpc/adder/current/src/hal_diag.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/src/hal_diag.c 25 Nov 2002 18:53:48 -0000
@@ -0,0 +1,84 @@
+//=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): hmt
+// Contributors:hmt
+// Date: 1999-06-08
+// Purpose: HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt macros
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#include <cyg/hal/hal_stub.h> // hal_output_gdb_string
+#endif
+
+#include <cyg/hal/ppc_regs.h>
+#include <cyg/hal/quicc/quicc_smc1.h>
+
+
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+ initialized = 1;
+
+ cyg_hal_plf_serial_init(); // Defined in hal/powerpc/quicc/...
+}
+
+// EOF hal_diag.c
Index: hal/powerpc/adder/current/src/redboot_linux_exec.c
===================================================================
RCS file: hal/powerpc/adder/current/src/redboot_linux_exec.c
diff -N hal/powerpc/adder/current/src/redboot_linux_exec.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/adder/current/src/redboot_linux_exec.c 16 Nov 2002 19:42:40 -0000
@@ -0,0 +1,273 @@
+//==========================================================================
+//
+// redboot_linux_boot.c
+//
+// RedBoot command to boot Linux
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####OTHERCOPYRIGHTBEGIN####
+//
+// The structure definitions below are taken from include/ppc/platforms/am860.h in
+// the Linux kernel, Copyright (c) 2002 Gary Thomas, Copyright (c) 1997 Dan Malek.
+// Their presence here is for the express purpose of communication with the Linux
+// kernel being booted and is considered 'fair use' by the original author and
+// are included with their permission.
+//
+//####OTHERCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): msalter
+// Contributors: gthomas,msalter
+// Date: 2002-01-14
+// Purpose:
+// Description:
+//
+// This code is part of RedBoot (tm).
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <redboot.h>
+#include <pkgconf/hal_powerpc_quicc.h>
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+
+#ifdef CYGPKG_REDBOOT_NETWORKING
+#include <net/net.h>
+#endif
+
+#ifdef CYGSEM_REDBOOT_HAL_LINUX_BOOT
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//=========================================================================
+
+// Exported CLI function(s)
+static void do_exec(int argc, char *argv[]);
+RedBoot_cmd("exec",
+ "Execute a Linux image - with MMU off",
+ "[-w timeout]\n"
+ " [-c \"kernel command line\"] [<entry_point>]",
+ do_exec
+ );
+
+//=========================================================================
+// Imported from Linux kernel include/asm-ppc/am860.h
+// Copyright (c) 2002 Gary Thomas (gary@chez-thomas.org)
+// Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+// Used with permission of author(s).
+
+
+/* A Board Information structure that is given to a program when
+ * RedBoot starts it up.
+ */
+typedef struct bd_info {
+ unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
+ unsigned int bi_size; /* Size of this structure */
+ unsigned int bi_revision; /* revision of this structure */
+ unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */
+ unsigned int bi_memstart; /* Memory start address */
+ unsigned int bi_memsize; /* Memory (end) size in bytes */
+ unsigned int bi_intfreq; /* Internal Freq, in Hz */
+ unsigned int bi_busfreq; /* Bus Freq, in Hz */
+ unsigned int bi_clun; /* Boot device controller */
+ unsigned int bi_dlun; /* Boot device logical dev */
+ unsigned char bi_enetaddr[6];
+ unsigned int bi_baudrate;
+ unsigned char *bi_cmdline;
+} bd_t;
+
+//
+// Execute a Linux kernel - this is a RedBoot CLI command
+//
+static void
+do_exec(int argc, char *argv[])
+{
+ unsigned long entry;
+ bool wait_time_set, cmd_line_set;
+ int wait_time;
+ char *cmd_line;
+ char *cline;
+ struct option_info opts[2];
+ hal_virtual_comm_table_t *__chan;
+ int baud_rate;
+
+ bd_t *board_info;
+ CYG_INTERRUPT_STATE oldints;
+ unsigned long sp = CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE;
+
+ init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
+ (void **)&wait_time, (bool *)&wait_time_set, "wait timeout");
+ init_opts(&opts[1], 'c', true, OPTION_ARG_TYPE_STR,
+ (void **)&cmd_line, (bool *)&cmd_line_set, "kernel command line");
+ entry = entry_address; // Default from last 'load' operation
+ if (!scan_opts(argc, argv, 1, opts, 2, (void *)&entry, OPTION_ARG_TYPE_NUM,
+ "[physical] starting address")) {
+ return;
+ }
+
+ // Determine baud rate on current console
+ __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+ baud_rate = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_GETBAUD);
+ if (baud_rate <= 0) {
+ baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+ }
+
+ // Make a little space at the top of the stack, and align to
+ // 64-bit boundary.
+ sp = (sp-128) & ~7; // The Linux boot code uses this space for FIFOs
+
+ // Copy the commandline onto the stack, and set the SP to just below it.
+ if (cmd_line_set) {
+ int len,i;
+
+ // get length of string
+ for( len = 0; cmd_line[len] != '\0'; len++ );
+
+ // decrement sp by length of string and align to
+ // word boundary.
+ sp = (sp-(len+1)) & ~3;
+
+ // assign this SP value to command line start
+ cline = (char *)sp;
+
+ // copy command line over.
+ for( i = 0; i < len; i++ )
+ cline[i] = cmd_line[i];
+ cline[len] = '\0';
+
+ } else {
+ cline = (char *)NULL;
+ }
+
+ // Set up parameter struct at top of stack
+ sp = sp-sizeof(bd_t);
+ board_info = (bd_t *)sp;
+ memset(board_info, sizeof(*board_info), 0);
+
+ board_info->bi_tag = 0x42444944;
+ board_info->bi_size = sizeof(board_info);
+ board_info->bi_revision = 1;
+ board_info->bi_bdate = 0x06012002;
+ board_info->bi_memstart = CYGMEM_REGION_ram;
+ board_info->bi_memsize = CYGMEM_REGION_ram_SIZE;
+ board_info->bi_intfreq = CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000;
+ board_info->bi_busfreq = 66*1000000;
+ board_info->bi_clun = 0; // ????
+ board_info->bi_dlun = 0; // ????
+ board_info->bi_baudrate = baud_rate;
+ board_info->bi_cmdline = cline;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+ memcpy(board_info->bi_enetaddr, __local_enet_addr, sizeof(enet_addr_t));
+#endif
+
+ // adjust SP to 64 bit boundary, and leave a little space
+ // between it and the commandline for PowerPC calling
+ // conventions.
+
+ sp = (sp-32)&~7;
+
+ if (wait_time_set) {
+ int script_timeout_ms = wait_time * 1000;
+#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
+ unsigned char *hold_script = script;
+ script = (unsigned char *)0;
+#endif
+ diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
+ (void *)entry, wait_time);
+ while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
+ int res;
+ char line[80];
+ res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
+ if (res == _GETS_CTRLC) {
+#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
+ script = hold_script; // Re-enable script
+#endif
+ return;
+ }
+ script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
+ }
+ }
+
+ // Disable interrupts
+ HAL_DISABLE_INTERRUPTS(oldints);
+
+ // Put the caches to sleep.
+ HAL_DCACHE_SYNC();
+ HAL_ICACHE_DISABLE();
+ HAL_DCACHE_DISABLE();
+ HAL_DCACHE_SYNC();
+ HAL_ICACHE_INVALIDATE_ALL();
+ HAL_DCACHE_INVALIDATE_ALL();
+
+// diag_printf("entry %08x, sp %08x, info %08x, cmd line %08x, baud %d\n",
+// entry, sp, board_info, cline, baud_rate);
+// breakpoint();
+
+ // Call into Linux
+ __asm__ volatile (
+ // Start by disabling MMU - the mappings are
+ // 1-1 so this should not cause any problems
+ "mfmsr 3\n"
+ "li 4,0xFFFFFFCF\n"
+ "and 3,3,4\n"
+ "sync\n"
+ "mtmsr 3\n"
+ "sync\n"
+
+ // Now set up parameters to jump into linux
+
+ "mtlr %0\n" // set entry address in LR
+ "mr 1,%1\n" // set stack pointer
+ "mr 3,%2\n" // set board info in R3
+ "mr 4,%3\n" // set command line in R4
+ "blr \n" // jump into linux
+ :
+ : "r"(entry),"r"(sp),"r"(board_info),"r"(cline)
+ : "r3", "r4"
+
+ );
+}
+
+#endif // CYGSEM_REDBOOT_HAL_LINUX_BOOT
+
+//=========================================================================
+// EOF redboot_linux_exec.c
Index: hal/powerpc/mbx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mbx/current/ChangeLog,v
retrieving revision 1.29
diff -u -5 -p -r1.29 ChangeLog
--- hal/powerpc/mbx/current/ChangeLog 6 Aug 2002 14:34:06 -0000 1.29
+++ hal/powerpc/mbx/current/ChangeLog 25 Nov 2002 18:54:26 -0000
@@ -1,5 +1,9 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * cdl/hal_powerpc_mbx.cdl: Add new CDL which describes port layout.
+
2002-08-02 Andrew Lunn <Andrew.Lunn@ascom.ch>
* cdl/hal_powerpc_mbx.cdl: Redboot exec command can now be disabled
by CDL
Index: hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl,v
retrieving revision 1.14
diff -u -5 -p -r1.14 hal_powerpc_mbx.cdl
--- hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl 6 Aug 2002 14:34:06 -0000 1.14
+++ hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl 25 Nov 2002 20:25:06 -0000
@@ -7,10 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -62,13 +63,15 @@ cdl_package CYGPKG_HAL_POWERPC_MBX {
compile hal_diag.c hal_aux.c mbx.S
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGNUM_HAL_QUICC_SMC1
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_powerpc_quicc.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_mbx.h>"
puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 860\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Motorola MBX\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
@@ -111,55 +114,10 @@ cdl_package CYGPKG_HAL_POWERPC_MBX {
when booting from the 32-bit flash so that the correct memory
timing and access method is initialized. This consideration
does apply to RAM start eCos applications as well as ROM start
or stub ROMs."
}
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
- display "Number of communication channels on the board"
- flavor data
- calculated 1
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
- display "Debug serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The MBX board has only one serial port. This option
- chooses which port will be used to connect to a host
- running GDB."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Diagnostic serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The MBX board has only one serial port. This option
- chooses which port will be used for diagnostic output."
- }
-
- # This option is only used when USE_ROM_MONITOR is enabled - but
- # it cannot be a sub-option to that option, since the code uses the
- # definition in a preprocessor comparison.
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
- display "Debug serial port used by ROM monitor"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The MBX board has only one serial port. This
- option tells the code which port is in use by the ROM
- monitor. It should only be necessary to change this
- option if a non-standard configurated eCos GDB stub is
- used."
- }
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
description "
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.19
diff -u -5 -p -r1.19 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog 15 Nov 2002 14:32:18 -0000 1.19
+++ hal/powerpc/mpc8xx/current/ChangeLog 25 Nov 2002 18:55:04 -0000
@@ -1,5 +1,9 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * include/var_regs.h: Add CICR definitions.
+
2002-11-15 Gary Thomas <gthomas@ecoscentric.com>
* src/var_misc.c: Change in API for profile callback.
2002-11-14 Gary Thomas <gthomas@ecoscentric.com>
Index: hal/powerpc/mpc8xx/current/include/var_regs.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_regs.h,v
retrieving revision 1.7
diff -u -5 -p -r1.7 var_regs.h
--- hal/powerpc/mpc8xx/current/include/var_regs.h 27 Jun 2002 20:27:19 -0000 1.7
+++ hal/powerpc/mpc8xx/current/include/var_regs.h 25 Nov 2002 18:55:05 -0000
@@ -10,10 +10,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -329,10 +330,12 @@
#define CYGARC_REG_IMM_CICR (CYGARC_REG_IMM_BASE + 0x940)
#define CYGARC_REG_IMM_CICR_IEN 0x00000080 // interrupt enable
#define CYGARC_REG_IMM_CICR_IRQMASK 0x0000e000 // irq priority mask
#define CYGARC_REG_IMM_CICR_IRQ_SHIFT 13
+// CPM interrupt in-pending register
+#define CYGARC_REG_IMM_CIPR (CYGARC_REG_IMM_BASE + 0x944)
// CPM interrupt mask register
#define CYGARC_REG_IMM_CIMR (CYGARC_REG_IMM_BASE + 0x948)
// CPM interrupt in-service register
#define CYGARC_REG_IMM_CISR (CYGARC_REG_IMM_BASE + 0x94C)
Index: hal/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.24
diff -u -5 -p -r1.24 ChangeLog
--- hal/powerpc/quicc/current/ChangeLog 18 Jul 2002 16:00:36 -0000 1.24
+++ hal/powerpc/quicc/current/ChangeLog 25 Nov 2002 18:56:02 -0000
@@ -1,5 +1,12 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * src/quicc_smc1.c: Support any combination of SMC1/SMC2 and
+ SCC1/SCC2/SCC3 [or at least lay foundation for it]
+
+ * cdl/hal_powerpc_quicc.cdl: Add more controls over port layout.
+
2002-07-18 Gary Thomas <gary@chez-thomas.org>
* src/quicc_smc1.c (cyg_hal_scc1_init_channel): Fix init which
failed from power-up - wrong channel in CP command!
Index: hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl,v
retrieving revision 1.6
diff -u -5 -p -r1.6 hal_powerpc_quicc.cdl
--- hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl 11 Jul 2002 16:39:24 -0000 1.6
+++ hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl 25 Nov 2002 20:19:24 -0000
@@ -57,22 +57,91 @@ cdl_package CYGPKG_HAL_QUICC {
include_dir cyg/hal/quicc
description "
The QUICC package provides some of the support needed
to run eCos on a Motorola MPC8xx (MBX) board, using the QUICC
feature of the MPC860 and MPC821 CPUs.
- Currently only serial IO via SMC1 and SCC1 is provided by
+ Currently only serial IO via SMC1/2 and SCC1 is provided by
this package."
+ cdl_interface CYGNUM_HAL_QUICC_SMC1 {
+ display "SMC1 is available for serial I/O"
+ description "
+ This interface indicates that SMC1 can be outfitted as
+ a serial device."
+ }
+
+ cdl_interface CYGNUM_HAL_QUICC_SMC2 {
+ display "SMC2 is available for serial I/O"
+ description "
+ This interface indicates that SMC2 can be outfitted as
+ a serial device."
+ }
+
cdl_interface CYGNUM_HAL_QUICC_SCC1 {
display "SCC1 is available for serial I/O"
description "
Most MPC8xx chipsets use SCC1 to drive the ethernet controller.
On some newer (e.g. 860T) chips, SCC1 can be used for general
serial since there is a separate ethernet machine."
}
+ cdl_interface CYGNUM_HAL_QUICC_SCC2 {
+ display "SCC2 is available for serial I/O"
+ description "
+ Port SCC2 is available for serial I/O"
+ }
+
+ cdl_interface CYGNUM_HAL_QUICC_SCC3 {
+ display "SCC3 is available for serial I/O"
+ description "
+ Port SCC3 is available for serial I/O"
+ }
+
compile quicc_smc1.c
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated CYGNUM_HAL_QUICC_SMC1+CYGNUM_HAL_QUICC_SMC2+CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option chooses which port will be used to connect to a host
+ via the GDB remote protocol."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option chooses which port will be used for diagnostic output."
+ }
+
+ # This option is only used when USE_ROM_MONITOR is enabled - but
+ # it cannot be a sub-option to that option, since the code uses the
+ # definition in a preprocessor comparison.
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
+ display "Debug serial port used by ROM monitor"
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ If a platform has multiple serial ports, then this
+ option tells the code which port is in use by the ROM
+ monitor. It should only be necessary to change this
+ option if a non-standard configurated eCos GDB stub is
+ used."
+ }
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
display "Baud rate for the HAL diagnostic port"
flavor data
legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
Index: hal/powerpc/quicc/current/include/ppc8xx.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/include/ppc8xx.h,v
retrieving revision 1.10
diff -u -5 -p -r1.10 ppc8xx.h
--- hal/powerpc/quicc/current/include/ppc8xx.h 11 Oct 2002 20:09:25 -0000 1.10
+++ hal/powerpc/quicc/current/include/ppc8xx.h 25 Nov 2002 19:49:38 -0000
@@ -105,10 +105,12 @@
#define PAODR 0x954 /* Port A - Open Drain Control */
#define PADAT 0x956 /* Port A - Data */
#else
+#include <cyg/infra/cyg_type.h>
+
/*****************************************************************
Communications Processor Buffer Descriptor
*****************************************************************/
struct cp_bufdesc {
volatile unsigned short ctrl; /* status/control register */
@@ -932,10 +934,16 @@ static inline EPPC *eppc_base(void)
: /* no inputs */ );
return retval;
}
+
+// Function used to allocate space in shared memory area
+// typically used for buffer descriptors, etc.
+__externC unsigned short cyg_hal_allocBd(int len);
+
+#define QUICC_BD_BASE 0x2000 // Start of shared memory
#endif /* __ASSEMBLER__ */
/* Memory Periodic Timer Prescaler Register values */
Index: hal/powerpc/quicc/current/src/quicc_smc1.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c,v
retrieving revision 1.21
diff -u -5 -p -r1.21 quicc_smc1.c
--- hal/powerpc/quicc/current/src/quicc_smc1.c 18 Jul 2002 16:00:37 -0000 1.21
+++ hal/powerpc/quicc/current/src/quicc_smc1.c 25 Nov 2002 20:34:46 -0000
@@ -1,10 +1,10 @@
//==========================================================================
//
// quicc_smc1.c
//
-// PowerPC QUICC basic Serial IO using port SMC1/SCC1
+// PowerPC QUICC basic Serial IO using port(s) SMC1/SMC2/SCC1/SCC2/SCC3
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
@@ -44,15 +44,13 @@
// Author(s): Red Hat
// Contributors: hmt, gthomas
// Date: 1999-06-08
// Purpose: Provide basic Serial IO for MPC8xx boards (like Motorola MBX)
// Description: Serial IO for MPC8xx boards which connect their debug channel
-// to SMC1 or SCC1; or any QUICC user who wants to use SMC1/SCC1
+// to SMCx or SCCx; or any QUICC user who wants to use SMCx/SCCx
// Usage:
-// Notes: The driver hooks itself up on procs channel 0. This should
-// probably be made configurable, allowing the platform
-// to specify location.
+// Notes:
//
//####DESCRIPTIONEND####
//
//==========================================================================
@@ -80,34 +78,54 @@
#define UART_BAUD_RATE CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
// Note: buffers will be placed just after descriptors
// Sufficient space should be provided between descrptors
// for the buffers (single characters)
+
struct port_info {
- int Txbd; // Offset to Tx descriptors
int Txnum; // Number of Tx buffers
- int Rxbd; // Offset to Rx descriptors
int Rxnum; // Number of Rx buffers
int intnum; // Interrupt bit
int timeout; // Timeout in msec
int pram; // [Pointer] to PRAM data
int regs; // [Pointer] to control registers
volatile struct cp_bufdesc *next_rxbd;
int irq; // Interrupt state
+ int init; // Has port been initialized?
};
static struct port_info ports[] = {
- { 0x2800, 1, 0x2810, 4, CYGNUM_HAL_INTERRUPT_CPM_SMC1, 1000,
+#if CYGNUM_HAL_QUICC_SMC1 > 0
+ { 1, 4, CYGNUM_HAL_INTERRUPT_CPM_SMC1, 1000,
(int)&((EPPC *)0)->pram[2].scc.pothers.smc_modem.psmc.u,
(int)&((EPPC *)0)->smc_regs[0]
},
+#endif
+#if CYGNUM_HAL_QUICC_SMC2 > 0
+ { 1, 4, CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP, 1000,
+ (int)&((EPPC *)0)->pram[3].scc.pothers.smc_modem.psmc.u,
+ (int)&((EPPC *)0)->smc_regs[1]
+ },
+#endif
#if CYGNUM_HAL_QUICC_SCC1 > 0
- { 0x2700, 1, 0x2710, 4, CYGNUM_HAL_INTERRUPT_CPM_SCC1, 1000,
+ { 1, 4, CYGNUM_HAL_INTERRUPT_CPM_SCC1, 1000,
(int)&((EPPC *)0)->pram[0].scc.pscc.u,
(int)&((EPPC *)0)->scc_regs[0]
},
#endif
+#if CYGNUM_HAL_QUICC_SCC2 > 0
+ { 1, 4, CYGNUM_HAL_INTERRUPT_CPM_SCC2, 1000,
+ (int)&((EPPC *)0)->pram[1].scc.pscc.u,
+ (int)&((EPPC *)0)->scc_regs[1]
+ },
+#endif
+#if CYGNUM_HAL_QUICC_SCC3 > 0
+ { 1, 4, CYGNUM_HAL_INTERRUPT_CPM_SCC3, 1000,
+ (int)&((EPPC *)0)->pram[2].scc.pscc.u,
+ (int)&((EPPC *)0)->scc_regs[2]
+ },
+#endif
};
// SMC Events (interrupts)
#define QUICC_SMCE_BRK 0x10 // Break received
#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
@@ -115,10 +133,13 @@ static struct port_info ports[] = {
#define QUICC_SMCE_RX 0x01 // Rx interrupt
/*
* Reset the communications processor
*/
+
+static short nextBd;
+
static void
reset_cpm(void)
{
EPPC *eppc = eppc_base();
int i;
@@ -126,59 +147,103 @@ reset_cpm(void)
if (init_done) return;
init_done++;
eppc->cp_cr = QUICC_CPM_CR_RESET | QUICC_CPM_CR_BUSY;
+ memset(eppc->pram, 0, 0x400);
for (i = 0; i < 100000; i++);
+ nextBd = QUICC_BD_BASE;
+
+}
+
+//
+// Allocate a chunk of memory in the shared CPM memory, typically
+// used for buffer descriptors, etc. The length will be aligned
+// to a multiple of 8 bytes.
+//
+unsigned short
+cyg_hal_allocBd(int len)
+{
+ unsigned short bd = nextBd;
+
+ len = (len + 7) & ~7; // Multiple of 8 bytes
+ nextBd += len;
+ return bd;
}
/*
- * Initialize SMC1 as a uart.
+ * Initialize SMCX as a uart.
*
* Comments below reference Motorola's "MPC860 User Manual".
* The basic initialization steps are from Section 16.15.8
* of that manual.
*/
static void
-cyg_hal_smc1_init_channel(struct port_info *info)
+cyg_hal_smcx_init_channel(struct port_info *info, int port)
{
EPPC *eppc = eppc_base();
int i;
volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
struct cp_bufdesc *txbd, *rxbd;
- static int init_done = 0;
- if (init_done) return;
- init_done++;
+ if (info->init) return;
+ info->init = 1;
reset_cpm();
- /*
- * Set up the PortB pins for UART operation.
- * Set PAR and DIR to allow SMCTXD1 and SMRXD1
- * (Table 16-39)
- */
- eppc->pip_pbpar |= 0xc0;
- eppc->pip_pbdir &= ~0xc0;
-
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
-
- /*
- * NMSI mode, BRG1 to SMC1
- * (Section 16.12.5.2)
- */
- eppc->si_simode = 0;
+ switch (port) {
+#if CYGNUM_HAL_QUICC_SMC1 > 0
+ case QUICC_CPM_SMC1:
+ /*
+ * Set up the PortB pins for UART operation.
+ * Set PAR and DIR to allow SMCTXD1 and SMRXD1
+ * (Table 16-39)
+ */
+ eppc->pip_pbpar |= 0xc0;
+ eppc->pip_pbdir &= ~0xc0;
+
+ /* Configure baud rate generator (Section 16.13.2) */
+ eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
+ /*
+ * NMSI mode, BRG1 to SMC1
+ * (Section 16.12.5.2)
+ */
+ eppc->si_simode = 0;
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SMC2 > 0
+ case QUICC_CPM_SMC2:
+ /*
+ * Set up the PortA pins for UART operation.
+ * Set PAR and DIR to allow SMCTXD2 and SMRXD2
+ * (Table 16-39)
+ */
+ eppc->pio_papar |= 0xc0;
+ eppc->pio_padir &= ~0xc0;
+ eppc->pio_paodr &= ~0xc0;
+
+ /* Configure baud rate generator (Section 16.13.2) */
+ eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
+ /*
+ * NMSI mode, BRG1 to SMC2
+ * (Section 16.12.5.2)
+ */
+ eppc->si_simode = 0x00000000;
+ break;
+#endif
+ }
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
- uart_pram->rbase = info->Rxbd;
- uart_pram->tbase = info->Txbd;
+ uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+ uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
/*
* SDMA & LCD bus request level 5
* (Section 16.10.2.1)
*/
@@ -205,29 +270,25 @@ cyg_hal_smc1_init_channel(struct port_in
/* 1 break char sent on top XMIT */
uart_pram->brkcr = 1;
/* setup RX buffer descriptors */
- rxbd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
+ rxbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
info->next_rxbd = rxbd;
for (i = 0; i < info->Rxnum; i++) {
rxbd->length = 0;
- rxbd->buffer = ((char *)eppc + (info->Rxbd+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
+ rxbd->buffer = ((char *)eppc + (uart_pram->rbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
- if (i == ((info->Rxnum)-1)) {
- rxbd->ctrl |= QUICC_BD_CTL_Wrap;
- }
rxbd++;
}
- // Compiler bug: for whatever reason, the Wrap code above fails!
- rxbd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
- rxbd[(info->Rxnum)-1].ctrl |= QUICC_BD_CTL_Wrap;
+ rxbd--;
+ rxbd->ctrl |= QUICC_BD_CTL_Wrap;
/* setup TX buffer descriptor */
- txbd = (struct cp_bufdesc *)((char *)eppc + info->Txbd);
+ txbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
txbd->length = 1;
- txbd->buffer = ((char *)eppc + (info->Txbd+(info->Txnum*sizeof(struct cp_bufdesc))));
+ txbd->buffer = ((char *)eppc + (uart_pram->tbase+(info->Txnum*sizeof(struct cp_bufdesc))));
txbd->ctrl = 0x2000;
/*
* Clear any previous events. Mask interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
@@ -241,20 +302,15 @@ cyg_hal_smc1_init_channel(struct port_in
*/
regs->smc_smcmr = 0x4820;
regs->smc_smcmr = 0x4823;
/*
- * Init Rx & Tx params for SMC1
+ * Init Rx & Tx params for SMCx
*/
- eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_SMC1 | QUICC_CPM_CR_BUSY;
+ eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | port | QUICC_CPM_CR_BUSY;
info->irq = 0; // Interrupts not enabled
-#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // remove below
-#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
- HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_CPM_SMC1 );
-#endif
-#endif
}
//#define UART_BUFSIZE 32
@@ -269,11 +325,11 @@ cyg_hal_smc1_init_channel(struct port_in
#ifdef CYGDBG_DIAG_BUF
extern int enable_diag_uart;
#endif // CYGDBG_DIAG_BUF
static void
-cyg_hal_smc1_putc(void* __ch_data, cyg_uint8 ch)
+cyg_hal_smcx_putc(void* __ch_data, cyg_uint8 ch)
{
volatile struct cp_bufdesc *bd, *first;
EPPC *eppc = eppc_base();
struct port_info *info = (struct port_info *)__ch_data;
volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
@@ -365,11 +421,11 @@ cyg_hal_sxx_getc_nonblock(void* __ch_dat
bd->length = 0;
bd->buffer[0] = '\0';
bd->ctrl |= QUICC_BD_CTL_Ready;
if (bd->ctrl & QUICC_BD_CTL_Wrap) {
- bd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
+ bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
} else {
bd++;
}
info->next_rxbd = bd;
@@ -398,17 +454,17 @@ cyg_hal_sxx_getc(void* __ch_data)
return ch;
}
static void
-cyg_hal_smc1_write(void* __ch_data, const cyg_uint8* __buf,
+cyg_hal_smcx_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
- cyg_hal_smc1_putc(__ch_data, *__buf++);
+ cyg_hal_smcx_putc(__ch_data, *__buf++);
CYGARC_HAL_RESTORE_GP();
}
/*
@@ -495,17 +551,18 @@ cyg_hal_sxx_control(void *__ch_data, __c
/*
* Low-level interrupt (ISR) handler
* This function can be called on only an SMC port
*/
static int
-cyg_hal_smc1_isr(void *__ch_data, int* __ctrlc,
+cyg_hal_smcx_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
EPPC *eppc = eppc_base();
volatile struct cp_bufdesc *bd;
struct port_info *info = (struct port_info *)__ch_data;
volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
+ volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
char ch;
int res = 0;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
@@ -521,11 +578,11 @@ cyg_hal_smc1_isr(void *__ch_data, int* _
// then there be a character waiting
ch = bd->buffer[0];
bd->length = 1;
bd->ctrl |= QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
if (bd->ctrl & QUICC_BD_CTL_Wrap) {
- bd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
+ bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
} else {
bd++;
}
info->next_rxbd = bd;
@@ -540,63 +597,119 @@ cyg_hal_smc1_isr(void *__ch_data, int* _
CYGARC_HAL_RESTORE_GP();
return res;
}
-#if CYGNUM_HAL_QUICC_SCC1 > 0
+#if (CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3) > 0
/*
- * Initialize SCC1 as a uart.
+ * Initialize an SCC as a uart.
*
* Comments below reference Motorola's "MPC860 User Manual".
* The basic initialization steps are from Section 16.15.8
* of that manual.
*/
static void
-cyg_hal_scc1_init_channel(struct port_info *info)
+cyg_hal_sccx_init_channel(struct port_info *info, int port)
{
EPPC *eppc = eppc_base();
int i;
volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram);
volatile struct scc_regs *regs = (volatile struct scc_regs *)((char *)eppc + info->regs);
struct cp_bufdesc *txbd, *rxbd;
- static int init_done = 0;
- if (init_done) return;
- init_done++;
+ if (info->init) return;
+ info->init = 1;
reset_cpm();
/*
- * Set up the PortA pins for UART operation.
+ * Set up the Port pins for UART operation.
*/
- eppc->pio_papar |= 0x03;
- eppc->pio_padir &= ~0x03;
- eppc->pio_paodr &= ~0x03;
-
- /* CTS on PortC.11 */
- eppc->pio_pcdir &= 0x800;
- eppc->pio_pcpar &= 0x800;
- eppc->pio_pcso |= 0x800;
-
- /* RTS on PortB.19 */
- eppc->pip_pbpar |= 0x1000;
- eppc->pip_pbdir |= 0x1000;
-
- /* Configure baud rate generator (Section 16.13.2) */
- eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+ switch (port) {
+#if CYGNUM_HAL_QUICC_SCC1 > 0
+ case QUICC_CPM_SCC1:
+ eppc->pio_papar |= 0x03;
+ eppc->pio_padir &= ~0x03;
+ eppc->pio_paodr &= ~0x03;
+
+ /* CTS on PortC.11 */
+ eppc->pio_pcdir &= 0x800;
+ eppc->pio_pcpar &= 0x800;
+ eppc->pio_pcso |= 0x800;
+
+ /* RTS on PortB.19 */
+ eppc->pip_pbpar |= 0x1000;
+ eppc->pip_pbdir |= 0x1000;
+
+ /* Configure baud rate generator (Section 16.13.2) */
+ eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
+ /*
+ * NMSI mode, BRG2 to SCC1
+ */
+ eppc->si_sicr |= (1<<3)|(1<<0);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SCC2 > 0
+ case QUICC_CPM_SCC2:
+#error FIXME
+ eppc->pio_papar |= 0x03;
+ eppc->pio_padir &= ~0x03;
+ eppc->pio_paodr &= ~0x03;
+
+ /* CTS on PortC.11 */
+ eppc->pio_pcdir &= 0x800;
+ eppc->pio_pcpar &= 0x800;
+ eppc->pio_pcso |= 0x800;
+
+ /* RTS on PortB.19 */
+ eppc->pip_pbpar |= 0x1000;
+ eppc->pip_pbdir |= 0x1000;
+
+ /* Configure baud rate generator (Section 16.13.2) */
+ eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
+ /*
+ * NMSI mode, BRG2 to SCC1
+ */
+ eppc->si_sicr |= (1<<3)|(1<<0);
+ break;
+#endif
+#if CYGNUM_HAL_QUICC_SCC3 > 0
+ case QUICC_CPM_SCC3:
+#if 0
+// CAUTION! Enabling these bits made the port get stuck :-(
+ /* CTS/RTS/CD on PortC.4/5/13 */
+ eppc->pio_pcdir &= 0x0C04;
+ eppc->pio_pcpar &= 0x0C00;
+// eppc->pio_pcpar |= 0x0004;
+ eppc->pio_pcso |= 0x0C00;
+#endif
- /*
- * NMSI mode, BRG2 to SCC1
- */
- eppc->si_simode = 0;
- eppc->si_sicr = (1<<3)|(1<<0);
+ /* RxD/TxD on PortB.24/25 */
+ eppc->pip_pbpar |= 0x00C0;
+ eppc->pip_pbdir |= 0x00C0;
+ eppc->pip_pbodr &= ~0x00C0;
+
+ /* Configure baud rate generator (Section 16.13.2) */
+ eppc->brgc4 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
+
+ /*
+ * NMSI mode, BRG4 to SCC3
+ */
+ eppc->si_sicr &= ~(0xFF << 16);
+ eppc->si_sicr |= (3<<19)|(3<<16);
+ break;
+#endif
+ }
/*
* Set pointers to buffer descriptors.
*/
- uart_pram->rbase = info->Rxbd;
- uart_pram->tbase = info->Txbd;
+ memset((void *)uart_pram, 0xFF, 0x100);
+ uart_pram->rbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
+ uart_pram->tbase = cyg_hal_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
/*
* SDMA & LCD bus request level 5
*/
eppc->dma_sdcr = 1;
@@ -623,62 +736,60 @@ cyg_hal_scc1_init_channel(struct port_in
uart_pram->brkcr = 1;
/* character mask */
uart_pram->rccm = 0xC0FF;
+ /* control characters */
+ for (i = 0; i < 8; i++) {
+ uart_pram->cc[i] = 0x8000; // Mark unused
+ }
+
/* setup RX buffer descriptors */
- rxbd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
+ rxbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
info->next_rxbd = rxbd;
for (i = 0; i < info->Rxnum; i++) {
rxbd->length = 0;
- rxbd->buffer = ((char *)eppc + (info->Rxbd+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
+ rxbd->buffer = ((char *)eppc + (uart_pram->rbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
- if (i == ((info->Rxnum)-1)) {
- rxbd->ctrl |= QUICC_BD_CTL_Wrap;
- }
rxbd++;
}
- // Compiler bug: for whatever reason, the Wrap code above fails!
- rxbd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
- rxbd[(info->Rxnum)-1].ctrl |= QUICC_BD_CTL_Wrap;
+ rxbd--;
+ rxbd->ctrl |= QUICC_BD_CTL_Wrap;
/* setup TX buffer descriptor */
- txbd = (struct cp_bufdesc *)((char *)eppc + info->Txbd);
- txbd->length = 1;
- txbd->buffer = ((char *)eppc + (info->Txbd+(info->Txnum*sizeof(struct cp_bufdesc))));
+ txbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
+ txbd->length = 0;
+ txbd->buffer = ((char *)eppc + (uart_pram->tbase+(info->Txnum*sizeof(struct cp_bufdesc))));
txbd->ctrl = 0x2000;
/*
- * Init Rx & Tx params for SCC1
- */
- eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_SCC1 | QUICC_CPM_CR_BUSY;
-
- /*
* Clear any previous events. Mask interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
- regs->scc_scce = 0xff;
+ regs->scc_scce = 0xffff;
regs->scc_sccm = 5;
+ regs->scc_sccm = 3;
/*
* Set 8,n,1 characters
*/
regs->scc_psmr = (3<<12);
regs->scc_gsmr_h = 0x20; // 8bit FIFO
regs->scc_gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART
+
+ /*
+ * Init Rx & Tx params for SCCX
+ */
+ eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | port | QUICC_CPM_CR_BUSY;
+
regs->scc_gsmr_l |= 0x30; // Enable Rx, Tx
info->irq = 0;
-#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // remove below
-#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
- HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_CPM_SCC1 );
-#endif
-#endif
}
static void
-cyg_hal_scc1_putc(void* __ch_data, cyg_uint8 ch)
+cyg_hal_sccx_putc(void* __ch_data, cyg_uint8 ch)
{
volatile struct cp_bufdesc *bd, *first;
EPPC *eppc = eppc_base();
struct port_info *info = (struct port_info *)__ch_data;
volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram);
@@ -703,39 +814,40 @@ cyg_hal_scc1_putc(void* __ch_data, cyg_u
// This buffer has just completed interrupt output. Reset bits
bd->ctrl &= ~QUICC_BD_CTL_Int;
bd->length = 0;
}
+ bd->length = 0;
bd->buffer[bd->length++] = ch;
bd->ctrl |= QUICC_BD_CTL_Ready;
while (bd->ctrl & QUICC_BD_CTL_Ready) ; // Wait until buffer free
- bd->length = 0;
CYGARC_HAL_RESTORE_GP();
}
static void
-cyg_hal_scc1_write(void* __ch_data, const cyg_uint8* __buf,
+cyg_hal_sccx_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
- cyg_hal_scc1_putc(__ch_data, *__buf++);
+ cyg_hal_sccx_putc(__ch_data, *__buf++);
CYGARC_HAL_RESTORE_GP();
}
static int
-cyg_hal_scc1_isr(void *__ch_data, int* __ctrlc,
+cyg_hal_sccx_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
EPPC *eppc = eppc_base();
volatile struct cp_bufdesc *bd;
struct port_info *info = (struct port_info *)__ch_data;
volatile struct scc_regs *regs = (volatile struct scc_regs *)((char *)eppc + info->regs);
+ volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram);
char ch;
int res = 0;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
@@ -751,11 +863,11 @@ cyg_hal_scc1_isr(void *__ch_data, int* _
// then there be a character waiting
ch = bd->buffer[0];
bd->length = 1;
bd->ctrl |= QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
if (bd->ctrl & QUICC_BD_CTL_Wrap) {
- bd = (struct cp_bufdesc *)((char *)eppc + info->Rxbd);
+ bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
} else {
bd++;
}
info->next_rxbd = bd;
@@ -769,11 +881,11 @@ cyg_hal_scc1_isr(void *__ch_data, int* _
}
CYGARC_HAL_RESTORE_GP();
return res;
}
-#endif // CYGNUM_HAL_QUICC_SCC1
+#endif // CYGNUM_HAL_QUICC_SCCX
/*
* Early initialization of comm channels. Must not rely
* on interrupts, yet. Interrupt operation can be enabled
* in _bsp_board_init().
@@ -783,42 +895,94 @@ cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
static int init = 0; // It's wrong to do this more than once
+ int chan = 0;
if (init) return;
init++;
// Setup procs in the vector table
- // Set channel 0 - SMC1
- cyg_hal_smc1_init_channel(&ports[0]);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(0);// Should be configurable!
+#if CYGNUM_HAL_QUICC_SMC1 > 0
+ // Set up SMC1
+ cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC1);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
- CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[0]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smc1_write);
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smcx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smc1_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smcx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
- CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smc1_isr);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
+ chan++;
+#endif
+
+#if CYGNUM_HAL_QUICC_SMC2 > 0
+ // Set up SMC2
+ cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC2);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smcx_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smcx_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
+ chan++;
+#endif
#if CYGNUM_HAL_QUICC_SCC1 > 0
+ // Set up SCC1
+ cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC1);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
+ chan++;
+#endif
+
+#if CYGNUM_HAL_QUICC_SCC2 > 0
+ // Set up SCC2
+ cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC2);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
+ chan++;
+#endif
- // Set channel 1 - SCC1
- cyg_hal_scc1_init_channel(&ports[1]);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(1);// Should be configurable!
+#if CYGNUM_HAL_QUICC_SCC3 > 0
+ // Set up SCC3
+ cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC3);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable!
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
- CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[1]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_scc1_write);
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_scc1_putc);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control);
- CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_scc1_isr);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout);
+ chan++;
#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
Index: hal/powerpc/ts1000/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ts1000/current/ChangeLog,v
retrieving revision 1.4
diff -u -5 -p -r1.4 ChangeLog
--- hal/powerpc/ts1000/current/ChangeLog 18 Oct 2002 21:39:39 -0000 1.4
+++ hal/powerpc/ts1000/current/ChangeLog 25 Nov 2002 18:56:38 -0000
@@ -1,5 +1,11 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * src/ts1000.S: Minor include file cleanup.
+
+ * cdl/hal_powerpc_ts1000.cdl: Update port layout CDL.
+
2002-10-18 Gary Thomas <gthomas@ecoscentric.com>
* cdl/hal_powerpc_ts1000.cdl: Fix clock rate calculation.
* misc/redboot_ROMRAM.ecm:
Index: hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl,v
retrieving revision 1.2
diff -u -5 -p -r1.2 hal_powerpc_ts1000.cdl
--- hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl 18 Oct 2002 21:39:40 -0000 1.2
+++ hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl 25 Nov 2002 20:25:07 -0000
@@ -63,13 +63,15 @@ cdl_package CYGPKG_HAL_POWERPC_TS1000 {
compile hal_diag.c hal_aux.c ts1000.S
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGNUM_HAL_QUICC_SMC1
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_powerpc_quicc.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_ts1000.h>"
puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 855\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Allied Telesyn TS1000\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
@@ -98,55 +100,10 @@ cdl_package CYGPKG_HAL_POWERPC_TS1000 {
TS1000 Development Boards have various system clock speeds
depending on the processor fitted. Select the clock speed
appropriate for your board so that the system can set the serial
baud rate correctly, amongst other things."
}
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
- display "Number of communication channels on the board"
- flavor data
- calculated 1
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
- display "Debug serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The TS1000 board has only one serial port. This option
- chooses which port will be used to connect to a host
- running GDB."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Diagnostic serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The TS1000 board has only one serial port. This option
- chooses which port will be used for diagnostic output."
- }
-
- # This option is only used when USE_ROM_MONITOR is enabled - but
- # it cannot be a sub-option to that option, since the code uses the
- # definition in a preprocessor comparison.
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
- display "Debug serial port used by ROM monitor"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The TS1000 board has only one serial port. This
- option tells the code which port is in use by the ROM
- monitor. It should only be necessary to change this
- option if a non-standard configurated eCos GDB stub is
- used."
- }
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
description "
Index: hal/powerpc/ts1000/current/src/ts1000.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ts1000/current/src/ts1000.S,v
retrieving revision 1.2
diff -u -5 -p -r1.2 ts1000.S
--- hal/powerpc/ts1000/current/src/ts1000.S 15 Oct 2002 18:47:55 -0000 1.2
+++ hal/powerpc/ts1000/current/src/ts1000.S 16 Nov 2002 19:53:28 -0000
@@ -50,14 +50,11 @@
##
######DESCRIPTIONEND####
##
##=============================================================================
-#include <pkgconf/system.h>
#include <pkgconf/hal.h>
-#include <pkgconf/hal_powerpc.h>
-#include <pkgconf/hal_powerpc_ts1000.h>
#include <cyg/hal/arch.inc> /* register symbols et al */
#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
/* registers, IMM layout... */
#include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
Index: hal/powerpc/viper/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/ChangeLog,v
retrieving revision 1.17
diff -u -5 -p -r1.17 ChangeLog
--- hal/powerpc/viper/current/ChangeLog 18 Oct 2002 16:56:57 -0000 1.17
+++ hal/powerpc/viper/current/ChangeLog 25 Nov 2002 18:57:49 -0000
@@ -1,5 +1,10 @@
+2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
+
+ * src/viper.S: Minor include file cleanups.
+ * cdl/hal_powerpc_viper.cdl: Update port layout CDL.
+
2002-10-18 Gary Thomas <gthomas@ecoscentric.com>
* include/plf_cache.h: No need for old FLASH cache support.
* src/hal_diag.c:
Index: hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl,v
retrieving revision 1.10
diff -u -5 -p -r1.10 hal_powerpc_viper.cdl
--- hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl 22 Sep 2002 13:51:39 -0000 1.10
+++ hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl 25 Nov 2002 22:15:03 -0000
@@ -63,14 +63,16 @@ cdl_package CYGPKG_HAL_POWERPC_VIPER {
compile hal_diag.c hal_aux.c viper.S
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGNUM_HAL_QUICC_SMC1
implements CYGNUM_HAL_QUICC_SCC1
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_powerpc_quicc.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_viper.h>"
puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 860\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"A&M VIPER\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
@@ -99,55 +101,10 @@ cdl_package CYGPKG_HAL_POWERPC_VIPER {
VIPER Development Boards have various system clock speeds
depending on the processor fitted. Select the clock speed
appropriate for your board so that the system can set the serial
baud rate correctly, amongst other things."
}
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
- display "Number of communication channels on the board"
- flavor data
- calculated 1+CYGNUM_HAL_QUICC_SCC1
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
- display "Debug serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The VIPER board has two serial ports (SMC1 & SCC1). This option
- chooses which port will be used to connect to a host
- running GDB."
- }
-
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
- display "Diagnostic serial port"
- active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The VIPER board has two serial ports (SMC1 & SCC1). This option
- chooses which port will be used for diagnostic output."
- }
-
- # This option is only used when USE_ROM_MONITOR is enabled - but
- # it cannot be a sub-option to that option, since the code uses the
- # definition in a preprocessor comparison.
- cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
- display "Debug serial port used by ROM monitor"
- flavor data
- legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
- description "
- The VIPER board has two serial ports (SMC1 & SCC1). This
- option tells the code which port is in use by the ROM
- monitor. It should only be necessary to change this
- option if a non-standard configurated eCos GDB stub is
- used."
- }
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
description "
Index: hal/powerpc/viper/current/src/viper.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/viper/current/src/viper.S,v
retrieving revision 1.7
diff -u -5 -p -r1.7 viper.S
--- hal/powerpc/viper/current/src/viper.S 24 Jul 2002 14:49:07 -0000 1.7
+++ hal/powerpc/viper/current/src/viper.S 16 Nov 2002 19:53:28 -0000
@@ -50,15 +50,12 @@
##
######DESCRIPTIONEND####
##
##=============================================================================
-#include <pkgconf/system.h>
#include <pkgconf/hal.h>
-#include <pkgconf/hal_powerpc.h>
-#include <pkgconf/hal_powerpc_viper.h>
-
+
#include <cyg/hal/arch.inc> /* register symbols et al */
#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
/* registers, IMM layout... */
#include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
--
------------------------------------------------------------
Gary Thomas |
eCosCentric, Ltd. |
+1 (970) 229-1963 | eCos & RedBoot experts
gthomas@ecoscentric.com |
http://www.ecoscentric.com/ |
------------------------------------------------------------