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MIPS HAL cache fixes
- From: Bart Veer <bartv at ecoscentric dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Sun, 15 Dec 2002 21:26:34 +0000 (GMT)
- Subject: MIPS HAL cache fixes
The MIPS HAL cache macros were broken, like the PowerPC ones as per
recent ecos-discuss postings, but discovered independently. The diff
below ignores white space differences.
Bart
2002-12-12 Bart Veer <bartv@ecoscentric.com>
* include/hal_cache.h: allow for cache flushes etc. where the base
address is not aligned to a cacheline boundary.
Index: hal_cache.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/mips/arch/current/include/hal_cache.h,v
retrieving revision 1.15
diff -u -b -r1.15 hal_cache.h
--- hal_cache.h 23 May 2002 23:03:21 -0000 1.15
+++ hal_cache.h 15 Dec 2002 21:25:11 -0000
@@ -162,17 +162,21 @@
#endif
//-----------------------------------------------------------------------------
-// Size adjustment
-// These macros adjust the size argument up to a whole multiple of the
-// cache line size. This ensures that we apply the cache operation to
-// all cache lines covered by the address[size] arguments in the
-// macros below.
+// Address adjustment.
+// Given an address and a size, these macros return the first
+// cacheline containing the requested range and a terminating address.
-#define HAL_DCACHE_ADJUST_SIZE(_size_) \
-(((_size_)+HAL_DCACHE_LINE_SIZE-1) & ~(HAL_DCACHE_LINE_SIZE-1))
+#define HAL_DCACHE_START_ADDRESS(_addr_) \
+(((CYG_ADDRESS)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))
-#define HAL_ICACHE_ADJUST_SIZE(_size_) \
-(((_size_)+HAL_ICACHE_LINE_SIZE-1) & ~(HAL_ICACHE_LINE_SIZE-1))
+#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
+((CYG_ADDRESS)((_addr_) + (_asize_)))
+
+#define HAL_ICACHE_START_ADDRESS(_addr_) \
+(((CYG_ADDRESS)(_addr_)) & ~(HAL_ICACHE_LINE_SIZE-1))
+
+#define HAL_ICACHE_END_ADDRESS(_addr_, _asize_) \
+((CYG_ADDRESS)((_addr_) + (_asize_)))
//-----------------------------------------------------------------------------
// Global control of data cache
@@ -230,14 +234,13 @@
#ifndef HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
- register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
- register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
- register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_); \
+ register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
+ register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
register CYG_WORD _state_; \
HAL_DCACHE_IS_ENABLED( _state_ ); \
if( _state_ ) { \
_HAL_ASM_SET_MIPS_ISA(3); \
- for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
+ for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
{ _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); } \
_HAL_ASM_SET_MIPS_ISA(0); \
} \
@@ -270,14 +273,13 @@
#ifndef HAL_DCACHE_FLUSH_DEFINED
#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
CYG_MACRO_START \
- register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
- register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
- register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_); \
+ register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
+ register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
register CYG_WORD _state_; \
HAL_DCACHE_IS_ENABLED( _state_ ); \
if( _state_ ) { \
_HAL_ASM_SET_MIPS_ISA(3); \
- for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
+ for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
{ _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); } \
_HAL_ASM_SET_MIPS_ISA(0); \
} \
@@ -289,11 +291,10 @@
#ifndef HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
- register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
- register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
- register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_); \
+ register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
+ register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
_HAL_ASM_SET_MIPS_ISA(3); \
- for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
+ for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
{ _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); } \
_HAL_ASM_SET_MIPS_ISA(0); \
CYG_MACRO_END
@@ -304,14 +305,13 @@
#ifndef HAL_DCACHE_STORE_DEFINED
#define HAL_DCACHE_STORE( _base_ , _asize_ ) \
CYG_MACRO_START \
- register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
- register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
- register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_); \
+ register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
+ register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
register CYG_WORD _state_; \
HAL_DCACHE_IS_ENABLED( _state_ ); \
if( _state_ ) { \
_HAL_ASM_SET_MIPS_ISA(3); \
- for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
+ for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
{ _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); } \
_HAL_ASM_SET_MIPS_ISA(0); \
} \
@@ -376,14 +376,13 @@
#ifndef HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
- register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
- register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
- register CYG_WORD _size_ = HAL_ICACHE_ADJUST_SIZE(_asize_); \
+ register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
+ register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
register CYG_WORD _state_; \
HAL_ICACHE_IS_ENABLED( _state_ ); \
if( _state_ ) { \
_HAL_ASM_SET_MIPS_ISA(3); \
- for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
+ for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
{ _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); } \
_HAL_ASM_SET_MIPS_ISA(0); \
} \
@@ -408,11 +407,10 @@
#ifndef HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
- register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
- register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
- register CYG_WORD _size_ = HAL_ICACHE_ADJUST_SIZE(_asize_); \
+ register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
+ register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
_HAL_ASM_SET_MIPS_ISA(3); \
- for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
+ for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
{ _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); } \
_HAL_ASM_SET_MIPS_ISA(0); \
CYG_MACRO_END