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New board port - Cogent CSB281


Note: only tested for RedBoot at this time.

Index: ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ChangeLog,v
retrieving revision 1.90
diff -u -5 -p -r1.90 ChangeLog
--- ChangeLog	22 Dec 2002 11:17:03 -0000	1.90
+++ ChangeLog	24 Dec 2002 15:49:54 -0000
@@ -1,5 +1,9 @@
+2002-12-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* ecos.db: Add port to Cogent CSB281 (PowerPC 8245)
+
 2002-12-22  Nick Garnett  <nickg@ecoscentric.com>
 
 	* ecos.db: Add HTTPD package.
 
 2002-12-12  Gary Thomas  <gthomas@ecoscentric.com>
Index: NEWS
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/NEWS,v
retrieving revision 1.59
diff -u -5 -p -r1.59 NEWS
--- NEWS	12 Dec 2002 21:15:24 -0000	1.59
+++ NEWS	24 Dec 2002 15:57:45 -0000
@@ -1,5 +1,6 @@
+* Add support for Cogent CSB281 - PowerPC 8245 board.
 * Add support for PowerPC 8260 based systems - one from Motorola (VADS)
   and another from Delphi Communications.  Contributed by Delphi.
 * Add support for Analogue & Micro Adder (PowerPC 850) boards
 * Update MN10300 ASB2303 HAL to support RedBoot
 * New package for application level profiling (histogram only)
Index: ecos.db
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ecos.db,v
retrieving revision 1.83
diff -u -5 -p -r1.83 ecos.db
--- ecos.db	22 Dec 2002 11:17:03 -0000	1.83
+++ ecos.db	24 Dec 2002 15:58:41 -0000
@@ -3876,10 +3876,60 @@ target psim {
         description "
             The psim target provides the packages needed to run
             eCos in the PSIM simulator."
 }
 
+##-------------------------------------------------------------------------------------------
+## Cogent CSB281 (PowerPC 8245) packages
+##
+package CYGPKG_HAL_POWERPC_CSB281 {
+	alias		{ "Cogent PowerPC 8245 board" hal_powerpc_csb281 }
+	directory	hal/powerpc/csb281
+	script		hal_powerpc_csb281.cdl
+	hardware
+        description "
+            The CSB281 HAL package provides the support needed to run
+            eCos on a Cogent PowerPC 8245 board."
+}
+
+package CYGPKG_DEVS_FLASH_CSB281 {
+	alias 		{ "FLASH memory support for Cogent PowerPC 8245 board" flash_csb281 }
+	directory	devs/flash/powerpc/csb281
+	script		flash_csb281.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Cogent CSB281 (PowerPC 8245) board."
+}
+
+package CYGPKG_DEVS_ETH_CSB281 {
+	alias 		{ "Cogent CSB281 (PowerPC 8245) 82559 ethernet driver"
+			   devs_eth_csb281 }
+	hardware
+	directory	devs/eth/powerpc/csb281
+	script		csb281_eth_drivers.cdl
+        description     "Ethernet driver for Cogent CSB281 (PowerPC 8245)
+                         with Intel i82559 ethernet interfaces."
+}
+
+target csb281 {
+	alias		{ "Cogent PowerPC 8245" cogent8245 }
+	packages        { CYGPKG_HAL_POWERPC
+                          CYGPKG_HAL_POWERPC_PPC60x
+                          CYGPKG_HAL_POWERPC_CSB281
+                          CYGPKG_DEVS_FLASH_STRATA
+                          CYGPKG_DEVS_FLASH_CSB281
+                          CYGPKG_IO_PCI
+                          CYGPKG_DEVS_ETH_CSB281
+                          CYGPKG_DEVS_ETH_INTEL_I82559
+        }
+        description "
+            The csb281 target provides the packages needed to run
+            eCos on the Cogent CSB281 (8245) board."
+}
+##-------------------------------------------------------------------------------------------
+
 # --------------------------------------------------------------------------
 # MIPS targets
 
 target jmr3904 {
         alias		{ "Toshiba JMR-TX3904 board" jmr tx39 }
Index: devs/eth/intel/i82559/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/intel/i82559/current/ChangeLog,v
retrieving revision 1.16
diff -u -5 -p -r1.16 ChangeLog
--- devs/eth/intel/i82559/current/ChangeLog	17 Dec 2002 22:10:53 -0000	1.16
+++ devs/eth/intel/i82559/current/ChangeLog	24 Dec 2002 15:40:09 -0000
@@ -9,10 +9,16 @@
 	* src/if_i82559.c (pci_init_find_82559s): Changed scope of 
 	max_interrupt_handle since its needed in other places.
 	* src/if_i82559.c (i82559_stop): Corrected wrong name of variable
 	in a diag_printf function.
 
+2002-07-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/if_i82559.c (pci_init_find_82559s): 
+	Allow platform to define CYGHWR_DEVS_ETH_INTEL_I82559_USE_MEMORY
+	which forces use of memory instead of I/O space for device access.
+
 2002-06-14  Gary Thomas  <gary@chez-thomas.org>
 
 	* src/if_i82559.c: 
 	Need to include <pkgconf/io_eth_drivers.h> for proper configuration
 	of stand-alone (polled) vs. system (interrupt driven) mode.
Index: devs/eth/intel/i82559/current/src/if_i82559.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/intel/i82559/current/src/if_i82559.c,v
retrieving revision 1.16
diff -u -5 -p -r1.16 if_i82559.c
--- devs/eth/intel/i82559/current/src/if_i82559.c	17 Dec 2002 22:10:54 -0000	1.16
+++ devs/eth/intel/i82559/current/src/if_i82559.c	24 Dec 2002 15:38:20 -0000
@@ -7,10 +7,11 @@
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -1331,11 +1332,11 @@ i82559_init(struct cyg_netdevtab_entry *
 
     if ( 0 == initialized++ ) {
         // then this is the first time ever:
         if ( ! pci_init_find_82559s() ) {
 #ifdef DEBUG
-            os_printf( "pci_init_find_82559s failed" );
+            os_printf( "pci_init_find_82559s failed\n" );
 #endif
             return 0;
         }
     }
 
@@ -2929,10 +2930,15 @@ pci_init_find_82559s( void )
                 p_i82559->memory_address = dev_info.base_map[0];
                 p_i82559->io_address = dev_info.base_map[1];
 #ifdef DEBUG
                 db_printf(" memory address = 0x%08x\n", dev_info.base_map[0]);
                 db_printf(" I/O address = 0x%08x\n", dev_info.base_map[1]);
+#endif
+#ifdef CYGHWR_DEVS_ETH_INTEL_I82559_USE_MEMORY
+                // Use the memory address instead of I/O.  Some devices just
+                // don't want to talk using the I/O registers :-(
+                p_i82559->io_address = dev_info.base_map[0];
 #endif
 
                 // Don't use cyg_pci_set_device_info since it clears
                 // some of the fields we want to print out below.
                 cyg_pci_read_config_uint16(dev_info.devid,
Index: devs/eth/powerpc/csb281/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/csb281/current/ChangeLog
diff -N devs/eth/powerpc/csb281/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/csb281/current/ChangeLog	24 Dec 2002 15:51:21 -0000
@@ -0,0 +1,41 @@
+2002-12-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* include/devs_eth_csb281.inl: 
+	* cdl/csb281_eth_drivers.cdl: New package - ethernet support
+	via i82559 on PCI for Cogent CSB281 board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/eth/powerpc/csb281/current/cdl/csb281_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/csb281/current/cdl/csb281_eth_drivers.cdl
diff -N devs/eth/powerpc/csb281/current/cdl/csb281_eth_drivers.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/csb281/current/cdl/csb281_eth_drivers.cdl	24 Dec 2002 15:51:12 -0000
@@ -0,0 +1,201 @@
+# ====================================================================
+#
+#      csb281_eth_drivers.cdl
+#
+#      Ethernet drivers - support for i82559 ethernet controller
+#      on the Cogent CSB281 (PowerPC 8245) board.
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      jskov
+# Contributors:   jskov, hmt, gthomas
+# Date:           2001-02-28
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_CSB281 {
+    display       "Cogent CSB281 ethernet driver"
+    description   "
+	Ethernet driver for Cogent CSB281 with Intel
+	i82559 Ethernet controllers attached via the PCI"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+    active_if     CYGPKG_HAL_POWERPC_CSB281
+
+    include_dir   cyg/io
+
+    # FIXME: This really belongs in the INTEL_I82559 package
+    cdl_interface CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED {
+        display   "Intel i82559 ethernet driver required"
+    }
+
+    define_proc {
+        puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_I82559_INL <cyg/io/devs_eth_csb281.inl>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_INTEL_I82559_CFG <pkgconf/devs_eth_csb281.h>"
+        puts $::cdl_system_header "/*****  ethernet driver proc output end  *****/"
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_CSB281_ETH0 {
+        display       "CSB281 ethernet port 0 driver"
+        flavor        bool
+        default_value 1
+        description   "
+            This option includes the ethernet device driver on the 
+            csb281 motherboard."
+
+        implements CYGHWR_NET_DRIVERS
+        implements CYGHWR_NET_DRIVER_ETH0
+        implements CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED
+
+        cdl_option CYGDAT_DEVS_ETH_CSB281_ETH0_NAME {
+            display       "Device name for the ethernet port 0 driver"
+            flavor        data
+            default_value {"\"eth0\""}
+            description   "
+                This option sets the name of the ethernet device for the
+                ethernet port 0."
+        }
+
+        cdl_component CYGSEM_DEVS_ETH_CSB281_ETH0_SET_ESA {
+            display       "Set the ethernet station address"
+            flavor        bool
+	    default_value !CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
+            description   "Enabling this option will allow the ethernet
+            station address to be forced to the value set by the
+            configuration.  This may be required if the hardware does
+            not include a serial EEPROM for the ESA, and if RedBoot's
+	    flash configuration support is not available."
+            
+            cdl_option CYGDAT_DEVS_ETH_CSB281_ETH0_ESA {
+                display       "The ethernet station address"
+                flavor        data
+                default_value {"{0x00, 0xB5, 0xE0, 0xB5, 0xE0, 0x11}"}
+                description   "The ethernet station address"
+            }
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_CSB281_ETH1 {
+        display       "CSB281 ethernet port 1 driver"
+        flavor        bool
+        default_value 0
+        description   "
+            This option includes the ethernet device driver for the
+            additional i82559 devices plugged into a PCI slot."
+
+        implements CYGHWR_NET_DRIVERS
+        implements CYGHWR_NET_DRIVER_ETH1
+        implements CYGINT_DEVS_ETH_INTEL_I82559_REQUIRED
+
+        cdl_option CYGDAT_DEVS_ETH_CSB281_ETH1_NAME {
+            display       "Device name for the ethernet port 1 driver"
+            flavor        data
+            default_value {"\"eth1\""}
+            description   "
+                This option sets the name of the ethernet device for the
+                ethernet port 1."
+        }
+
+        cdl_component CYGSEM_DEVS_ETH_CSB281_ETH1_SET_ESA {
+            display       "Set the ethernet station address"
+            flavor        bool
+	    default_value !CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
+            description   "Enabling this option will allow the ethernet
+            station address to be forced to the value set by the
+            configuration.  This may be required if the hardware does
+            not include a serial EEPROM for the ESA, and if RedBoot's
+	    flash configuration support is not available."
+            
+            cdl_option CYGDAT_DEVS_ETH_CSB281_ETH1_ESA {
+                display       "The ethernet station address"
+                flavor        data
+                default_value {"{0x00, 0xB5, 0xE0, 0xB5, 0xE0, 0x12}"}
+                description   "The ethernet station address"
+            }
+        }
+    }
+
+
+    # note that this option's name is NOT csb281-specific, but i82559
+    # generic - other instantiations can set these also.
+    cdl_component CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA {
+	display         "RedBoot manages ESA initialization data"
+	flavor          bool
+	default_value	1
+
+	active_if     CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+
+	description   "Enabling this option will allow the ethernet
+	station address to be acquired from RedBoot's configuration data,
+	stored in flash memory.  It can be overridden individually by the
+	'Set the ethernet station address' option for each interface."
+
+	cdl_component CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_VARS {
+	    display        "Build-in flash config fields for ESAs"
+	    flavor         bool
+	    default_value  1
+
+	    active_if       CYGPKG_REDBOOT
+	    active_if       CYGPKG_REDBOOT_FLASH
+	    active_if       CYGSEM_REDBOOT_FLASH_CONFIG
+	    active_if 	    CYGPKG_REDBOOT_NETWORKING
+
+	    description	"
+	    This option controls the presence of RedBoot flash
+	    configuration fields for the ESAs of the interfaces when you
+	    are building RedBoot.  It is independent of whether RedBoot
+	    itself uses the network or any particular interface; this
+	    support is more for the application to use than for RedBoot
+	    itself, though the application gets at the data by vector
+	    calls; this option cannot be enabled outside of building
+	    RedBoot."
+	
+	    cdl_option CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0 {
+		display         "RedBoot manages ESA for eth0"
+		flavor          bool
+		default_value   1
+	    }
+	}
+    }
+}
+
+# EOF csb281_eth_drivers.cdl
Index: devs/eth/powerpc/csb281/current/include/devs_eth_csb281.inl
===================================================================
RCS file: devs/eth/powerpc/csb281/current/include/devs_eth_csb281.inl
diff -N devs/eth/powerpc/csb281/current/include/devs_eth_csb281.inl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/csb281/current/include/devs_eth_csb281.inl	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,116 @@
+//==========================================================================
+//
+//      devs/eth/powerpc/csb281/include/devs_eth_csb281.inl
+//
+//      PCI i82559 ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas
+// Date:        2001-01-25
+// Purpose:     PC i82559 ethernet defintions
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <cyg/hal/hal_intr.h>           // CYGNUM_HAL_INTERRUPT_ETHR
+
+#ifdef CYGPKG_DEVS_ETH_CSB281_ETH0
+
+#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE (CYGARC_UNCACHED_ADDRESS(CYGMEM_SECTION_pci_window))
+#define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE CYGMEM_SECTION_pci_window_SIZE
+#define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
+#define CYGHWR_DEVS_ETH_INTEL_I82559_USE_MEMORY
+
+static I82559 i82559_eth0_priv_data = { 
+#ifdef CYGSEM_DEVS_ETH_CSB281_ETH0_SET_ESA
+    hardwired_esa: 1,
+    mac_address: CYGDAT_DEVS_ETH_CSB281_ETH0_ESA
+#else
+    hardwired_esa: 0,
+#endif
+};
+
+ETH_DRV_SC(i82559_sc0,
+           &i82559_eth0_priv_data,      // Driver specific data
+           CYGDAT_DEVS_ETH_CSB281_ETH0_NAME, // Name for device
+           i82559_start,
+           i82559_stop,
+           i82559_ioctl,
+           i82559_can_send,
+           i82559_send,
+           i82559_recv,
+           i82559_deliver,
+           i82559_poll,
+           i82559_int_vector
+    );
+
+NETDEVTAB_ENTRY(i82559_netdev0, 
+                "i82559_" CYGDAT_DEVS_ETH_CSB281_ETH0_NAME,
+                i82559_init, 
+                &i82559_sc0);
+
+#endif // CYGPKG_DEVS_ETH_CSB281_ETH0
+
+
+// These arrays are used for sanity checking of pointers
+I82559 *
+i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
+#ifdef CYGPKG_DEVS_ETH_CSB281_ETH0
+    &i82559_eth0_priv_data,
+#endif
+};
+
+#ifdef CYGDBG_USE_ASSERTS
+// These are only used when assertions are enabled
+cyg_netdevtab_entry_t *
+i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
+#ifdef CYGPKG_DEVS_ETH_CSB281_ETH0
+    &i82559_netdev0,
+#endif
+};
+
+struct eth_drv_sc *
+i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
+#ifdef CYGPKG_DEVS_ETH_CSB281_ETH0
+    &i82559_sc0,
+#endif
+};
+#endif // CYGDBG_USE_ASSERTS
+
+// EOF devs_eth_csb281.inl
Index: devs/flash/powerpc/csb281/current/ChangeLog
===================================================================
RCS file: devs/flash/powerpc/csb281/current/ChangeLog
diff -N devs/flash/powerpc/csb281/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/csb281/current/ChangeLog	24 Dec 2002 15:52:02 -0000
@@ -0,0 +1,41 @@
+2002-12-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* include/csb281_strataflash.inl: 
+	* cdl/flash_csb281.cdl: New package - FLASH support for
+	Cogent CSB281 (PowerPC 8245) board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/flash/powerpc/csb281/current/cdl/flash_csb281.cdl
===================================================================
RCS file: devs/flash/powerpc/csb281/current/cdl/flash_csb281.cdl
diff -N devs/flash/powerpc/csb281/current/cdl/flash_csb281.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/csb281/current/cdl/flash_csb281.cdl	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,81 @@
+# ====================================================================
+#
+#      flash_csb281.cdl
+#
+#      FLASH memory - Hardware support on Cogent CSB281 (PowerPC 8245)
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           2002-07-23
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_CSB281 {
+    display       "Cogent CSB281 (PowerPC 8245) FLASH memory support"
+
+    parent        CYGPKG_IO_FLASH
+    active_if	  CYGPKG_IO_FLASH
+    requires	  CYGPKG_HAL_POWERPC_CSB281
+
+    requires      CYGPKG_DEVS_FLASH_STRATA
+
+    implements    CYGHWR_IO_FLASH_BLOCK_LOCKING
+
+    include_dir   cyg/io
+
+    # Arguably this should do in the generic package
+    # but then there is a logic loop so you can never enable it.
+    cdl_interface CYGINT_DEVS_FLASH_STRATA_REQUIRED {
+        display   "Generic StrataFLASH driver required"
+    }
+
+    implements    CYGINT_DEVS_FLASH_STRATA_REQUIRED
+
+    define_proc {
+        puts $::cdl_system_header "/***** strataflash driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_INL <cyg/io/csb281_strataflash.inl>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_FLASH_STRATA_CFG <pkgconf/devs_flash_csb281.h>"
+        puts $::cdl_system_header "/*****  strataflash driver proc output end  *****/"
+    }
+}
+
Index: devs/flash/powerpc/csb281/current/include/csb281_strataflash.inl
===================================================================
RCS file: devs/flash/powerpc/csb281/current/include/csb281_strataflash.inl
diff -N devs/flash/powerpc/csb281/current/include/csb281_strataflash.inl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/flash/powerpc/csb281/current/include/csb281_strataflash.inl	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,68 @@
+#ifndef CYGONCE_DEVS_FLASH_CSB281_STRATAFLASH_INL
+#define CYGONCE_DEVS_FLASH_CSB281_STRATAFLASH_INL
+//==========================================================================
+//
+//      csb281_strataflash.inl
+//
+//      Flash programming - device constants, etc.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas, hmt
+// Contributors: gthomas
+// Date:         2002-07-23
+// Purpose:      
+// Description:  
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// The csb281 has two 16-bit devices.
+// StrataFlash 28F128.
+
+#define CYGNUM_FLASH_DEVICES 	(2)
+#define CYGNUM_FLASH_BASE_MASK  (0xFE000000u) // 32Mb
+
+#define CYGNUM_FLASH_BASE 	(0x70000000u)
+#define CYGNUM_FLASH_WIDTH 	(16)
+#define CYGNUM_FLASH_BLANK      (1)
+
+#endif  // CYGONCE_DEVS_FLASH_CSB281_STRATAFLASH_INL
+// ------------------------------------------------------------------------
+// EOF csb281_strataflash.inl
Index: hal/powerpc/arch/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/ChangeLog,v
retrieving revision 1.45
diff -u -5 -p -r1.45 ChangeLog
--- hal/powerpc/arch/current/ChangeLog	14 Nov 2002 23:36:48 -0000	1.45
+++ hal/powerpc/arch/current/ChangeLog	24 Dec 2002 15:53:26 -0000
@@ -1,5 +1,11 @@
+2002-12-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/vectors.S: 
+	* cdl/hal_powerpc.cdl: Add option to allow ROM code to simply
+	jump to the startup code, instead of using an absolute address.
+
 2002-11-14  Gary Thomas  <gthomas@ecoscentric.com>
 
 	* src/vectors.S: Provide pointer to saved registers on interrupt.
 	This is necessary for profiling support.
 
@@ -11,10 +17,15 @@
 2002-08-05  Gary Thomas  <gary@chez-thomas.org>
 2002-08-05  Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>	
 
 	* include/arch.inc: hal_fpu_load regs was not loading registers!
 
+2002-08-01  Gary Thomas  <gary@mlbassoc.com>
+ 
+ 	* include/hal_io.h: 
+ 	* include/hal_intr.h: Allow more variant/platform overrides.
+ 
 2002-04-29  Jonathan Larmour  <jlarmour@redhat.com>
 
 	* src/vectors.S:
 	Don't use .file as it can confuse debugging since the .file
 	doesn't contain the path and therefore the debugger will never
Index: hal/powerpc/arch/current/cdl/hal_powerpc.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/cdl/hal_powerpc.cdl,v
retrieving revision 1.4
diff -u -5 -p -r1.4 hal_powerpc.cdl
--- hal/powerpc/arch/current/cdl/hal_powerpc.cdl	23 May 2002 23:04:11 -0000	1.4
+++ hal/powerpc/arch/current/cdl/hal_powerpc.cdl	24 Dec 2002 15:38:20 -0000
@@ -98,10 +98,16 @@ cdl_package CYGPKG_HAL_POWERPC {
         @tail +2 target.tmp >> $(notdir $@).deps
         @echo >> $(notdir $@).deps
         @rm target.tmp
     }
 
+    cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+        display       "RESET vector jumps to startup"
+        default_value 0
+        description   "
+            Some platforms may need this for ROMRAM startup."
+    }
 
     cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS {
         display       "Copy exception vectors to RAM"
         default_value { (CYG_HAL_STARTUP != "RAM" ||
                          CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) ? 1 : 0 }
Index: hal/powerpc/arch/current/include/hal_intr.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/include/hal_intr.h,v
retrieving revision 1.17
diff -u -5 -p -r1.17 hal_intr.h
--- hal/powerpc/arch/current/include/hal_intr.h	23 May 2002 23:04:12 -0000	1.17
+++ hal/powerpc/arch/current/include/hal_intr.h	24 Dec 2002 15:38:20 -0000
@@ -10,10 +10,11 @@
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -129,11 +130,13 @@
 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL     CYGNUM_HAL_VECTOR_SYSTEM_CALL
 #define CYGNUM_HAL_EXCEPTION_TRACE           CYGNUM_HAL_VECTOR_TRACE
 #define CYGNUM_HAL_EXCEPTION_FP_ASSIST       CYGNUM_HAL_VECTOR_FP_ASSIST
 
 #define CYGNUM_HAL_EXCEPTION_MIN             CYGNUM_HAL_EXCEPTION_RESERVED_0
-#define CYGNUM_HAL_EXCEPTION_MAX             CYGNUM_HAL_VECTOR_FP_ASSIST
+#ifndef CYGNUM_HAL_EXCEPTION_MAX
+#define CYGNUM_HAL_EXCEPTION_MAX             CYGNUM_HAL_VSR_MAX
+#endif
 
 #define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
 
 #endif // CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
 
@@ -399,12 +402,14 @@ externC void cyg_hal_default_exception_v
         result = 0;                                             \
     *(_pvalue_) = -result;                                      \
     CYG_MACRO_END
 #endif
 
+#ifndef HAL_DELAY_US
 extern void hal_delay_us(int);
 #define HAL_DELAY_US(n) hal_delay_us(n)
+#endif
 
 // The vector used by the Real time clock
 #ifndef CYGNUM_HAL_INTERRUPT_RTC
 #define CYGNUM_HAL_INTERRUPT_RTC             CYGNUM_HAL_INTERRUPT_DECREMENTER
 #endif // CYGNUM_HAL_INTERRUPT_RTC
Index: hal/powerpc/arch/current/include/hal_io.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/include/hal_io.h,v
retrieving revision 1.6
diff -u -5 -p -r1.6 hal_io.h
--- hal/powerpc/arch/current/include/hal_io.h	23 May 2002 23:04:12 -0000	1.6
+++ hal/powerpc/arch/current/include/hal_io.h	24 Dec 2002 15:38:20 -0000
@@ -10,10 +10,11 @@
 //=============================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -58,10 +59,13 @@
 //####DESCRIPTIONEND####
 //
 //=============================================================================
 
 #include <cyg/infra/cyg_type.h>
+#ifdef CYGBLD_HAL_PLF_IO_H
+#include CYGBLD_HAL_PLF_IO_H
+#endif
 
 //-----------------------------------------------------------------------------
 // Enforce in-order IO for all HAL reads/writes using this macro.
 #define HAL_IO_BARRIER()                        \
     asm volatile ( "eieio" : : : "memory" )
Index: hal/powerpc/arch/current/src/vectors.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/src/vectors.S,v
retrieving revision 1.27
diff -u -5 -p -r1.27 vectors.S
--- hal/powerpc/arch/current/src/vectors.S	14 Nov 2002 23:36:48 -0000	1.27
+++ hal/powerpc/arch/current/src/vectors.S	24 Dec 2002 15:38:20 -0000
@@ -188,13 +188,18 @@
 
         .macro  reset_vector name
         .p2align 8
         .globl  __exception_\name
 __exception_\name:
+#ifdef CYGSEM_HAL_POWERPC_RESET_USES_JUMP        
+        bl      _start               
+#else
         lwi     r3,_start
         mtlr    r3
         blr
+#endif                
+
         .endm
         
 # Generic vector macro
                 
         .macro  exception_vector name
@@ -308,11 +313,11 @@ _hal_hardware_init_done:                
         lwi     sp,__interrupt_stack
         mtspr   SPRG0,sp        # save in sprg0 for later use
 
         # Set up exception handlers and VSR table, taking care not to
         # step on any ROM monitor''s toes.
-        hal_mon_init
+        hal_mon_init        
 
 #if defined(CYG_HAL_STARTUP_ROM)
 
         # Copy data from ROM to ram
         lwi     r3,__rom_data_start     # r3 = rom start
Index: hal/powerpc/csb281/current/ChangeLog
===================================================================
RCS file: hal/powerpc/csb281/current/ChangeLog
diff -N hal/powerpc/csb281/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/ChangeLog	24 Dec 2002 15:55:47 -0000
@@ -0,0 +1,62 @@
+2002-12-24  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/redboot_linux_exec.c: 
+	* src/hal_diag.c: 
+	* src/hal_aux.c: 
+	* src/csb281.S: 
+	* misc/redboot_ROM.ecm: 
+	* misc/redboot_RAM.ecm: 
+	* include/pkgconf/mlt_powerpc_csb281_romram.mlt: 
+	* include/pkgconf/mlt_powerpc_csb281_romram.ldi: 
+	* include/pkgconf/mlt_powerpc_csb281_romram.h: 
+	* include/pkgconf/mlt_powerpc_csb281_rom.mlt: 
+	* include/pkgconf/mlt_powerpc_csb281_rom.ldi: 
+	* include/pkgconf/mlt_powerpc_csb281_rom.h: 
+	* include/pkgconf/mlt_powerpc_csb281_ram.mlt: 
+	* include/pkgconf/mlt_powerpc_csb281_ram.ldi: 
+	* include/pkgconf/mlt_powerpc_csb281_ram.h: 
+	* include/plf_stub.h: 
+	* include/plf_regs.h: 
+	* include/plf_io.h: 
+	* include/plf_intr.h: 
+	* include/plf_cache.h: 
+	* include/platform.inc: 
+	* include/hal_diag.h: 
+	* cdl/hal_powerpc_csb281.cdl: New package - HAL support
+	for Cogent CSB281 (PowerPC 8245) board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/powerpc/csb281/current/cdl/hal_powerpc_csb281.cdl
===================================================================
RCS file: hal/powerpc/csb281/current/cdl/hal_powerpc_csb281.cdl
diff -N hal/powerpc/csb281/current/cdl/hal_powerpc_csb281.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/cdl/hal_powerpc_csb281.cdl	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,391 @@
+# ====================================================================
+#
+#      hal_powerpc_csb281.cdl
+#
+#      PowerPC/CSB281 board HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      jskov
+# Original data:  hmt
+# Contributors:   gthomas
+# Date:           1999-11-02
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_POWERPC_CSB281 {
+    display       "Cogent CSB281 (PowerPC 8245) board"
+    parent        CYGPKG_HAL_POWERPC
+    requires      CYGPKG_HAL_POWERPC_PPC60x
+    define_header hal_powerpc_csb281.h
+    include_dir   cyg/hal
+    description   "
+        The CSB281 HAL package provides the support needed to run
+        eCos on a Cogent PowerPC 8245 board."
+
+    compile       hal_diag.c hal_aux.c csb281.S
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+# For now, until RedBoot is working
+#    implements    CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_powerpc_ppc60x.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_csb281.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLF_IO_H   <cyg/hal/plf_io.h>"
+
+	puts $::cdl_header "#define HAL_PLATFORM_CPU    \"PowerPC 8245\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Cogent CSB281\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        legal_values  {"RAM" "ROM" "ROMRAM"}
+        default_value {"RAM"}
+	no_define
+	define -file system.h CYG_HAL_STARTUP
+        description   "
+           This option is used to control where the application program will
+           run, either from RAM or ROM (flash) memory.  ROM based applications
+           must be self contained, while RAM applications will typically assume
+           the existence of a debug environment, such as GDB stubs."
+    }
+
+    cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
+        display          "Development board clock speed (MHz)"
+        flavor           data
+        legal_values     333
+        default_value    333
+        description      "
+           CSB281 Development Boards have various system clock speeds
+           depending on the processor fitted.  Select the clock speed
+           appropriate for your board so that the system can set the serial
+           baud rate correctly, amongst other things."
+   }
+
+    cdl_option CYGHWR_HAL_POWERPC_MEM_SPEED {
+        display          "Development board memory bus speed (MHz)"
+        flavor           data
+        legal_values     83
+        default_value    83
+        description      "
+           CSB281 Development Boards have various system clock speeds
+           depending on the processor fitted.  Select the clock speed
+           appropriate for your board so that the system can set the serial
+           baud rate correctly, amongst other things."
+   }
+
+   cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+       display      "Number of communication channels on the board"
+       flavor       data
+       calculated   1
+   }
+
+   cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+       display          "Debug serial port"
+       active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+       flavor data
+       legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+       default_value    0
+       description      "
+           The CSB281 board has only one serial port. This option
+           chooses which port will be used to connect to a host
+           running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display          "Diagnostic serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+           The CSB281 board has only one serial port.  This option
+           chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Baud rate for the HAL diagnostic port"
+        flavor        data
+        legal_values  { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+                      4800 7200 9600 14400 19200 38400 57600 115200 230400
+        }
+        default_value 38400
+        description   "
+            This option specifies the default baud rate (speed) for the 
+            HAL diagnostic port."
+    }
+
+    # This option is only used when USE_ROM_MONITOR is enabled - but
+    # it cannot be a sub-option to that option, since the code uses the
+    # definition in a preprocessor comparison.
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_ROM_DEBUG_CHANNEL {
+        display          "Debug serial port used by ROM monitor"
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The CSB281 board has only one serial port.  This
+            option tells the code which port is in use by the ROM
+            monitor. It should only be necessary to change this
+            option if a non-standard configurated eCos GDB stub is
+            used."
+    }
+
+    # Real-time clock/counter specifics
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants."
+        description   "
+            Period is busclock/100."
+        flavor        none
+    
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            calculated    1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            calculated    100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            calculated    { (((CYGHWR_HAL_POWERPC_MEM_SPEED*1000000)/4)/100) }
+        }
+    }
+    
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        parent  CYGPKG_NONE
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "powerpc-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-msoft-float -mcpu=603e -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by
+                default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-msoft-float -mcpu=603e -g -nostdlib -Wl,--gc-sections -Wl,-static" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+
+        cdl_option CYGBLD_BUILD_GDB_STUBS {
+            display "Build GDB stub ROM image"
+            default_value 0
+            requires { CYG_HAL_STARTUP == "ROM" }
+            requires CYGSEM_HAL_ROM_MONITOR
+            requires CYGBLD_BUILD_COMMON_GDB_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+            no_define
+            description "
+                This option enables the building of the GDB stubs for the
+                board. The common HAL controls takes care of most of the
+                build process, but the platform CDL takes care of creating
+                an S-Record data file suitable for programming using
+                the board's EPPC-Bug firmware monitor."
+
+            make -priority 320 {
+                <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) -O srec --change-address=0x02000000 $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_HAL_POWERPC_CSB281_OPTIONS {
+        display "CSB281 build options"
+        flavor  none
+        description   "
+	    Package specific build options including control over
+	    compiler flags used only in building this package,
+	    and details of which tests are built."
+
+
+        cdl_option CYGPKG_HAL_POWERPC_CSB281_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the CSB281 HAL. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_POWERPC_CSB281_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the CSB281 HAL. These flags are removed from
+                the set of global flags if present."
+        }
+
+        cdl_option CYGPKG_HAL_POWERPC_CSB281_TESTS {
+            display "CSB281 tests"
+            flavor  data
+            no_define
+            calculated { "tests/csb281time" }
+            description   "
+                This option specifies the set of tests for the CSB281 HAL."
+        }
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_csb281_ram" : \
+                     CYG_HAL_STARTUP == "ROMRAM" ? "powerpc_csb281_romram" : \
+                                                "powerpc_csb281_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_csb281_ram.ldi>" : \
+                         CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_powerpc_csb281_romram.ldi>" : \
+                                                    "<pkgconf/mlt_powerpc_csb281_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_csb281_ram.h>" : \
+                         CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_powerpc_csb281_romram.h>" : \
+                                                    "<pkgconf/mlt_powerpc_csb281_rom.h>" }
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGSEM_REDBOOT_HAL_LINUX_BOOT {
+            display        "Support booting Linux via RedBoot"
+            flavor         bool
+            default_value  1
+            description    "
+               This option enables RedBoot to support booting of a Linux kernel."
+
+            compile -library=libextras.a redboot_linux_exec.c
+        }
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+
+#            compile -library=libextras.a redboot_cmds.c
+ 
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+}
Index: hal/powerpc/csb281/current/include/hal_diag.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/hal_diag.h
diff -N hal/powerpc/csb281/current/include/hal_diag.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/hal_diag.h	24 Dec 2002 15:54:02 -0000
@@ -0,0 +1,93 @@
+#ifndef CYGONCE_HAL_HAL_DIAG_H
+#define CYGONCE_HAL_HAL_DIAG_H
+
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:nickg
+// Date:        1998-03-02
+// Purpose:     HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage:       #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
+//-----------------------------------------------------------------------------
+// functions implemented in hal_diag.c
+
+externC void hal_diag_init(void);
+
+externC void hal_diag_write_char(char c);
+
+externC void hal_diag_read_char(char *c);
+
+//-----------------------------------------------------------------------------
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_HAL_DIAG_H
Index: hal/powerpc/csb281/current/include/platform.inc
===================================================================
RCS file: hal/powerpc/csb281/current/include/platform.inc
diff -N hal/powerpc/csb281/current/include/platform.inc
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/platform.inc	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,84 @@
+#ifndef CYGONCE_HAL_PLATFORM_INC
+#define CYGONCE_HAL_PLATFORM_INC
+##=============================================================================
+##
+##	platform.inc
+##
+##	Platform specific assembler header file
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): 	gthomas
+## Contributors:
+## Date:	2002-07-31
+## Purpose:	Platform specific assembly code
+## Description:	This file contains various definitions and macros that are
+##              useful for writing assembly code for the platform.
+## Usage:       included from <cyg/hal/variant.inc>
+##		
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+##-----------------------------------------------------------------------------
+## MPC82xx interrupt handling.
+
+#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED
+
+        # decode the interrupt
+	.macro  hal_intc_decode dreg,state
+        lwz     \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
+        rlwinm. \dreg,\dreg,22,31,31            # isolate bit 21
+        beq     0f                              # done if decrementer (vec 0)
+        lwi     \dreg,_CSB281_EPIC_IACK         # if external, get vector
+        li      r0,0            
+        lwbrx   \dreg,r0,\dreg                  # EPIC is little endian!
+        lwi     r3,_CSB281_EPIC_EOI             # clear interrupt?
+        stw     r0,0(r3)
+        cmpi    0,\dreg,0xFF                    # spurious interrupt?
+        beq     restore_state
+0:      stw     \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
+        slwi    \dreg,\dreg,2                   # convert to byte offset.
+        .endm                              
+
+#define CYGPKG_HAL_POWERPC_INTC_DEFINED
+#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED
+
+#------------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_PLATFORM_INC
+# end of platform.inc
Index: hal/powerpc/csb281/current/include/plf_cache.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/plf_cache.h
diff -N hal/powerpc/csb281/current/include/plf_cache.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/plf_cache.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,77 @@
+#ifndef CYGONCE_PLF_CACHE_H
+#define CYGONCE_PLF_CACHE_H
+
+//=============================================================================
+//
+//      plf_cache.h
+//
+//      Platform HAL cache details
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov
+// Date:        2000-01-26
+// Purpose:     Platform cache control API
+// Description: The macros defined here provide the platform specific
+//              cache control operations / behavior.
+// Usage:       Is included via the architecture cache header:
+//              #include <cyg/hal/hal_cache.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//---------------------------------------------------------------------------
+// Initial cache enabling - controlled by common CDL
+
+//-----------------------------------------------------------------------------
+// FIXME: This definition forces the IO flash driver to use a
+// known-good procedure for fiddling flash before calling flash device
+// driver functions. The procedure breaks on other platform/driver
+// combinations though so is depricated. Hence this definition.
+//
+// If you work on this target, please try to remove this definition
+// and verify that the flash driver still works (both from RAM and
+// flash). If it does, remove the definition and this comment for good
+// [and the old macro definition if this happens to be the last client
+// of that code].
+#define HAL_FLASH_CACHES_OLD_MACROS
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_PLF_CACHE_H
+// End of plf_cache.h
Index: hal/powerpc/csb281/current/include/plf_intr.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/plf_intr.h
diff -N hal/powerpc/csb281/current/include/plf_intr.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/plf_intr.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,129 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+
+//==========================================================================
+//
+//      plf_intr.h
+//
+//      CSB281 platform specific interrupt definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jskov
+// Contributors: jskov, gthomas
+// Date:         2000-06-13
+// Purpose:      Define platform specific interrupt support
+//              
+// Usage:
+//              #include <cyg/hal/plf_intr.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+//----------------------------------------------------------------------------
+// Platform specific interrupt mapping - interrupt vectors
+#define CYGNUM_HAL_INTERRUPT_IRQ0   0x02
+#define CYGNUM_HAL_INTERRUPT_IRQ1   0x03
+#define CYGNUM_HAL_INTERRUPT_IRQ2   0x04
+#define CYGNUM_HAL_INTERRUPT_IRQ3   0x05
+#define CYGNUM_HAL_INTERRUPT_IRQ4   0x06
+#define CYGNUM_HAL_INTERRUPT_UART0  0x07
+#define CYGNUM_HAL_INTERRUPT_UART1  0x08
+#define CYGNUM_HAL_INTERRUPT_TIMER0 0x09
+#define CYGNUM_HAL_INTERRUPT_TIMER1 0x0A
+#define CYGNUM_HAL_INTERRUPT_TIMER2 0x0B
+#define CYGNUM_HAL_INTERRUPT_TIMER3 0x0C
+#define CYGNUM_HAL_INTERRUPT_I2C    0x0D
+#define CYGNUM_HAL_INTERRUPT_DMA0   0x0E
+#define CYGNUM_HAL_INTERRUPT_DMA1   0x0F
+#define CYGNUM_HAL_INTERRUPT_MSG    0x10
+#define CYGNUM_HAL_ISR_MAX          0x10
+
+#define CYGNUM_HAL_INTERRUPT_PCI0   CYGNUM_HAL_INTERRUPT_IRQ0  // PCI slot 0 (disabled)
+#define CYGNUM_HAL_INTERRUPT_PCI1   CYGNUM_HAL_INTERRUPT_IRQ1  // PCI slot 1
+#define CYGNUM_HAL_INTERRUPT_LAN    CYGNUM_HAL_INTERRUPT_IRQ2  // Onboard GD82559
+#define CYGNUM_HAL_INTERRUPT_MOUSE  CYGNUM_HAL_INTERRUPT_IRQ3  // PS/2 mouse
+#define CYGNUM_HAL_INTERRUPT_KBD    CYGNUM_HAL_INTERRUPT_IRQ4  // PS/2 keyboard
+
+// Platform specific interrupt handling - using EPIC
+#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
+
+externC void hal_interrupt_mask(int);
+externC void hal_interrupt_unmask(int);
+externC void hal_interrupt_acknowledge(int);
+externC void hal_interrupt_configure(int, int, int);
+externC void hal_interrupt_set_level(int, int);
+
+#define HAL_INTERRUPT_MASK( _vector_ )                     \
+    hal_interrupt_mask( _vector_ ) 
+#define HAL_INTERRUPT_UNMASK( _vector_ )                   \
+    hal_interrupt_unmask( _vector_ )
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )              \
+    hal_interrupt_acknowledge( _vector_ )
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
+    hal_interrupt_configure( _vector_, _level_, _up_ )
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )       \
+    hal_interrupt_set_level( _vector_, _level_ )
+
+
+//--------------------------------------------------------------------------
+// Control-C support.
+
+// Defined by the quicc driver
+// #include <cyg/hal/quicc/quicc_smc1.h>
+
+
+//----------------------------------------------------------------------------
+// Reset.
+
+// The CSB281 does not have a watchdog (not one we can easily use for this
+// purpose anyway).
+#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
+
+#define HAL_PLATFORM_RESET_ENTRY 0xfff00100
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_PLF_INTR_H
+// End of plf_intr.h
Index: hal/powerpc/csb281/current/include/plf_io.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/plf_io.h
diff -N hal/powerpc/csb281/current/include/plf_io.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/plf_io.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,167 @@
+#ifndef CYGONCE_PLF_IO_H
+#define CYGONCE_PLF_IO_H
+
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific IO support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    hmt, jskov 
+// Contributors: hmt, jskov, gthomas
+// Date:         2002-07-23
+// Purpose:      Cogent CSB281 (PowerPC 8245) PCI IO support macros
+// Description: 
+// Usage:        #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include CYGBLD_HAL_PLATFORM_H
+//#include CYGBLD_HAL_PLF_DEFS_H
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/plf_intr.h>           // Interrupt vectors
+
+//-----------------------------------------------------------------------------
+//
+// PCI support
+//
+#define CYGARC_PHYSICAL_ADDRESS(x) (x)
+#define CYGARC_UNCACHED_ADDRESS(x) (x)
+
+// Restrict device [slot] space
+#define CYG_PCI_MAX_BUS                       1  // Only one BUS
+#define CYG_PCI_MIN_DEV                      11  // Slots start at 11
+#define CYG_PCI_MAX_DEV                      14  // ... and end at 13
+
+//-----------------------------------------------------------------------------
+// Resources
+
+// Map PCI device resources starting from these addresses in PCI space.
+#define HAL_PCI_ALLOC_BASE_MEMORY                 0xF8000000
+#define HAL_PCI_ALLOC_BASE_IO                     0xFE800000
+
+// This is where the PCI spaces are mapped in the CPU's address space.
+#define HAL_PCI_PHYSICAL_MEMORY_BASE              0  // Address maps are 1-1
+#define HAL_PCI_PHYSICAL_IO_BASE                  0
+
+// [hard-wired] shared memory segment
+#define CYGMEM_SECTION_pci_window                 CYGMEM_REGION_ram_SIZE  // "end" of RAM
+#define CYGMEM_SECTION_pci_window_SIZE            0x00100000
+
+// Initialize the PCI environment
+externC void _csb281_pci_init(void);
+#define HAL_PCI_INIT() \
+  _csb281_pci_init()
+
+// Translate the PCI interrupt requested by the device (INTA#, INTB#,
+// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
+externC void _csb281_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid);
+#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
+  _csb281_pci_translate_interrupt(__bus, __devfn, &__vec, &__valid)
+
+// Read a value from the PCI configuration space of the appropriate
+// size at an address composed from the bus, devfn and offset.
+externC cyg_uint8 _csb281_pci_cfg_read_uint8(int bus, int dev, int offset);
+#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )  \
+  __val = _csb281_pci_cfg_read_uint8(__bus, __devfn, __offset)
+    
+externC cyg_uint16 _csb281_pci_cfg_read_uint16(int bus, int dev, int offset);
+#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val )  \
+  __val = _csb281_pci_cfg_read_uint16(__bus, __devfn, __offset)
+    
+externC cyg_uint32 _csb281_pci_cfg_read_uint32(int bus, int dev, int offset);
+#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val )  \
+  __val = _csb281_pci_cfg_read_uint32(__bus, __devfn, __offset)
+
+// Write a value to the PCI configuration space of the appropriate
+// size at an address composed from the bus, devfn and offset.
+externC void _csb281_pci_cfg_write_uint8(int bus, int dev, int offset, cyg_uint8 val);
+#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
+  _csb281_pci_cfg_write_uint8(__bus, __devfn, __offset, __val)
+
+externC void _csb281_pci_cfg_write_uint16(int bus, int dev, int offset, cyg_uint16 val);
+#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
+  _csb281_pci_cfg_write_uint16(__bus, __devfn, __offset, __val)
+
+externC void _csb281_pci_cfg_write_uint32(int bus, int dev, int offset, cyg_uint32 val);
+#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
+  _csb281_pci_cfg_write_uint32(__bus, __devfn, __offset, __val)
+
+static __inline__ unsigned long
+_le32(unsigned long val)
+{
+    return (((val & 0x000000FF) << 24) |
+            ((val & 0x0000FF00) <<  8) |
+            ((val & 0x00FF0000) >>  8) |
+            ((val & 0xFF000000) >> 24));
+}
+
+static __inline__ unsigned short
+_le16(unsigned short val)
+{
+    return (((val & 0x000000FF) << 8) |
+            ((val & 0x0000FF00) >> 8));
+}
+
+#define HAL_WRITE_UINT32LE(_addr_, _val_) \
+  HAL_WRITE_UINT32(_addr_, _le32(_val_))
+#define HAL_WRITE_UINT16LE(_addr_, _val_) \
+  HAL_WRITE_UINT16(_addr_, _le16(_val_))
+#define HAL_WRITE_UINT8LE(_addr_, _val_) \
+  HAL_WRITE_UINT8(_addr_, _val_)
+#define HAL_READ_UINT32LE(_addr_, _val_)        \
+  {                                             \
+      HAL_READ_UINT32(_addr_, _val_);           \
+      _val_ = _le32(_val_);                     \
+  }
+#define HAL_READ_UINT16LE(_addr_, _val_)        \
+  {                                             \
+      HAL_READ_UINT16(_addr_, _val_);           \
+      _val_ = _le16(_val_);                     \
+  }
+#define HAL_READ_UINT8LE(_addr_, _val_)        \
+  HAL_READ_UINT8(_addr_, _val_)
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_PLF_IO_H
Index: hal/powerpc/csb281/current/include/plf_regs.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/plf_regs.h
diff -N hal/powerpc/csb281/current/include/plf_regs.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/plf_regs.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,159 @@
+#ifndef CYGONCE_HAL_PLF_REGS_H
+#define CYGONCE_HAL_PLF_REGS_H
+
+//==========================================================================
+//
+//      plf_regs.h
+//
+//      PowerPC 82xx platform CPU definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2002-06-27
+// Purpose:      
+// Description:  Possibly override any platform assumptions
+//
+// Usage:        Included via the variant+architecture register headers:
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define _CSB281_PCI_CONFIG_ADDR    0xFEC00000   // PCI configuration cycle address
+#define _CSB281_PCI_CONFIG_DATA    0xFEE00000   // PCI configuration cycle data
+
+#define _CSB281_BCSR               0xFF000000   // Board control (16 bit access)
+#define _CSB281_BCSR_IDSEL1          0x0001     // Select PCI slot 0
+#define _CSB281_BCSR_IDSEL2          0x0002     // Select PCI slot 1
+#define _CSB281_BCSR_IDSEL3          0x0004     // Select GD82559 (PCI)
+#define _CSB281_BCSR_LED0            0x0008     // 0 => LED0 on
+#define _CSB281_BCSR_LED1            0x0010     // 0 => LED1 on
+#define _CSB281_BCSR_PRESET          0x0020     // 0 => Reset peripherals (PCI, etc)
+#define _CSB281_BCSR_SMI             0x0040     // 1 => enable SMI via SW0
+#define _CSB281_BCSR_NMI             0x0080     // 1 => enable SMI via SW1
+#define _CSB281_BCSR_USER0           0x0100     // 0 => DIP switch 0 on
+#define _CSB281_BCSR_USER1           0x0200     // 0 => DIP switch 1 on
+#define _CSB281_BCSR_USER2           0x0400     // 0 => DIP switch 2 on
+#define _CSB281_BCSR_USER3           0x0800     // 0 => DIP switch 3 on
+#define _CSB281_BCSR_SW0             0x1000     // 0 => SW0 pressed
+#define _CSB281_BCSR_SW1             0x2000     // 0 => SW1 pressed
+
+#define _CSB281_2WCSR              0xFF000100   // 2wire controller (32 bit access)
+#define _CSB281_2WCSR_CLR_ALL        0x0000     // SDA=0, SCL=0
+#define _CSB281_2WCSR_SET_ALL        0x00FF     // SDA=1, SCL=1
+#define _CSB281_2WCSR_CLR_SDA        0x0004     // SDA=0
+#define _CSB281_2WCSR_SET_SDA        0x0008     // SDA=1
+#define _CSB281_2WCSR_CLR_SCL        0x0001     // SCL=0
+#define _CSB281_2WCSR_SET_SCL        0x0002     // SCL=1
+#define _CSB281_2WCSR_GET_SCL        0x0002     // SCL=?
+#define _CSB281_2WCSR_GET_SDA        0x0001     // SDA=?
+
+#define _CSB281_FS6377_DEV         0x58
+
+#define _CSB281_EUMBBAR            0xF0000000   // Internal registers
+
+// Interrupt controller
+#define _CSB281_EPIC               (_CSB281_EUMBBAR+0x40000)
+#define _CSB281_EPIC_FRR           (_CSB281_EPIC+0x01000)  // Feature reporting register
+#define _CSB281_EPIC_GCR           (_CSB281_EPIC+0x01020)  // Global configuration
+#define _CSB281_EPIC_GCR_R            0x80000000           // Reset
+#define _CSB281_EPIC_GCR_M            0x20000000           // Mode
+#define _CSB281_EPIC_EICR          (_CSB281_EPIC+0x01030)  // Interrupt configuration
+#define _CSB281_EPIC_EICR_SIE         0x08000000           // Serial interrupt enable
+#define _CSB281_EPIC_EVI           (_CSB281_EPIC+0x01080)  // Vendor identification
+#define _CSB281_EPIC_PI            (_CSB281_EPIC+0x01090)  // Processor initialization
+#define _CSB281_EPIC_SVR           (_CSB281_EPIC+0x010E0)  // Spurious interrupt
+#define _CSB281_EPIC_TFRR          (_CSB281_EPIC+0x010F0)  // Timer frequency
+#define _CSB281_EPIC_TCR           (_CSB281_EPIC+0x010F4)  // Timer control
+#define _CSB281_EPIC_GTCCR0        (_CSB281_EPIC+0x01100)  // Timer 0 - current count
+#define _CSB281_EPIC_GTBCR0        (_CSB281_EPIC+0x01110)  // Timer 0 - base  count
+#define _CSB281_EPIC_GTVPR0        (_CSB281_EPIC+0x01120)  // Timer 0 - vector/priority
+#define _CSB281_EPIC_GTDR0         (_CSB281_EPIC+0x01130)  // Timer 0 - destination
+#define _CSB281_EPIC_GTCCR1        (_CSB281_EPIC+0x01140)  // Timer 1 - current count
+#define _CSB281_EPIC_GTBCR1        (_CSB281_EPIC+0x01150)  // Timer 1 - base  count
+#define _CSB281_EPIC_GTVPR1        (_CSB281_EPIC+0x01160)  // Timer 1 - vector/priority
+#define _CSB281_EPIC_GTDR1         (_CSB281_EPIC+0x01170)  // Timer 1 - destination
+#define _CSB281_EPIC_GTCCR2        (_CSB281_EPIC+0x01180)  // Timer 2 - current count
+#define _CSB281_EPIC_GTBCR2        (_CSB281_EPIC+0x01190)  // Timer 2 - base  count
+#define _CSB281_EPIC_GTVPR2        (_CSB281_EPIC+0x011A0)  // Timer 2 - vector/priority
+#define _CSB281_EPIC_GTDR2         (_CSB281_EPIC+0x011B0)  // Timer 2 - destination
+#define _CSB281_EPIC_GTCCR3        (_CSB281_EPIC+0x011C0)  // Timer 2 - current count
+#define _CSB281_EPIC_GTBCR3        (_CSB281_EPIC+0x011D0)  // Timer 2 - base  count
+#define _CSB281_EPIC_GTVPR3        (_CSB281_EPIC+0x011E0)  // Timer 2 - vector/priority
+#define _CSB281_EPIC_IVPR0         (_CSB281_EPIC+0x10200)  // IRQ 0 - vector/priority
+#define _CSB281_EPIC_IDR0          (_CSB281_EPIC+0x10210)  // IRQ 0 - destination
+#define _CSB281_EPIC_IVPR1         (_CSB281_EPIC+0x10220)  // IRQ 1 - vector/priority
+#define _CSB281_EPIC_IDR1          (_CSB281_EPIC+0x10230)  // IRQ 1 - destination
+#define _CSB281_EPIC_IVPR2         (_CSB281_EPIC+0x10240)  // IRQ 2 - vector/priority
+#define _CSB281_EPIC_IDR2          (_CSB281_EPIC+0x10250)  // IRQ 2 - destination
+#define _CSB281_EPIC_IVPR3         (_CSB281_EPIC+0x10260)  // IRQ 3 - vector/priority
+#define _CSB281_EPIC_IDR3          (_CSB281_EPIC+0x10270)  // IRQ 3 - destination
+#define _CSB281_EPIC_IVPR4         (_CSB281_EPIC+0x10280)  // IRQ 4 - vector/priority
+#define _CSB281_EPIC_IDR4          (_CSB281_EPIC+0x10290)  // IRQ 4 - destination
+#define _CSB281_EPIC_I2CVPR        (_CSB281_EPIC+0x11020)  // I2C - vector/priority
+#define _CSB281_EPIC_I2CDR         (_CSB281_EPIC+0x11030)  // I2C - destination
+#define _CSB281_EPIC_DMA0VPR       (_CSB281_EPIC+0x11040)  // DMA0 - vector/priority
+#define _CSB281_EPIC_DMA0DR        (_CSB281_EPIC+0x11050)  // DMA0 - destination
+#define _CSB281_EPIC_DMA1VPR       (_CSB281_EPIC+0x11060)  // DMA1 - vector/priority
+#define _CSB281_EPIC_DMA1DR        (_CSB281_EPIC+0x11070)  // DMA1 - destination
+#define _CSB281_EPIC_MSGVPR        (_CSB281_EPIC+0x110C0)  // MSG - vector/priority
+#define _CSB281_EPIC_MSGDR         (_CSB281_EPIC+0x110D0)  // MSG - destination
+#define _CSB281_EPIC_UART0VPR      (_CSB281_EPIC+0x11120)  // UART0 - vector/priority
+#define _CSB281_EPIC_UART0DR       (_CSB281_EPIC+0x11130)  // UART0 - destination
+#define _CSB281_EPIC_UART1VPR      (_CSB281_EPIC+0x11140)  // UART1 - vector/priority
+#define _CSB281_EPIC_UART1DR       (_CSB281_EPIC+0x11150)  // UART1 - destination
+#define _CSB281_EPIC_PCTPR         (_CSB281_EPIC+0x20080)  // Processor current task priority
+#define _CSB281_EPIC_IACK          (_CSB281_EPIC+0x200A0)  // Interrupt ack (vector)
+#define _CSB281_EPIC_EOI           (_CSB281_EPIC+0x200B0)  // End of interrupt
+
+#define _CSB281_EPIC_PVR_M            0x80000000           // Interrupt masked
+#define _CSB281_EPIC_PVR_A            0x40000000           // Interrupt active
+#define _CSB281_EPIC_PVR_P            0x00800000           // Polarity 0 = active low
+#define _CSB281_EPIC_PVR_S            0x00400000           // Sense 0 = edge
+#define _CSB281_EPIC_PVR_PRIO_SHIFT   16
+#define _CSB281_EPIC_PVR_PRIO_MASK    0xF
+#define _CSB281_EPIC_PVR_VEC_SHIFT    0
+#define _CSB281_EPIC_PVR_VEC_MASK     0xFF
+
+#define _zero_bit(_val_, _bit_) _val_ & ~_bit_
+#define _one_bit(_val_, _bit_) _val_ | _bit_
+
+#endif // CYGONCE_HAL_PLF_REGS_H
Index: hal/powerpc/csb281/current/include/plf_stub.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/plf_stub.h
diff -N hal/powerpc/csb281/current/include/plf_stub.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/plf_stub.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,88 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas
+// Date:        1999-02-12
+// Purpose:     Platform HAL stub support for Cogent CSB281 PowerPC/8245 board.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/ppc_stub.h>           // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#ifdef CYG_HAL_STARTUP_ROM
+# define HAL_STUB_PLATFORM_INIT()
+// to distinguish eCos stub ROM ready state from either RedBoot or app.
+#endif
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.h
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,37 @@
+// eCos memory layout - Thu May 30 10:27:39 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x3F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vectors) [];
+#endif
+#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
+#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
+#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
+#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_for_rom) [];
+#endif
+#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom))
+#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x3cd00)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x3F00000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.ldi
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.ldi
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.ldi	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,31 @@
+// eCos memory layout - Thu May 30 10:27:39 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x1F00000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
+    CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
+    CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
+    CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x3cd00;
+    SECTION_vectors (ram, ALIGN (0x10), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.mlt
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.mlt
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.mlt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_ram.mlt	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,17 @@
+version 0
+region ram 0 1f00000 0 !
+section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
+section reserved_vsr_table 200 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
+section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom !
+section reserved_for_rom 3cd00 10 0 0 0 1 0 1 vectors vectors !
+section vectors 0 10 0 1 0 1 0 1 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 1 0 1 data data !
+section data 0 8 0 1 0 1 0 1 sbss sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.h
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,35 @@
+// eCos memory layout - Thu May 30 10:21:41 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x1F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xfff00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vectors) [];
+#endif
+#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
+#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
+#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
+#endif
+#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
+#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x1f00000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.ldi
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.ldi
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.ldi	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,31 @@
+// eCos memory layout - Thu May 30 10:21:41 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x1f00000
+    rom : ORIGIN = 0xfff00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_vectors (rom, 0xfff00000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
+    CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
+    CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
+    SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table))
+    SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.mlt
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.mlt
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.mlt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_rom.mlt	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,17 @@
+version 0
+region ram 0 1f00000 0 !
+region rom fff00000 100000 1 !
+section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
+section reserved_vsr_table 200 1 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
+section reserved_virtual_table 100 1 0 0 0 1 0 0 data !
+section data 0 10 1 1 0 1 0 0 sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section vectors 0 1 0 1 1 1 1 1 fff00000 fff00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 0 0 1 data !
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.h	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,17 @@
+// eCos memory layout - Thu May 30 10:05:45 2002
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0)
+#define CYGMEM_REGION_ram_SIZE (0x800000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x800000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.ldi	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,27 @@
+// eCos memory layout - Thu May 30 10:05:45 2002
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x800000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_vectors (ram, 0, LMA_EQ_VMA)
+    SECTION_text (ram, 0x3400, LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt
===================================================================
RCS file: hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt
diff -N hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/include/pkgconf/mlt_powerpc_csb281_romram.mlt	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,13 @@
+version 0
+region ram 0 800000 0 !
+section vectors 0 1 0 1 1 0 1 0 0 0 !
+section text 0 1 0 1 1 1 1 1 3400 3400 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
+section rodata 0 8 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 1 0 1 0 1 0 1 data data !
+section data 0 8 0 1 0 1 0 1 sbss sbss !
+section sbss 0 4 0 1 0 1 0 1 bss bss !
+section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
Index: hal/powerpc/csb281/current/misc/redboot_RAM.ecm
===================================================================
RCS file: hal/powerpc/csb281/current/misc/redboot_RAM.ecm
diff -N hal/powerpc/csb281/current/misc/redboot_RAM.ecm
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/misc/redboot_RAM.ecm	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,116 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    csb281 ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_POWERPC current ;
+    package -hardware CYGPKG_HAL_POWERPC_PPC60x current ;
+    package -hardware CYGPKG_HAL_POWERPC_CSB281 current ;
+    package -hardware CYGPKG_DEVS_FLASH_STRATA current ;
+    package -hardware CYGPKG_DEVS_FLASH_CSB281 current ;
+    package -hardware CYGPKG_IO_PCI current ;
+    package -hardware CYGPKG_DEVS_ETH_CSB281 current ;
+    package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_NS_DNS current ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_component CYGSEM_DEVS_ETH_CSB281_ETH0_SET_ESA {
+    user_value 1
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+    user_value 0
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value RAM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+    user_value 0x01F00000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+    inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+    inferred_value 0
+};
+
+
Index: hal/powerpc/csb281/current/misc/redboot_ROM.ecm
===================================================================
RCS file: hal/powerpc/csb281/current/misc/redboot_ROM.ecm
diff -N hal/powerpc/csb281/current/misc/redboot_ROM.ecm
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/misc/redboot_ROM.ecm	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,116 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    csb281 ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_POWERPC current ;
+    package -hardware CYGPKG_HAL_POWERPC_PPC60x current ;
+    package -hardware CYGPKG_HAL_POWERPC_CSB281 current ;
+    package -hardware CYGPKG_DEVS_FLASH_STRATA current ;
+    package -hardware CYGPKG_DEVS_FLASH_CSB281 current ;
+    package -hardware CYGPKG_IO_PCI current ;
+    package -hardware CYGPKG_DEVS_ETH_CSB281 current ;
+    package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_NS_DNS current ;
+    package CYGPKG_IO_FLASH current ;
+    package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_component CYGSEM_DEVS_ETH_CSB281_ETH0_SET_ESA {
+    user_value 1
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
+    user_value 0
+};
+
+cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
+    user_value 1
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    user_value 0x00040000
+};
+
+cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET {
+    user_value 0x01F00000
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG {
+    user_value 1
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+    inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+    inferred_value 0
+};
+
+
Index: hal/powerpc/csb281/current/src/csb281.S
===================================================================
RCS file: hal/powerpc/csb281/current/src/csb281.S
diff -N hal/powerpc/csb281/current/src/csb281.S
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/src/csb281.S	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,202 @@
+##=============================================================================
+##
+##      csb281.S
+##
+##      CSB281 board hardware setup
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):   gthomas
+## Contributors:hmt
+## Date:        2002-07-22
+## Purpose:     CSB281 board hardware setup
+## Description: This file contains any code needed to initialize the
+##              hardware on a Cogent CSB281 (PowerPC 8245) board.
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_powerpc.h>
+#include <pkgconf/hal_powerpc_csb281.h>
+        
+#include <cyg/hal/arch.inc>		/* register symbols et al */
+#include <cyg/hal/ppc_regs.h>		/* on-chip resource layout, special */
+
+#------------------------------------------------------------------------------
+
+// LED macro uses r23, r25: r4 left alone
+#if 0        
+#define LED( x ) \
+	lwi	r25,0xFA100018;         \
+	lwi	r23,(x);                \
+	stb	r23,0(r25)
+#else
+#define LED(x)                          
+#endif
+
+FUNC_START(_led)        
+        lwi     r25,0xFF000000
+        lwz     r26,0(r25)
+        ori     r26,r26,0x18
+        stw     r26,0(r25)
+        blr
+FUNC_END(_led)        
+	
+#------------------------------------------------------------------------------
+                
+FUNC_START( hal_hardware_init )
+
+#if 0 // Seem to be 860 specific
+                
+#define CACHE_UNLOCKALL		0x0a00
+#define CACHE_DISABLE		0x0400
+#define CACHE_INVALIDATEALL	0x0c00
+#define CACHE_ENABLE		0x0200
+#define CACHE_ENABLEBIT		0x8000
+
+#define CACHE_FORCEWRITETHROUGH 0x0100
+#define CACHE_NOWRITETHROUGH    0x0300
+#define CACHE_CLEAR_LE_SWAP     0x0700
+
+	# DATA CACHE
+	mfspr	r3,CYGARC_REG_DC_CST		/* clear error bits */
+        lis     r3,CACHE_UNLOCKALL
+	sync
+        mtspr   CYGARC_REG_DC_CST,r3		/* unlock all lines */
+	
+        lis     r3,CACHE_INVALIDATEALL
+	sync
+        mtspr   CYGARC_REG_DC_CST,r3		/* invalidate all lines */
+
+	lis	r3,CACHE_DISABLE
+	sync
+	mtspr	CYGARC_REG_DC_CST,r3            /* disable */
+	
+	lis	r3,CACHE_FORCEWRITETHROUGH
+	sync
+	mtspr	CYGARC_REG_DC_CST,r3            /* set force-writethrough mode */
+
+	lis	r3,CACHE_CLEAR_LE_SWAP
+	sync
+	mtspr	CYGARC_REG_DC_CST,r3            /* clear little-endian swap mode */
+	/* (dunno what this is, but it sounds like a bad thing) */
+	
+	# INSTRUCTION CACHE (no writeback modes)
+	mfspr	r3,CYGARC_REG_IC_CST		/* clear error bits */
+        lis     r3,CACHE_UNLOCKALL
+        mtspr   CYGARC_REG_IC_CST,r3		/* unlock all lines */
+	isync
+        lis     r3,CACHE_INVALIDATEALL
+        mtspr   CYGARC_REG_IC_CST,r3		/* invalidate all lines */
+        isync
+	lis	r3,CACHE_DISABLE
+	mtspr	CYGARC_REG_IC_CST,r3            /* disable */
+	isync
+	
+	sync
+#endif
+                
+        // Basic hardware initialization
+        mflr    r31
+        bl      10f     // Gets position independent address of table
+HW_init:        
+#ifndef CYG_HAL_STARTUP_RAM
+        .long   0x80000080, 0x00000000  // MSAR1 - SDRAM Bank 0 start
+        .long   0x80000090, 0x0000003F  // MEAR1 - SDRAM Bank 0 end
+        .long   0x800000A0, 0x00000001  // MBEN1 - SDRAM Bank 1 enable
+        .long   0x800000F0, 0x88000000  // MCCR1 - SDRAM control (no GO)
+        .long   0x800000F4, 0x1E00023C  // MCCR2 - Timing
+        .long   0x800000F8, 0xB6000000  // MCCR3
+        .long   0x800000FC, 0x35B03334  // MCCR4
+        .long   0x800000F0, 0x88080000  // MCCR1 - SDRAM control (GO)
+        .long   0x800000D0, 0xB4000000  // ERCR1
+        .long   0x800000D4, 0xBCF7B1E3  // ERCR2
+        .long   0x800000D8, 0x7000000D  // RCS2  - 0x70000000..0x71FFFFFF
+        .long   0x800000DC, 0x7800000D  // RCS3  - 0x78000000..0x79FFFFFF
+#endif        
+        .long   0x80000078, _CSB281_EUMBBAR  // EUMBBAR - machine registers
+        .long   0x800000A8, 0xFF141110  // PICR1 - RCS0 local, Big Endian, DEC/TB
+        .long   0x800000AC, 0x08000000  // PICR2
+        .long   0
+10:     nop
+        mflr    r3              // Pointer to initialization table
+        subi    r3,r3,4
+        lwi     r4,_CSB281_PCI_CONFIG_ADDR
+        lwi     r5,_CSB281_PCI_CONFIG_DATA
+20:     lwzu    r6,4(r3)        // Register address
+        lwzu    r7,4(r3)        // Data
+        cmpi    0,r6,0
+        beq     30f             // end of table?
+        stwbrx  r6,0,r4         // Set address
+        stwbrx  r7,0,r5         // value
+        b       20b
+30:     mtlr    r31        
+		
+	# set the decrementer to maxint
+	lwi	r2,0
+	not	r2,r2
+	mtdec	r2
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+        // Copy image from ROM to RAM
+        mflr    r3              
+        lwi     r4,0xFFF00000
+        lwi     r5,0x000FFFFF   // ROM/FLASH base
+        and     r3,r3,r5        // segment relative
+        lwi     r6,_hal_hardware_init_done
+        mtlr    r6
+        sub     r6,r3,r6        // Absolute address
+        add     r6,r6,r4        // FLASH address
+        lwi     r7,0            // where to copy to
+        lwi     r8,__ram_data_end
+10:     lwz     r5,0(r6)
+        stw     r5,0(r7)
+        addi    r6,r6,4
+        addi    r7,r7,4
+        cmplw   r7,r8
+        bne     10b
+#endif
+
+	blr
+FUNC_END( hal_hardware_init )
+
+#------------------------------------------------------------------------------
+# end of csb281.S
Index: hal/powerpc/csb281/current/src/hal_aux.c
===================================================================
RCS file: hal/powerpc/csb281/current/src/hal_aux.c
diff -N hal/powerpc/csb281/current/src/hal_aux.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/src/hal_aux.c	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,661 @@
+//=============================================================================
+//
+//      hal_aux.c
+//
+//      HAL auxiliary objects and code; per platform
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   hmt
+// Contributors:hmt, gthomas
+// Date:        1999-06-08
+// Purpose:     HAL aux objects: startup tables.
+// Description: Tables for per-platform initialization
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/io_pci.h>
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_mem.h>            // HAL memory definitions
+#include <cyg/hal/ppc_regs.h>           // Platform registers
+#include <cyg/hal/hal_if.h>             // hal_if_init
+#include <cyg/hal/hal_intr.h>           // interrupt definitions
+#include <cyg/hal/hal_cache.h>
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+#include <cyg/io/pci.h>
+#include <cyg/hal/hal_io.h>             // I/O macros
+#include CYGHWR_MEMORY_LAYOUT_H
+
+// The memory map is weakly defined, allowing the application to redefine
+// it if necessary. The regions defined below are the minimum requirements.
+CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
+    // Mapping for the Cogent CSB281 development boards
+    CYGARC_MEMDESC_NOCACHE( 0x70000000, 0x10000000 ), // FLASH region, LCD, PS/2
+    CYGARC_MEMDESC_NOCACHE( 0xf0000000, 0x10000000 ), // PCI space, LEDS, control
+    CYGARC_MEMDESC_CACHE(   CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
+
+    CYGARC_MEMDESC_TABLE_END
+};
+
+//--------------------------------------------------------------------------
+// Platform init code.
+void
+hal_platform_init(void)
+{
+    cyg_uint32 bcsr, gcr, frr, eicr;
+    int vec;
+
+    // Initialize I/O interfaces
+    hal_if_init();
+    // Reset interrupt controller/state
+    HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
+    HAL_READ_UINT32LE(_CSB281_EPIC_FRR, frr);
+    HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_R);
+    do {
+        HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
+    } while ((gcr & _CSB281_EPIC_GCR_R) != 0);
+    HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_M);
+    HAL_READ_UINT32LE(_CSB281_EPIC_EICR, eicr);  // Force direct interrupts
+    eicr &= ~_CSB281_EPIC_EICR_SIE;
+    HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
+    for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
+        HAL_INTERRUPT_CONFIGURE(vec, 0, 0);  // Default to low-edge
+        HAL_INTERRUPT_SET_LEVEL(vec, 0x0F);  // Priority
+    }
+    HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
+    // Reset peripherals
+    HAL_READ_UINT32(_CSB281_BCSR, bcsr);
+    HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
+    HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
+    _csb281_i2c_init();
+    _csb281_fs6377_init();
+    _csb281_pci_init();
+}
+
+//--------------------------------------------------------------------------
+// Interrupt support
+
+CYG_ADDRWORD _pvrs[] = {
+    _CSB281_EPIC_IVPR0,     // CYGNUM_HAL_INTERRUPT_IRQ0   0x02
+    _CSB281_EPIC_IVPR1,     // CYGNUM_HAL_INTERRUPT_IRQ1   0x03
+    _CSB281_EPIC_IVPR2,     // CYGNUM_HAL_INTERRUPT_IRQ2   0x04
+    _CSB281_EPIC_IVPR3,     // CYGNUM_HAL_INTERRUPT_IRQ3   0x05
+    _CSB281_EPIC_IVPR4,     // CYGNUM_HAL_INTERRUPT_IRQ4   0x06
+    _CSB281_EPIC_UART0VPR,  // CYGNUM_HAL_INTERRUPT_UART0  0x07
+    _CSB281_EPIC_UART1VPR,  // CYGNUM_HAL_INTERRUPT_UART1  0x08
+    _CSB281_EPIC_GTVPR0,    // CYGNUM_HAL_INTERRUPT_TIMER0 0x09
+    _CSB281_EPIC_GTVPR1,    // CYGNUM_HAL_INTERRUPT_TIMER1 0x0A
+    _CSB281_EPIC_GTVPR2,    // CYGNUM_HAL_INTERRUPT_TIMER2 0x0B
+    _CSB281_EPIC_GTVPR3,    // CYGNUM_HAL_INTERRUPT_TIMER3 0x0C
+    _CSB281_EPIC_I2CVPR,    // CYGNUM_HAL_INTERRUPT_I2C    0x0D
+    _CSB281_EPIC_DMA0VPR,   // CYGNUM_HAL_INTERRUPT_DMA0   0x0E
+    _CSB281_EPIC_DMA1VPR,   // CYGNUM_HAL_INTERRUPT_DMA1   0x0F
+    _CSB281_EPIC_MSGVPR,    // CYGNUM_HAL_INTERRUPT_MSG    0x10
+};
+
+void 
+hal_interrupt_mask(int vector)
+{
+    cyg_uint32 pvr;
+
+    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
+    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
+    if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
+        // Can't do much with non-external interrupts
+        return;
+    }
+    HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+    pvr |= _CSB281_EPIC_PVR_M;
+    HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+//    diag_printf("%s(%d)\n", __FUNCTION__, vector);
+}
+
+void 
+hal_interrupt_unmask(int vector)
+{
+    cyg_uint32 pvr;
+
+    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
+    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
+    if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
+        // Can't do much with non-external interrupts
+        return;
+    }
+    HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+    pvr &= ~_CSB281_EPIC_PVR_M;
+    HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+//    diag_printf("%s(%d)\n", __FUNCTION__, vector);
+}
+
+void 
+hal_interrupt_acknowledge(int vector)
+{
+}
+
+void 
+hal_interrupt_configure(int vector, int level, int up)
+{
+    cyg_uint32 pvr;
+
+    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
+    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
+    if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
+        // Can't do much with non-external interrupts
+        return;
+    }
+//    diag_printf("%s(%d, %d, %d)\n", __FUNCTION__, vector, level, up);
+    HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+    pvr &= _CSB281_EPIC_PVR_M;  // Preserve mask
+    pvr |= vector;
+    if (level) {
+        pvr |= _CSB281_EPIC_PVR_S;
+    } else {
+        pvr &= ~_CSB281_EPIC_PVR_S;
+    }
+    if (up) {
+        pvr |= _CSB281_EPIC_PVR_P;
+    } else {
+        pvr &= ~_CSB281_EPIC_PVR_P;
+    }
+    HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+}
+
+void 
+hal_interrupt_set_level(int vector, int level)
+{
+    cyg_uint32 pvr;
+
+    CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
+    CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
+    if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
+        // Can't do much with non-external interrupts
+        return;
+    }
+    HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+    pvr &= ~(_CSB281_EPIC_PVR_PRIO_MASK<<_CSB281_EPIC_PVR_PRIO_SHIFT);
+    pvr |= (level<<_CSB281_EPIC_PVR_PRIO_SHIFT);
+    HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
+}
+
+
+//--------------------------------------------------------------------------
+// PCI support
+
+externC void
+_csb281_pci_init(void)
+{
+    static int _init = 0;
+    cyg_uint8 next_bus;
+    cyg_uint32 cmd_state;
+
+    if (_init) return;
+    _init = 1;
+
+    // Initialize PCI support
+    cyg_pci_init();
+
+    // Setup for bus mastering
+    HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
+                            CYG_PCI_CFG_COMMAND, cmd_state);
+    if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
+        // Force PCI-side window to 0
+        HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
+                                 CYG_PCI_CFG_BAR_0, 0x01);
+        // Enable bus mastering from host
+        HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
+                                 CYG_PCI_CFG_COMMAND,
+                                 CYG_PCI_CFG_COMMAND_MEMORY |
+                                 CYG_PCI_CFG_COMMAND_MASTER |
+                                 CYG_PCI_CFG_COMMAND_PARITY |
+                                 CYG_PCI_CFG_COMMAND_SERR);
+
+        // Setup latency timer field
+        HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
+                                CYG_PCI_CFG_LATENCY_TIMER, 32);
+
+        // Configure PCI bus.
+        next_bus = 1;
+        cyg_pci_configure_bus(0, &next_bus);
+    }
+
+    // Configure interrupts (high level)?
+    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
+    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
+    HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
+}
+
+externC void 
+_csb281_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
+{
+    cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
+
+    // Purely slot based
+    if (dev >= CYG_PCI_MIN_DEV) {
+        CYG_ADDRWORD __translation[] = {                                       
+            CYGNUM_HAL_INTERRUPT_PCI0,
+            CYGNUM_HAL_INTERRUPT_PCI1,
+            CYGNUM_HAL_INTERRUPT_LAN
+        };
+        *vec = __translation[dev-CYG_PCI_MIN_DEV];
+        *valid = true;
+    } else {
+        *valid = false;
+    }
+#if 0
+    diag_printf("Int - dev: %d, vector: %d [%s]\n", 
+                dev, *vec, *valid ? "OK" : "BAD");
+#endif
+}
+
+// PCI configuration space access
+#define _EXT_ENABLE                     0x80000000
+
+//
+// Prepare for a config cycle on the PCI bus
+//
+static __inline__ cyg_uint32
+_cfg_sel(int bus, int devfn, int offset)
+{
+    cyg_uint32 cfg_addr, addr;
+    cyg_uint32 bcsr;
+
+    HAL_READ_UINT32(_CSB281_BCSR, bcsr);
+    bcsr = (bcsr & ~0x07) | (1<<(CYG_PCI_DEV_GET_DEV(devfn)-CYG_PCI_MIN_DEV));
+    HAL_WRITE_UINT32(_CSB281_BCSR, bcsr);
+    cfg_addr = _EXT_ENABLE | 
+        (bus << 16) | 
+        (CYG_PCI_DEV_GET_DEV(devfn) << 11) | 
+        (CYG_PCI_DEV_GET_FN(devfn) << 8) | 
+        ((offset & 0xFF) << 0);
+    HAL_WRITE_UINT32LE(_CSB281_PCI_CONFIG_ADDR, cfg_addr);
+    addr = _CSB281_PCI_CONFIG_DATA + (offset & 0x03);
+    return addr;
+}
+
+externC cyg_uint8 
+_csb281_pci_cfg_read_uint8(int bus, int devfn, int offset)
+{
+    cyg_uint32 addr;
+    cyg_uint8 cfg_val = (cyg_uint8)0xFF;
+
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
+#endif // CYGPKG_IO_PCI_DEBUG
+    addr = _cfg_sel(bus, devfn, offset);
+    HAL_READ_UINT8LE(addr, cfg_val);
+#if 0
+    HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
+    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
+        // Cycle failed - clean up and get out
+        cfg_val = (cyg_uint8)0xFF;
+        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
+    }
+#endif
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%x\n", cfg_val);
+#endif // CYGPKG_IO_PCI_DEBUG
+    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
+    return cfg_val;
+}
+
+externC cyg_uint16 
+_csb281_pci_cfg_read_uint16(int bus, int devfn, int offset)
+{
+    cyg_uint32 addr;
+    cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
+
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
+#endif // CYGPKG_IO_PCI_DEBUG
+    addr = _cfg_sel(bus, devfn, offset);    
+    HAL_READ_UINT16LE(addr, cfg_val);
+#if 0
+    HAL_READ_UINT16LE(_CSB281_PCI_STAT_CMD, status);
+    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
+        // Cycle failed - clean up and get out
+        cfg_val = (cyg_uint16)0xFFFF;
+        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
+    }
+#endif
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%x\n", cfg_val);
+#endif // CYGPKG_IO_PCI_DEBUG
+    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
+    return cfg_val;
+}
+
+externC cyg_uint32 
+_csb281_pci_cfg_read_uint32(int bus, int devfn, int offset)
+{
+    cyg_uint32 addr;
+    cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
+
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
+#endif // CYGPKG_IO_PCI_DEBUG
+    addr = _cfg_sel(bus, devfn, offset);
+    HAL_READ_UINT32LE(addr, cfg_val);
+#if 0
+    HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
+    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
+        // Cycle failed - clean up and get out
+        cfg_val = (cyg_uint32)0xFFFFFFFF;
+        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
+    }
+#endif
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%x\n", cfg_val);
+#endif // CYGPKG_IO_PCI_DEBUG
+    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
+    return cfg_val;
+}
+
+externC void
+_csb281_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
+{
+    cyg_uint32 addr;
+
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
+#endif // CYGPKG_IO_PCI_DEBUG
+    addr = _cfg_sel(bus, devfn, offset);
+    HAL_WRITE_UINT8LE(addr, cfg_val);
+#if 0
+    HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
+    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
+        // Cycle failed - clean up and get out
+        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
+    }
+#endif
+    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
+}
+
+externC void
+_csb281_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
+{
+    cyg_uint32 addr;
+
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
+#endif // CYGPKG_IO_PCI_DEBUG
+    addr = _cfg_sel(bus, devfn, offset);
+    HAL_WRITE_UINT16LE(addr, cfg_val);
+#if 0
+    HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
+    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
+        // Cycle failed - clean up and get out
+        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
+    }
+#endif
+    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
+}
+
+externC void
+_csb281_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
+{
+    cyg_uint32 addr;
+
+#ifdef CYGPKG_IO_PCI_DEBUG
+    diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
+#endif // CYGPKG_IO_PCI_DEBUG
+    addr = _cfg_sel(bus, devfn, offset);
+    HAL_WRITE_UINT32LE(addr, cfg_val);
+#if 0
+    HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
+    if (status & _CSB281_PCI_STAT_ERROR_MASK) {
+        // Cycle failed - clean up and get out
+        HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
+    }
+#endif
+    HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
+}
+
+//--------------------------------------------------------------------------
+// I2C support
+static void
+_csb281_i2c_init(void)
+{
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_ALL);   // SDA=1, SCL=1
+}
+
+static void
+_csb281_i2c_delay(void)
+{
+    int ctr;
+
+    for (ctr = 0;  ctr < 100*10;  ctr++);
+}
+
+// Issue start sequence which is SDA(1->0) with SCL(1)
+static void
+_csb281_i2c_start(void)
+{
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA);   // SDA=1, SCL=?
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL);   // SDA=1, SCL=1
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SDA);   // SDA=0, SCL=1
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL);   // SDA=0, SCL=0
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA);   // SDA=1, SCL=1
+    _csb281_i2c_delay();
+}
+
+// Issue stop sequence which is SDA(0->1) with SCL(1)
+static void
+_csb281_i2c_stop(void)
+{
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SDA);   // SDA=0, SCL=?
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL);   // SDA=1, SCL=1
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA);   // SDA=1, SCL=1
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL);   // SDA=0, SCL=0
+    _csb281_i2c_delay();
+}
+
+// Send an 8-bit value, MSB first, SCL(1->0) clocks the data
+static int
+_csb281_i2c_put(unsigned char val)
+{
+    int bit, csr;
+
+    for (bit = 7;  bit >= 0;  bit--) {
+        if ((val & (1 << bit))) {
+            HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA);   // SDA=1, SCL=?
+        } else {
+            HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SDA);   // SDA=0, SCL=?
+        }
+        _csb281_i2c_delay();
+        HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL);   // SDA=?, SCL=1
+        _csb281_i2c_delay();
+        HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL);   // SDA=?, SCL=0
+    }
+    // Now wait for ACK
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA);   // SDA=1, SCL=0
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL);   // SDA=1, SCL=1
+    _csb281_i2c_delay();
+    HAL_READ_UINT32(_CSB281_2WCSR, csr);  // Read current state
+    if ((csr & _CSB281_2WCSR_GET_SDA)) {
+        // No ACK!
+        return -1;
+    }
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL);   // SDA=?, SCL=0
+    _csb281_i2c_delay();
+    return 0;
+}
+
+static unsigned char
+_csb281_i2c_get(void)
+{
+    unsigned char val = 0;
+    int bit, csr;
+
+    for (bit = 7;  bit >= 0;  bit--) {
+        HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL);   // SDA=?, SCL=1
+        _csb281_i2c_delay();
+        HAL_READ_UINT32(_CSB281_2WCSR, csr);  // Read current state
+        if ((csr & _CSB281_2WCSR_GET_SDA)) {
+            val |= (1 << bit);
+        }
+        HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL);   // SDA=?, SCL=0
+        _csb281_i2c_delay();
+    }
+    // Need extra transition (for ACK time slot)
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL);   // SDA=?, SCL=0
+    _csb281_i2c_delay();
+    HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL);   // SDA=?, SCL=0
+    _csb281_i2c_delay();
+    return val;
+}
+
+int
+_csb281_i2c_write_reg(int addr, int reg, unsigned char val)
+{
+    _csb281_i2c_start();
+    if (_csb281_i2c_put(addr << 1) < 0) {
+        return -1;
+    }
+    if (_csb281_i2c_put(reg) < 0) {
+        return -1;
+    }
+    if (_csb281_i2c_put(val) < 0) {
+        return -1;
+    }
+    _csb281_i2c_stop();
+    return 0;
+}
+
+int
+_csb281_i2c_read_reg(int addr, int reg)
+{
+    unsigned char val;
+    _csb281_i2c_start();
+    if (_csb281_i2c_put(addr << 1) < 0) {
+        return -1;
+    }
+    if (_csb281_i2c_put(reg) < 0) {
+        return -1;
+    }
+    _csb281_i2c_start();
+    if (_csb281_i2c_put((addr << 1) | 0x01) < 0) {
+        return -1;
+    }
+    val = _csb281_i2c_get();
+    _csb281_i2c_stop();
+    return val;
+}
+
+//--------------------------------------------------------------------------
+// FS6377 Clock generator support
+
+static unsigned char _fs6377_init_data[] = {
+    0x28, 0xEF, 0x53, 0x03, 0x4B, 0x80, 0x32, 0x80,
+    0x94, 0x32, 0x80, 0xD4, 0x56, 0xF6, 0xF6, 0xE0
+};
+
+static void
+_csb281_fs6377_init(void)
+{
+    int reg;
+
+    for (reg = 0;  reg < 16;  reg++) {
+        if (_csb281_i2c_write_reg(_CSB281_FS6377_DEV, reg, _fs6377_init_data[reg]) < 0) {
+            diag_printf("** Can't write FS6377 register %d\n", reg);
+            return;
+        }
+    }
+}
+
+//--------------------------------------------------------------------------
+// Blink the value 'val' into the LEDs
+//   LED0 - clock
+//   LED1 - value
+
+static void
+_set_leds(int led0, int led1)
+{
+    cyg_uint32 bcsr;
+
+    HAL_READ_UINT32(_CSB281_BCSR, bcsr);
+    bcsr = _one_bit(bcsr, (_CSB281_BCSR_LED0 | _CSB281_BCSR_LED1));
+    if (led0) bcsr = _zero_bit(bcsr, _CSB281_BCSR_LED0);
+    if (led1) bcsr = _zero_bit(bcsr, _CSB281_BCSR_LED1);
+    HAL_WRITE_UINT32(_CSB281_BCSR, bcsr);
+}
+
+_led_delay(int len)
+{
+    int ctr, limit;
+    int cache_state;
+
+    HAL_ICACHE_IS_ENABLED(cache_state);
+    limit = cache_state ? 0x100000 : 0x40000;
+    while (len--) {
+        for (ctr = 0;  ctr < limit;  ctr++);
+    }
+}
+
+_csb281_led(int val)
+{
+    int bit, ctr;
+
+    for (ctr = 0;  ctr < 8;  ctr++) {
+        _set_leds(0,0);
+        _led_delay(1);
+        _set_leds(0,1);
+        _led_delay(1);
+    }
+    _set_leds(0,0);
+    _led_delay(16);
+    for (bit = 7;  bit >= 0;  bit--) {
+        _set_leds(1, val & (1<<bit));
+        _led_delay(8);
+        _set_leds(0, 0);
+        _led_delay(8);
+    }
+}
+
+// EOF hal_aux.c
Index: hal/powerpc/csb281/current/src/hal_diag.c
===================================================================
RCS file: hal/powerpc/csb281/current/src/hal_diag.c
diff -N hal/powerpc/csb281/current/src/hal_diag.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/src/hal_diag.c	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,453 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic I/O code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   hmt
+// Contributors:hmt, gthomas
+// Date:        1999-06-08
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic I/O support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt macros
+#include <cyg/hal/drv_api.h>
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#include <cyg/hal/hal_stub.h>           // hal_output_gdb_string
+#endif
+
+#include <cyg/hal/ppc_regs.h>
+
+//=============================================================================
+// Serial driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CYG_DEV_SERIAL_BASE_A    0xF0004500 // port A
+#define CYG_DEV_SERIAL_BASE_B    0xF0004600 // port B
+
+//-----------------------------------------------------------------------------
+// Default baud rate is 38400
+#define _MEMCLK (CYGHWR_HAL_POWERPC_MEM_SPEED*1000000)
+#define _BAUD   CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
+#define CYG_DEV_SERIAL_RS232_T1_VALUE_B38400  (((_MEMCLK/16)/_BAUD) >> 8)
+#define CYG_DEV_SERIAL_RS232_T2_VALUE_B38400  (((_MEMCLK/16)/_BAUD) & 0xFF)
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The 8245 has a 16552 UART builtin.
+//
+#define CYG_DEV_SERIAL_RBR   0x00  // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER   0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM   0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR   0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR   0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR   0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR   0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR   0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR   0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR   0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR   0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI   0x01            // enable received data available irq
+#define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
+#define SIO_IER_ELSI    0x04            // enable receiver line status irq
+#define SIO_IER_EMSI    0x08            // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP      0x01            // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
+#define ISR_Tx  0x02
+#define ISR_Rx  0x04
+
+// The line status register bits.
+#define SIO_LSR_DR      0x01            // data ready
+#define SIO_LSR_OE      0x02            // overrun error
+#define SIO_LSR_PE      0x04            // parity error
+#define SIO_LSR_FE      0x08            // framing error
+#define SIO_LSR_BI      0x10            // break interrupt
+#define SIO_LSR_THRE    0x20            // transmitter holding register empty
+#define SIO_LSR_TEMT    0x40            // transmitter register empty
+#define SIO_LSR_ERR     0x80            // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS  0x01              // delta clear to send
+#define SIO_MSR_DDSR  0x02              // delta data set ready
+#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
+#define SIO_MSR_DDCD  0x08              // delta data carrier detect
+#define SIO_MSR_CTS   0x10              // clear to send
+#define SIO_MSR_DSR   0x20              // data set ready
+#define SIO_MSR_RI    0x40              // ring indicator
+#define SIO_MSR_DCD   0x80              // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0   0x01             // word length select bit 0
+#define SIO_LCR_WLS1   0x02             // word length select bit 1
+#define SIO_LCR_STB    0x04             // number of stop bits
+#define SIO_LCR_PEN    0x08             // parity enable
+#define SIO_LCR_EPS    0x10             // even parity select
+#define SIO_LCR_SP     0x20             // stick parity
+#define SIO_LCR_SB     0x40             // set break
+#define SIO_LCR_DLAB   0x80             // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
+#define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
+
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint8* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+} channel_data_t;
+
+//-----------------------------------------------------------------------------
+static void
+init_serial_channel(const channel_data_t* __ch_data)
+{
+    cyg_uint8* base = __ch_data->base;
+    cyg_uint8 lcr;
+
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_IER, 0);
+
+    // Disable and clear FIFOs (need to enable to clear).
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR,
+                    (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+    // Set speed to 38400.
+    HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
+    lcr |= SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
+
+
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL,
+                    CYG_DEV_SERIAL_RS232_T2_VALUE_B38400);
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM,
+                    CYG_DEV_SERIAL_RS232_T1_VALUE_B38400);
+    lcr &= ~SIO_LCR_DLAB;
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
+
+#if 0 // Necessary?
+    {
+        // Special initialization for ST16C552 on CMA102
+        cyg_uint8 mcr;
+        
+        HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR_A, mcr);
+        mcr |= 8;
+        HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR_A, mcr);
+
+        HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR_B, mcr);
+        mcr |= 8;
+        HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR_B, mcr);
+    }
+#endif
+
+    // Enable FIFOs (and clear them).
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR,
+                    (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+
+    HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
+    if ((lsr & SIO_LSR_DR) == 0)
+        return false;
+
+    HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
+
+    return true;
+}
+
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+void
+cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 lsr;
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c);
+
+    // Hang around until the character has been safely sent.
+    do {
+        HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static const channel_data_t channels[2] = {
+    { (cyg_uint8*)CYG_DEV_SERIAL_BASE_A, 1000, CYGNUM_HAL_INTERRUPT_UART0},
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
+    { (cyg_uint8*)CYG_DEV_SERIAL_BASE_B, 1000, CYGNUM_HAL_INTERRUPT_UART1},
+#endif
+};
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8 ier;
+    int ret = 0;
+    CYGARC_HAL_SAVE_GP();
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+        HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
+        ier |= SIO_IER_ERDAI;
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
+        irq_state = 1;
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
+        ier &= ~SIO_IER_ERDAI;
+        HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+    {
+        va_list ap;
+
+        va_start(ap, __func);
+
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+        va_end(ap);
+    }        
+    default:
+        break;
+    }
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8 _iir;
+    int res = 0;
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+    _iir &= SIO_IIR_ID_MASK;
+
+    *__ctrlc = 0;
+    if ( ISR_Rx == _iir ) {
+        cyg_uint8 c, lsr;
+        HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+        if (lsr & SIO_LSR_DR) {
+
+            HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_RBR, c);
+
+            if( cyg_hal_is_break( &c , 1 ) )
+                *__ctrlc = 1;
+        }
+
+        // Acknowledge the interrupt
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        res = CYG_ISR_HANDLED;
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Disable interrupts.
+    HAL_INTERRUPT_MASK(channels[0].isr_vector);
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
+    HAL_INTERRUPT_MASK(channels[1].isr_vector);
+#endif
+
+    // Init channels
+    init_serial_channel(&channels[0]);
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
+    init_serial_channel(&channels[1]);
+#endif
+
+    // Setup procs in the vector table
+
+    // Set channel 0
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1)
+    // Set channel 1
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+    
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+
+// EOF hal_diag.c
Index: hal/powerpc/csb281/current/src/redboot_linux_exec.c
===================================================================
RCS file: hal/powerpc/csb281/current/src/redboot_linux_exec.c
diff -N hal/powerpc/csb281/current/src/redboot_linux_exec.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/csb281/current/src/redboot_linux_exec.c	24 Dec 2002 15:38:20 -0000
@@ -0,0 +1,271 @@
+//==========================================================================
+//
+//      redboot_linux_boot.c
+//
+//      RedBoot command to boot Linux
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####OTHERCOPYRIGHTBEGIN####
+//
+//  The structure definitions below are taken from include/ppc/platforms/am860.h in
+//  the Linux kernel, Copyright (c) 2002 Gary Thomas, Copyright (c) 1997 Dan Malek. 
+//  Their presence here is for the express purpose of communication with the Linux 
+//  kernel being booted and is considered 'fair use' by the original author and
+//  are included with their permission.
+//
+//####OTHERCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    msalter
+// Contributors: gthomas,msalter
+// Date:         2002-01-14
+// Purpose:      
+// Description:  
+//              
+// This code is part of RedBoot (tm).
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <redboot.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+
+#ifdef CYGPKG_REDBOOT_NETWORKING
+#include <net/net.h>
+#endif
+
+#ifdef CYGSEM_REDBOOT_HAL_LINUX_BOOT
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//=========================================================================
+
+// Exported CLI function(s)
+static void do_exec(int argc, char *argv[]);
+RedBoot_cmd("exec", 
+            "Execute a Linux image - with MMU off", 
+            "[-w timeout]\n"
+            "        [-c \"kernel command line\"] [<entry_point>]",
+            do_exec
+    );
+
+//=========================================================================
+// Imported from Linux kernel include/asm-ppc/am860.h
+//   Copyright (c) 2002 Gary Thomas (gary@chez-thomas.org)
+//   Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+//   Used with permission of author(s).
+
+
+/* A Board Information structure that is given to a program when
+ * RedBoot starts it up.
+ */
+typedef struct bd_info {
+	unsigned int	bi_tag;		/* Should be 0x42444944 "BDID" */
+	unsigned int	bi_size;	/* Size of this structure */
+	unsigned int	bi_revision;	/* revision of this structure */
+	unsigned int	bi_bdate;	/* EPPCbug date, i.e. 0x11061997 */
+	unsigned int	bi_memstart;	/* Memory start address */
+	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
+	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
+	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
+	unsigned int	bi_clun;	/* Boot device controller */
+	unsigned int	bi_dlun;	/* Boot device logical dev */
+	unsigned char	bi_enetaddr[6];
+	unsigned int	bi_baudrate;
+        unsigned char   *bi_cmdline;
+} bd_t;
+
+//
+// Execute a Linux kernel - this is a RedBoot CLI command
+//
+static void 
+do_exec(int argc, char *argv[])
+{
+    unsigned long entry;
+    bool wait_time_set, cmd_line_set;
+    int  wait_time;
+    char *cmd_line;
+    char *cline;
+    struct option_info opts[2];
+    hal_virtual_comm_table_t *__chan;
+    int baud_rate;
+
+    bd_t *board_info;
+    CYG_INTERRUPT_STATE oldints;
+    unsigned long sp = CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE;
+    
+    init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM, 
+              (void **)&wait_time, (bool *)&wait_time_set, "wait timeout");
+    init_opts(&opts[1], 'c', true, OPTION_ARG_TYPE_STR, 
+              (void **)&cmd_line, (bool *)&cmd_line_set, "kernel command line");
+    entry = entry_address;  // Default from last 'load' operation
+    if (!scan_opts(argc, argv, 1, opts, 2, (void *)&entry, OPTION_ARG_TYPE_NUM, 
+                   "[physical] starting address")) {
+        return;
+    }
+
+    // Determine baud rate on current console
+    __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+    baud_rate = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_GETBAUD);
+    if (baud_rate <= 0) {
+        baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+    }
+
+    // Make a little space at the top of the stack, and align to
+    // 64-bit boundary.
+    sp = (sp-128) & ~7;  // The Linux boot code uses this space for FIFOs
+    
+    // Copy the commandline onto the stack, and set the SP to just below it.
+    if (cmd_line_set) {
+	int len,i;
+
+	// get length of string
+	for( len = 0; cmd_line[len] != '\0'; len++ );
+
+	// decrement sp by length of string and align to
+	// word boundary.
+	sp = (sp-(len+1)) & ~3;
+
+	// assign this SP value to command line start
+	cline = (char *)sp;
+
+	// copy command line over.
+	for( i = 0; i < len; i++ )
+	    cline[i] = cmd_line[i];
+	cline[len] = '\0';
+
+    } else {
+        cline = (char *)NULL;
+    }
+    
+    // Set up parameter struct at top of stack
+    sp = sp-sizeof(bd_t);
+    board_info = (bd_t *)sp;
+    memset(board_info, sizeof(*board_info), 0);
+    
+    board_info->bi_tag		= 0x42444944;
+    board_info->bi_size		= sizeof(board_info);
+    board_info->bi_revision	= 1;
+    board_info->bi_bdate	= 0x06012002;
+    board_info->bi_memstart	= CYGMEM_REGION_ram;
+    board_info->bi_memsize	= CYGMEM_REGION_ram_SIZE;
+    board_info->bi_intfreq	= CYGHWR_HAL_POWERPC_CPU_SPEED*1000000;
+    board_info->bi_busfreq	= CYGHWR_HAL_POWERPC_MEM_SPEED*1000000;
+    board_info->bi_clun		= 0;  // ????
+    board_info->bi_dlun		= 0;  // ????
+    board_info->bi_baudrate     = baud_rate;
+    board_info->bi_cmdline      = cline;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+    memcpy(board_info->bi_enetaddr, __local_enet_addr, sizeof(enet_addr_t));
+#endif
+
+    // adjust SP to 64 bit boundary, and leave a little space
+    // between it and the commandline for PowerPC calling
+    // conventions.
+	
+    sp = (sp-32)&~7;
+
+    if (wait_time_set) {
+        int script_timeout_ms = wait_time * 1000;
+#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
+        unsigned char *hold_script = script;
+        script = (unsigned char *)0;
+#endif
+        diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
+                    (void *)entry, wait_time);
+        while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
+            int res;
+            char line[80];
+            res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
+            if (res == _GETS_CTRLC) {
+#ifdef CYGFUN_REDBOOT_BOOT_SCRIPT
+                script = hold_script;  // Re-enable script
+#endif
+                return;
+            }
+            script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
+        }
+    }
+
+    // Disable interrupts
+    HAL_DISABLE_INTERRUPTS(oldints);
+
+    // Put the caches to sleep.
+    HAL_DCACHE_SYNC();
+    HAL_ICACHE_DISABLE();
+    HAL_DCACHE_DISABLE();
+    HAL_DCACHE_SYNC();
+    HAL_ICACHE_INVALIDATE_ALL();
+    HAL_DCACHE_INVALIDATE_ALL();
+
+//    diag_printf("entry %08x, sp %08x, info %08x, cmd line %08x, baud %d\n",
+//		entry, sp, board_info, cline, baud_rate);
+//    breakpoint();
+    
+    // Call into Linux
+    __asm__ volatile (        
+	               // Start by disabling MMU - the mappings are
+	               // 1-1 so this should not cause any problems
+	               "mfmsr	3\n"
+		       "li      4,0xFFFFFFCF\n"
+		       "and	3,3,4\n"
+		       "sync\n"
+		       "mtmsr	3\n"
+		       "sync\n"
+
+		       // Now set up parameters to jump into linux
+
+		       "mtlr	%0\n"		// set entry address in LR
+		       "mr	1,%1\n"		// set stack pointer
+		       "mr	3,%2\n"		// set board info in R3
+		       "mr	4,%3\n"		// set command line in R4
+		       "blr          \n"	// jump into linux
+		       :
+		       : "r"(entry),"r"(sp),"r"(board_info),"r"(cline)
+		       : "r3", "r4"
+	             
+	             );
+}
+
+#endif // CYGSEM_REDBOOT_HAL_LINUX_BOOT
+
+//=========================================================================
+// EOF redboot_linux_exec.c
Index: hal/powerpc/ppc60x/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/ChangeLog,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ChangeLog
--- hal/powerpc/ppc60x/current/ChangeLog	23 May 2002 23:04:31 -0000	1.7
+++ hal/powerpc/ppc60x/current/ChangeLog	24 Dec 2002 15:57:00 -0000
@@ -1,5 +1,22 @@
+2002-08-01  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/var_misc.c (cyg_hal_map_memory): Need to set protection bits.
+
+	* include/variant.inc: Additional exceptions.  Also allow for
+	more platform specifics (like INTC lookup macro).
+
+	* include/var_regs.h: Allow for platform registers <cyg/hal/plf_regs.h>
+	Also, flush out HID0 register (used by cache control).
+
+	* include/var_intr.h: Add PPC60x additional exceptions.
+
+	* include/var_cache.h: Initial cache support.
+
+	* cdl/hal_powerpc_ppc60x.cdl: Support various ROM monitor options,
+	matching other variants.
+
 2000-06-13  Jesper Skov  <jskov@redhat.com>
 
 	* cdl/hal_powerpc_ppc60x.cdl: Add vector table location definition.
 
 2000-04-13  Jesper Skov  <jskov@redhat.com>
Index: hal/powerpc/ppc60x/current/cdl/hal_powerpc_ppc60x.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/cdl/hal_powerpc_ppc60x.cdl,v
retrieving revision 1.5
diff -u -5 -p -r1.5 hal_powerpc_ppc60x.cdl
--- hal/powerpc/ppc60x/current/cdl/hal_powerpc_ppc60x.cdl	23 May 2002 23:04:31 -0000	1.5
+++ hal/powerpc/ppc60x/current/cdl/hal_powerpc_ppc60x.cdl	24 Dec 2002 15:56:43 -0000
@@ -7,10 +7,11 @@
 # ====================================================================
 #####ECOSGPLCOPYRIGHTBEGIN####
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
 ## Software Foundation; either version 2 or (at your option) any later version.
 ##
@@ -56,10 +57,32 @@ cdl_package CYGPKG_HAL_POWERPC_PPC60x {
     define_header hal_powerpc_ppc60x.h
     description   "
            The PowerPC 60x variant HAL package provides generic support
            for this processor variant. It is also necessary to
            select a specific target platform HAL package."
+
+    cdl_interface CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED {
+        display       "ROM monitor configuration is unsupported"
+        no_define
+    }
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        bool
+        default_value { (CYG_HAL_STARTUP == "RAM" &&
+                        !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS &&
+                        !CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED &&
+                        !CYGSEM_HAL_POWERPC_COPY_VECTORS) ? 1 : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        requires      ! CYGSEM_HAL_POWERPC_COPY_VECTORS
+        requires      ! CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        requires      ! CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED
+        description   "
+            Allow coexistence with ROM monitor (CygMon or GDB stubs) by
+            only initializing interrupt vectors on startup, thus leaving
+            exception handling to the ROM monitor."
+    }
 
     # Note: This should be sub-variant specific to reduce memory use.
     define_proc {
         puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)"
         puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)"
Index: hal/powerpc/ppc60x/current/include/var_cache.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/include/var_cache.h,v
retrieving revision 1.3
diff -u -5 -p -r1.3 var_cache.h
--- hal/powerpc/ppc60x/current/include/var_cache.h	23 May 2002 23:04:31 -0000	1.3
+++ hal/powerpc/ppc60x/current/include/var_cache.h	24 Dec 2002 15:38:20 -0000
@@ -9,10 +9,11 @@
 //=============================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -41,11 +42,11 @@
 //####ECOSGPLCOPYRIGHTEND####
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   nickg
-// Contributors:nickg, jskov
+// Contributors:nickg, jskov, gthomas
 // Date:        2000-04-02
 // Purpose:     Variant cache control API
 // Description: The macros defined here provide the HAL APIs for handling
 //              cache control operations on the PPC60x variant CPUs.
 // Usage:       Is included via the architecture cache header:
@@ -58,49 +59,96 @@
 
 #include <pkgconf/hal.h>
 #include <cyg/infra/cyg_type.h>
 
 #include <cyg/hal/ppc_regs.h>
-
 #include <cyg/hal/plf_cache.h>
 

 //-----------------------------------------------------------------------------
 // Cache dimensions
 
 // Data cache
-#define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
-#define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
-#define HAL_DCACHE_WAYS                 2       // Associativity of the cache
+#ifndef HAL_DCACHE_SIZE
+#define HAL_DCACHE_SIZE                 16384   // Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE            32      // Size of a data cache line
+#define HAL_DCACHE_WAYS                 4       // Associativity of the cache
+#endif
 
 // Instruction cache
-#define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
-#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
-#define HAL_ICACHE_WAYS                 2       // Associativity of the cache
+#ifndef HAL_ICACHE_SIZE
+#define HAL_ICACHE_SIZE                 16384   // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE            32      // Size of a cache line
+#define HAL_ICACHE_WAYS                 4       // Associativity of the cache
+#endif
 
 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
 //-----------------------------------------------------------------------------
 // Global control of data cache
 
 // Enable the data cache
-#define HAL_DCACHE_ENABLE()
+#define HAL_DCACHE_ENABLE()                     \
+    CYG_MACRO_START                             \
+    cyg_int32 _scratch;                         \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%1;"                \
+                  "or  %0,%0,%2;"               \
+                  "mtspr %1,%0"                 \
+                  : "=&r" (_scratch)            \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_DCE)             \
+        );                                      \
+    CYG_MACRO_END
 
 // Disable the data cache
-#define HAL_DCACHE_DISABLE()
+#define HAL_DCACHE_DISABLE()                    \
+    CYG_MACRO_START                             \
+    cyg_int32 _scratch;                         \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%1;"                \
+                  "andc %0,%0,%2;"              \
+                  "mtspr %1,%0"                 \
+                  : "=&r" (_scratch)            \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_DCE)             \
+        );                                      \
+    CYG_MACRO_END
 
 // Invalidate the entire cache
-#define HAL_DCACHE_INVALIDATE_ALL()
+#define HAL_DCACHE_INVALIDATE_ALL()             \
+    CYG_MACRO_START                             \
+    cyg_int32 _scr1, _scr2;                     \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%2;"                \
+                  "mr %1,%0;"                   \
+                  "or %0,%0,%3;"                \
+                  "mtspr %2,%0;"                \
+                  "mtspr %2,%1"                 \
+                  : "=&r" (_scr1),              \
+                    "=&r" (_scr2)               \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_DCFI)            \
+        );                                      \
+    CYG_MACRO_END
 
 // Synchronize the contents of the cache with memory.
 #define HAL_DCACHE_SYNC()
 
 // Query the state of the data cache
 #define HAL_DCACHE_IS_ENABLED(_state_)          \
     CYG_MACRO_START                             \
-    (_state_) = 0;                              \
+    cyg_int32 _scratch;                         \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%1;"                \
+                  "and %0,%0,%2;"               \
+                  : "=&r" (_scratch)            \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_DCE)             \
+        );                                      \
+    (_state_) = _scratch != 0;                  \
     CYG_MACRO_END
 
 // Set the data cache refill burst size
 //#define HAL_DCACHE_BURST_SIZE(_size_)
 
@@ -127,48 +175,147 @@
 // contents from memory.
 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
 // Write dirty cache lines to memory and invalidate the cache entries
 // for the given address range.
-//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
-
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
+   
 // Invalidate cache lines in the given range without writing to memory.
-//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbi 0,%0;sync;" : : "r" (__base));      \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
 
 // Write dirty cache lines to memory for the given address range.
-//#define HAL_DCACHE_STORE( _base_ , _size_ )
+#define HAL_DCACHE_STORE( _base_ , _size_ )                     \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbst 0,%0;sync;" : : "r" (__base));     \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
 
 // Preread the given range into the cache with the intention of reading
 // from it later.
-//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+#define HAL_DCACHE_READ_HINT( _base_ , _size_ )                 \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbt 0,%0;" : : "r" (__base));           \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
 
 // Preread the given range into the cache with the intention of writing
 // to it later.
-//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )                \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbtst 0,%0;" : : "r" (__base));         \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
 
 // Allocate and zero the cache lines associated with the given range.
-//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+#define HAL_DCACHE_ZERO( _base_ , _size_ )                      \
+    CYG_MACRO_START                                             \
+    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
+    cyg_int32 __size = (cyg_int32) (_size_);                    \
+    while (__size > 0) {                                        \
+        asm volatile ("dcbz 0,%0;" : : "r" (__base));           \
+        __base += HAL_DCACHE_LINE_SIZE;                         \
+        __size -= HAL_DCACHE_LINE_SIZE;                         \
+    }                                                           \
+    CYG_MACRO_END
 
 //-----------------------------------------------------------------------------
 // Global control of Instruction cache
 
 // Enable the instruction cache
-#define HAL_ICACHE_ENABLE()
+#define HAL_ICACHE_ENABLE()                     \
+    CYG_MACRO_START                             \
+    cyg_int32 _scratch;                         \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%1;"                \
+                  "or  %0,%0,%2;"               \
+                  "mtspr %1,%0"                 \
+                  : "=&r" (_scratch)            \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_ICE)             \
+        );                                      \
+    CYG_MACRO_END
 
 // Disable the instruction cache
-#define HAL_ICACHE_DISABLE()
+#define HAL_ICACHE_DISABLE()                    \
+    CYG_MACRO_START                             \
+    cyg_int32 _scratch;                         \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%1;"                \
+                  "andc %0,%0,%2;"              \
+                  "mtspr %1,%0"                 \
+                  : "=&r" (_scratch)            \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_ICE)             \
+        );                                      \
+    CYG_MACRO_END
 
 // Invalidate the entire cache
-#define HAL_ICACHE_INVALIDATE_ALL()
+#define HAL_ICACHE_INVALIDATE_ALL()             \
+    CYG_MACRO_START                             \
+    cyg_int32 _scr1, _scr2;                     \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%2;"                \
+                  "mr %1,%0;"                   \
+                  "or %0,%0,%3;"                \
+                  "mtspr %2,%0;"                \
+                  "mtspr %2,%1"                 \
+                  : "=&r" (_scr1),              \
+                    "=&r" (_scr2)               \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_ICFI)            \
+        );                                      \
+    CYG_MACRO_END
 
 // Synchronize the contents of the cache with memory.
-#define HAL_ICACHE_SYNC()
+#define HAL_ICACHE_SYNC()                       \
+  HAL_ICACHE_INVALIDATE_ALL()
 
 // Query the state of the instruction cache
 #define HAL_ICACHE_IS_ENABLED(_state_)          \
     CYG_MACRO_START                             \
-    (_state_) = 0;                              \
+    cyg_int32 _scratch;                         \
+    asm volatile ("isync;"                      \
+                  "mfspr %0,%1;"                \
+                  "and %0,%0,%2;"               \
+                  : "=&r" (_scratch)            \
+                  : "I" (CYGARC_REG_HID0),      \
+                    "r" (_HID0_ICE)             \
+        );                                      \
+    (_state_) = _scratch != 0;                  \
     CYG_MACRO_END
 
 // Set the instruction cache refill burst size
 //#define HAL_ICACHE_BURST_SIZE(_size_)
 
Index: hal/powerpc/ppc60x/current/include/var_intr.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/include/var_intr.h,v
retrieving revision 1.3
diff -u -5 -p -r1.3 var_intr.h
--- hal/powerpc/ppc60x/current/include/var_intr.h	23 May 2002 23:04:31 -0000	1.3
+++ hal/powerpc/ppc60x/current/include/var_intr.h	24 Dec 2002 15:38:20 -0000
@@ -9,10 +9,11 @@
 //=============================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -41,11 +42,11 @@
 //####ECOSGPLCOPYRIGHTEND####
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):   nickg
-// Contributors:nickg, jskov, jlarmour, hmt
+// Contributors:nickg, jskov, jlarmour, hmt, gthomas
 // Date:        2000-04-02
 // Purpose:     Variant interrupt support
 // Description: The macros defined here provide the HAL APIs for handling
 //              interrupts and the clock on the PPC60x variant CPUs.
 // Usage:       Is included via the architecture interrupt header:
@@ -54,10 +55,20 @@
 //
 //####DESCRIPTIONEND####
 //
 //=============================================================================
 
+// Additional trap/exceptions on PPC60x
+#define CYGNUM_HAL_VECTOR_ITLB_MISS        0x10
+#define CYGNUM_HAL_VECTOR_DTLB_LOAD_MISS   0x11
+#define CYGNUM_HAL_VECTOR_DTLB_STORE_MISS  0x12
+#define CYGNUM_HAL_VECTOR_SMI              0x13
+
+#define CYGNUM_HAL_VSR_MAX                 CYGNUM_HAL_VECTOR_SMI
+
 // No builtin interrupt controller in the PPC60x CPUs.
+
+#include <cyg/hal/plf_intr.h>  // Maybe something on the platform though
 
 //-----------------------------------------------------------------------------
 #endif // ifndef CYGONCE_VAR_INTR_H
 // End of var_intr.h
Index: hal/powerpc/ppc60x/current/include/var_regs.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/include/var_regs.h,v
retrieving revision 1.3
diff -u -5 -p -r1.3 var_regs.h
--- hal/powerpc/ppc60x/current/include/var_regs.h	23 May 2002 23:04:31 -0000	1.3
+++ hal/powerpc/ppc60x/current/include/var_regs.h	24 Dec 2002 15:38:20 -0000
@@ -57,17 +57,37 @@
 //
 //####DESCRIPTIONEND####
 //
 //==========================================================================
 
+#include <cyg/hal/plf_regs.h>  // Get any platform specifics
+
 //--------------------------------------------------------------------------
 // Cache
 #define CYGARC_REG_HID0   1008
-
-#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
-#define HID0       CYGARC_REG_HID0
-#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#define _HID0       CYGARC_REG_HID0
+#define _HID0_EMCP  0x80000000  // Enable machine check
+#define _HID0_EBA   0x20000000  // Enable bus address parity
+#define _HID0_EBD   0x10000000  // Enable bus data parity
+#define _HID0_BCLK  0x08000000
+#define _HID0_EICE  0x04000000
+#define _HID0_ECLK  0x02000000
+#define _HID0_PAR   0x01000000
+#define _HID0_DOZE  0x00800000
+#define _HID0_NAP   0x00400000
+#define _HID0_SLEEP 0x00200000
+#define _HID0_DPM   0x00100000
+#define _HID0_ICE   0x00008000  // Enable Instruction Cache
+#define _HID0_DCE   0x00004000  // Enable Data Cache
+#define _HID0_ILOCK 0x00002000  // Instruction Cache Lock
+#define _HID0_DLOCK 0x00001000  // Data Cache Lock
+#define _HID0_ICFI  0x00000800  // Instruction Cache [flash] Invalidate
+#define _HID0_DCFI  0x00000400  // Data Cache [flash] Invalidate
+#define _HID0_IFEM  0x00000080
+#define _HID0_FBIOB 0x00000010
+#define _HID0_ABE   0x00000008
+#define _HID0_NOOPT 0x00000001
 
 //--------------------------------------------------------------------------
 // BATs
 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 #define IBAT0U          528
Index: hal/powerpc/ppc60x/current/include/variant.inc
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/include/variant.inc,v
retrieving revision 1.4
diff -u -5 -p -r1.4 variant.inc
--- hal/powerpc/ppc60x/current/include/variant.inc	23 May 2002 23:04:31 -0000	1.4
+++ hal/powerpc/ppc60x/current/include/variant.inc	24 Dec 2002 15:38:20 -0000
@@ -9,10 +9,11 @@
 ##=============================================================================
 #####ECOSGPLCOPYRIGHTBEGIN####
 ## -------------------------------------------
 ## This file is part of eCos, the Embedded Configurable Operating System.
 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2002 Gary Thomas
 ##
 ## eCos is free software; you can redistribute it and/or modify it under
 ## the terms of the GNU General Public License as published by the Free
 ## Software Foundation; either version 2 or (at your option) any later version.
 ##
@@ -41,13 +42,13 @@
 #####ECOSGPLCOPYRIGHTEND####
 ##=============================================================================
 #######DESCRIPTIONBEGIN####
 ##
 ## Author(s): 	jskov
-## Contributors:jskov
+## Contributors:jskov, gthomas
 ## Date:	2000-02-04
-## Purpose:	MPC8xx family definitions.
+## Purpose:	PPC60x family definitions.
 ## Description:	This file contains various definitions and macros that are
 ##              useful for writing assembly code for the PPC60x CPU family.
 ## Usage:
 ##		#include <cyg/hal/variant.inc>
 ##		...
@@ -58,15 +59,21 @@
 ##=============================================================================
 
 #include <pkgconf/hal.h>
 	
 #include <cyg/hal/arch.inc>
+#include <cyg/hal/platform.inc>
 
 ##-----------------------------------------------------------------------------
 ## PPC60x defined vectors
 
         .macro hal_extra_vectors
+        exception_vector        instruction_TLB
+        exception_vector        data_load_TLB
+        exception_vector        data_store_TLB
+        exception_vector        instruction_address_breakpoint
+        exception_vector        system_management_interrupt
         .endm
 
 ##-----------------------------------------------------------------------------
 ## PPC60x CPU initialization
 ##
Index: hal/powerpc/ppc60x/current/src/var_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc60x/current/src/var_misc.c,v
retrieving revision 1.5
diff -u -5 -p -r1.5 var_misc.c
--- hal/powerpc/ppc60x/current/src/var_misc.c	23 May 2002 23:04:31 -0000	1.5
+++ hal/powerpc/ppc60x/current/src/var_misc.c	24 Dec 2002 15:38:20 -0000
@@ -7,10 +7,11 @@
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
 // Software Foundation; either version 2 or (at your option) any later version.
 //
@@ -85,11 +86,11 @@ cyg_hal_map_memory (int id,CYG_ADDRESS v
 {
     // Use BATs to map the memory.
     cyg_uint32 ubat, lbat;
 
     ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP;
-    lbat = (phys & LBAT_BRPNMASK);
+    lbat = (phys & LBAT_BRPNMASK) | LBAT_PP_RW;
     if (flags & CYGARC_MEMDESC_CI) 
         lbat |= LBAT_I;
     if (flags & CYGARC_MEMDESC_GUARDED) 
         lbat |= LBAT_G;
         


-- 
------------------------------------------------------------
Gary Thomas                 |
MLB Associates              |  Consulting for the
+1 (970) 229-1963           |    Embedded world
http://www.mlbassoc.com/    |
email: <gary@mlbassoc.com>  |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------


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