This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
Re: OpenRISC eCos port
- From: Jonathan Larmour <jifl at eCosCentric dot com>
- To: Scott Furman <sfurman at rosum dot com>
- Cc: ecos-patches at sources dot redhat dot com
- Date: Fri, 25 Apr 2003 05:00:00 +0100
- Subject: Re: OpenRISC eCos port
- References: <3E9F8CDC.5090601@rosum.com>
Scott Furman wrote:
About six weeks ago I submitted an architectural port to OpenRISC for
review. I received some initial feedback, but I was wondering if I
could get a detailed review in preparation for the code being checked in
? (Yes, I know that you guys were all busy with eCos 2.0, which is why
I waited before harassing you :)
I have included the latest snapshot of the port, which has a few minor
bug fixes (~15 lines code) since the previous posted snapshot.
Yep, big patches are (unsurprisingly) more difficult to find the time to
review. I've been looking at this off-and-on for a while now - sorry it's
taken so long.
Here's some questions though:
* .text.ram - that isn't used in the orp MLT files, nor the
CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM option present. Is this right?
* Is there definitely no sbss? Nor will there ever be? Just making sure
it's an architectural property, not just one of the current compiler.
* Exception interrupt vectors are copied from ROM to 0x100. Is that
address a strict architectural requirement? I just want to avoid anything
like the current problem we have with the ARM HAL which assumes RAM starts
at 0. If it isn't a requirement something like #including
CYGHWR_MEMORY_LAYOUT_H and using CYGMEM_REGION_RAM+0x100 would be the way.
But I don't know what OpenRISC actually needs :-).
* The invocation of cyg_hal_exception_handler doesn't look right...
nothing is saved! Otherwise if you take an exception there's no saved
register state to point at... vital for the GDB stub at least. This way
CYGSEM_HAL_ROM_MONITOR will get used as it's meant to as well (since it
isn't used at all right now ;)).
* I can't help but think that check_for_external_interrupts should live in
the platform HAL as the platform has a better idea of the external
interrupts supported and therefore the relative priorities.
* You add a comment in hal_openrisc_orp.cdl about CYGNUM_HAL_RTC_PERIOD
which should be calculated not default_value. Indeed that's what the CDL
option CYGNUM_KERNEL_COUNTERS_CLOCK_OVERRIDE_PERIOD is for.
* If you're using this with RedBoot do you have a potted .ecm file to go
with this? And also when we're done, remember to send me some prebuilt
known good redboot images I can check in to our redboot image repository
(ecos/images which isn't checked out by default so you won't have seen it).
I've made a number of minor tweaks myself, and I've attached the patches
for those - almost all trivial as you can see - I haven't even bothered
ChangeLog'ing the comment only changes. I've probably mucked up the linker
script changes I made.... I just noticed a few omissions and then I got a
bit carried away, sorry. So it will need to be checked :-|. It's all to
some extent future-proofing it against future compiler changes - we've
been bitten by missing stuff out in the past. I did still leave out sbss
from the MLT files though.
What I'll do is check in what I've got right now anyway as CVS is probably
the easiest way for you to work with this now anyway to avoid merge
conflicts. But _not_ the ecos.db change, nor adding it to NEWS, nor
http://sources.redhat.com/ecos/hardware.html (for which I'll need some
info from you about board availability if possible!). Then when we've
sorted out the above issues we can make it go live.
I have to say overall that for a first architectural port, this is rather
good.
Thanks for the contribution!
Jifl
--
eCosCentric http://www.eCosCentric.com/ The eCos and RedBoot experts
--[ "You can complain because roses have thorns, or you ]--
--[ can rejoice because thorns have roses." -Lincoln ]-- Opinions==mine
diff -urN orig/packages/devs/flash/openrisc/orp/current/ChangeLog packages/devs/flash/openrisc/orp/current/ChangeLog
--- orig/packages/devs/flash/openrisc/orp/current/ChangeLog Thu Mar 6 20:42:20 2003
+++ packages/devs/flash/openrisc/orp/current/ChangeLog Thu Apr 24 04:47:31 2003
@@ -1,4 +1,5 @@
2003-03-06 Scott Furman <sfurman at rosum dot com>
+
* src/openrisc_orp_flash.c, cdl/flash_openrisc_orp.cdl
New package: Flash programming for AMD AM29LVxxxxx devices
used with OpenRISC Reference Platform (ORP).
@@ -8,7 +9,6 @@
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
diff -urN orig/packages/devs/flash/openrisc/orp/current/cdl/flash_openrisc_orp.cdl packages/devs/flash/openrisc/orp/current/cdl/flash_openrisc_orp.cdl
--- orig/packages/devs/flash/openrisc/orp/current/cdl/flash_openrisc_orp.cdl Mon Feb 17 20:04:14 2003
+++ packages/devs/flash/openrisc/orp/current/cdl/flash_openrisc_orp.cdl Thu Apr 24 04:48:07 2003
@@ -40,9 +40,9 @@
# ====================================================================
######DESCRIPTIONBEGIN####
#
-# Author(s): jskov
-# Contributors: jskov
-# Date: 2000-12-05
+# Author(s): sfurman
+# Contributors:
+# Date: 2003-04-24
#
#####DESCRIPTIONEND####
#
@@ -68,3 +68,5 @@
implements CYGINT_DEVS_FLASH_AMD_AM29XXXXX_REQUIRED
requires CYGHWR_DEVS_FLASH_AMD_AM29LV160
}
+
+# EOF flash_openrisc_orp.cdl
diff -urN orig/packages/devs/flash/openrisc/orp/current/src/openrisc_orp_flash.c packages/devs/flash/openrisc/orp/current/src/openrisc_orp_flash.c
--- orig/packages/devs/flash/openrisc/orp/current/src/openrisc_orp_flash.c Thu Mar 6 20:23:37 2003
+++ packages/devs/flash/openrisc/orp/current/src/openrisc_orp_flash.c Thu Apr 24 04:49:06 2003
@@ -41,9 +41,9 @@
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): jskov
-// Contributors: jskov
-// Date: 2001-05-22
+// Author(s): sfurman
+// Contributors:
+// Date: 2003-04-24
// Purpose:
// Description:
//
@@ -67,4 +67,4 @@
#include "cyg/io/flash_am29xxxxx.inl"
// ------------------------------------------------------------------------
-// EOF mips_ocelot_flash.c
+// EOF openrisc_orp_flash.c
diff -urN orig/packages/hal/openrisc/arch/current/ChangeLog packages/hal/openrisc/arch/current/ChangeLog
--- orig/packages/hal/openrisc/arch/current/ChangeLog Fri Apr 18 00:36:34 2003
+++ packages/hal/openrisc/arch/current/ChangeLog Fri Apr 25 03:53:19 2003
@@ -1,8 +1,16 @@
-2003-04-17 Scott Furman <sfurman at rosum dot com>
- + Init tick timer on boot
- + Ensure stack is aligned in HAL_INIT_CONTEXT()
- + Add .text.ram section for time-critical code
+2003-04-25 Jonathan Larmour <jifl at eCosCentric dot com>
+
+ * src/openrisc.ld: Add some missing sections mostly just by comparison
+ with another HAL..
+ * include/hal_cache.h: Include hal_arch.h for MTSPR/MFSPR.
+
+2003-04-17 Scott Furman <sfurman at rosum dot com>
+
+ * src/vectors.S: Init tick timer on boot
+ * include/hal_arch.h: Ensure stack is aligned in
+ HAL_THREAD_INIT_CONTEXT()
+ * openrisc.ld: Add .text.ram section for time-critical code
2003-03-06 Scott Furman <sfurman at rosum dot com>
@@ -13,7 +21,6 @@
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
diff -urN orig/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl
--- orig/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl Wed Mar 5 01:14:41 2003
+++ packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl Thu Apr 24 04:54:37 2003
@@ -109,3 +109,5 @@
memory access speed settings."
}
}
+
+# EOF hal_openrisc.cdl
diff -urN orig/packages/hal/openrisc/arch/current/doc/build_or32_elf_tools.sh packages/hal/openrisc/arch/current/doc/build_or32_elf_tools.sh
--- orig/packages/hal/openrisc/arch/current/doc/build_or32_elf_tools.sh Wed Mar 19 01:25:10 2003
+++ packages/hal/openrisc/arch/current/doc/build_or32_elf_tools.sh Thu Jan 1 01:00:00 1970
@@ -1,156 +0,0 @@
-#!/bin/bash -x
-
-# Checkout and build gnu toolchain for OpenRISC (or32 target)
-
-# Usage:
-# build_or32_elf_tools.sh [-c]
-# -c Controls whether CVS checkout is done prior to build
-# You probably only want to use this command-line option the first time you build.
-
-# Directory in which to checkout sources and build
-BUILD_DIR=$HOME/or32-elf-src
-
-# Target architecture/OS
-TARGET=or32-elf
-
-# Directory in which to put compiled files, exported headers, etc.
-INSTALL_PREFIX=$HOME/tools/i386-redhat-linux
-
-########################################################################
-
-if [ $1foo = -cfoo ]; then DO_CVS_CHECKOUT=1; else DO_CVS_CHECKOUT=0; fi
-
-#
-# Some common variables
-#
-OK_STR="Build OK"
-FAIL_STR="Build Failed"
-
-mkdir -p $BUILD_DIR
-cd $BUILD_DIR
-
-#
-# Start with binutils
-#
-if [ $DO_CVS_CHECKOUT != 0 ]; then
-date > checkout_binutils.log 2>&1
-cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d binutils or1k/binutils >> \
- checkout_binutils.log 2>&1
-fi
-
-mkdir -p b-b
-cd b-b
-date > ../build_binutils.log 2>&1
-
-../binutils/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_binutils.log 2>&1
-
-make all install >> ../build_binutils.log 2>&1
-BUILD_BINUTILS_STATUS=$?
-export PATH=$INSTALL_PREFIX/bin:$PATH
-cd ..
-
-#
-# Check if binutils was built and installed correctly
-#
-if [ $BUILD_BINUTILS_STATUS = 0 ]; then
- echo "$OK_STR (`date`)" >> build_binutils.log
-else
- echo "$FAIL_STR (`date`)" >> build_binutils.log
-fi
-
-#
-# Build gdb
-#
-if [ $DO_CVS_CHECKOUT != 0 ]; then
-date > checkout_gdb.log 2>&1
-cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d gdb or1k/gdb-5.0 >> checkout_gdb.log 2>&1
-fi
-
-mkdir -p b-gdb
-cd b-gdb
-date > ../build_gdb.log 2>&1
-# Current version of readline has a configuration bug, so you must not specify
-# the prefix
-#../gdb/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_gdb.log 2>&1
-../gdb/configure --target=$TARGET >> ../build_gdb.log 2>&1
-make all >> ../build_gdb.log 2>&1
-BUILD_GDB_STATUS=$?
-cp gdb/gdb $INSTALL_PREFIX/bin/$TARGET-gdb
-cd ..
-
-
-#
-# Check if gdb was built and installed correctly
-#
-if [ $BUILD_GDB_STATUS = 0 ]; then
- echo "$OK_STR (`date`)" >> build_gdb.log
-else
- echo "$FAIL_STR (`date`)" >> build_gdb.log
-fi
-
-#
-# Build or1k simulator
-#
-if [ $DO_CVS_CHECKOUT != 0 ]; then
-date > checkout_or1ksim.log 2>&1
-cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d or1ksim or1k/or1ksim >> checkout_or1ksim.log 2>&1
-fi
-
-cd or1ksim
-date > ../build_or1ksim.log 2>&1
-../or1ksim/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_or1ksim.log 2>&1
-make all install >> ../build_or1ksim.log 2>&1
-BUILD_OR1KSIM_STATUS=$?
-cp sim $INSTALL_PREFIX/bin/or32-elf-sim
-cd ..
-
-#
-# Check if or1ksim was built and installed correctly
-#
-if [ $BUILD_OR1KSIM_STATUS = 0 ]; then
- echo "$OK_STR (`date`)" >> build_or1ksim.log
-else
- echo "$FAIL_STR (`date`)" >> build_or1ksim.log
-fi
-
-# For now, bail here
-#exit
-
-#
-# Build gcc
-#
-if [ $DO_CVS_CHECKOUT != 0 ]; then
-date > checkout_gcc.log 2>&1
-cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d gcc or1k/gcc-3.1 >> checkout_gcc.log 2>&1
-fi
-
-# The config script looks for libraries in a weird place. Instead of figuring out what's wrong,
-# I just placate it.
-
-pushd $INSTALL_PREFIX
-cp -pr lib $TARGET
-popd
-
-mkdir -p b-gcc
-cd b-gcc
-date > ../build_gcc.log 2>&1
-../gcc/configure --target=$TARGET \
- --with-gnu-as --with-gnu-ld --verbose \
- --enable-threads --prefix=$INSTALL_PREFIX \
- --enable-languages="c,c++" >> ../build_gcc.log 2>&1
-make all install >> ../build_gcc.log 2>&1
-BUILD_GCC_STATUS=$?
-
-#
-# Check if gcc was built and installed correctly
-#
-if [ $BUILD_GCC_STATUS = 0 ]; then
- echo "$OK_STR (`date`)" >> build_gcc.log
-else
- echo "$FAIL_STR (`date`)" >> build_gcc.log
-fi
-
-# Install even though g++ build fails due to inability to build libg++ without C library.
-# (How do we prevent building of libg++ ?)
-make install
-
diff -urN orig/packages/hal/openrisc/arch/current/include/arch.inc packages/hal/openrisc/arch/current/include/arch.inc
--- orig/packages/hal/openrisc/arch/current/include/arch.inc Sat Apr 12 23:03:27 2003
+++ packages/hal/openrisc/arch/current/include/arch.inc Thu Apr 24 04:54:52 2003
@@ -104,3 +104,5 @@
#include <cyg/hal/platform.inc>
#endif // #ifndef CYGONCE_HAL_ARCH_INC
+
+// EOF arch.inc
diff -urN orig/packages/hal/openrisc/arch/current/include/hal_cache.h packages/hal/openrisc/arch/current/include/hal_cache.h
--- orig/packages/hal/openrisc/arch/current/include/hal_cache.h Wed Mar 5 01:15:30 2003
+++ packages/hal/openrisc/arch/current/include/hal_cache.h Thu Apr 24 04:56:55 2003
@@ -82,6 +82,8 @@
#ifndef __ASSEMBLER__
+#include <cyg/hal/hal_arch.h>
+
//-----------------------------------------------------------------------------
// Global control of data cache
diff -urN orig/packages/hal/openrisc/arch/current/include/openrisc_opcode.h packages/hal/openrisc/arch/current/include/openrisc_opcode.h
--- orig/packages/hal/openrisc/arch/current/include/openrisc_opcode.h Wed Mar 5 01:17:08 2003
+++ packages/hal/openrisc/arch/current/include/openrisc_opcode.h Thu Apr 24 05:01:48 2003
@@ -90,3 +90,5 @@
#define OP_JALR 0x12
#endif /* _OPENRISC_OPCODE_H */
+
+// EOF openrisc_opcode.h
diff -urN orig/packages/hal/openrisc/arch/current/include/openrisc_stub.h packages/hal/openrisc/arch/current/include/openrisc_stub.h
--- orig/packages/hal/openrisc/arch/current/include/openrisc_stub.h Sat Mar 8 01:11:57 2003
+++ packages/hal/openrisc/arch/current/include/openrisc_stub.h Thu Apr 24 05:03:23 2003
@@ -164,3 +164,5 @@
externC void __clear_breakpoints (void);
#endif // ifndef CYGONCE_HAL_OPENRISC_STUB_H
+
+// EOF openrisc_stub.h
diff -urN orig/packages/hal/openrisc/arch/current/include/spr_defs.h packages/hal/openrisc/arch/current/include/spr_defs.h
--- orig/packages/hal/openrisc/arch/current/include/spr_defs.h Wed Mar 5 01:41:39 2003
+++ packages/hal/openrisc/arch/current/include/spr_defs.h Thu Apr 24 05:03:57 2003
@@ -462,3 +462,5 @@
#define SPR_TTMR_M 0xc0000000 /* Tick mode */
#endif
+
+// EOF spr_defs.h
diff -urN orig/packages/hal/openrisc/arch/current/misc/build_or32_elf_tools.sh packages/hal/openrisc/arch/current/misc/build_or32_elf_tools.sh
--- orig/packages/hal/openrisc/arch/current/misc/build_or32_elf_tools.sh Thu Jan 1 01:00:00 1970
+++ packages/hal/openrisc/arch/current/misc/build_or32_elf_tools.sh Wed Mar 19 01:25:10 2003
@@ -0,0 +1,156 @@
+#!/bin/bash -x
+
+# Checkout and build gnu toolchain for OpenRISC (or32 target)
+
+# Usage:
+# build_or32_elf_tools.sh [-c]
+# -c Controls whether CVS checkout is done prior to build
+# You probably only want to use this command-line option the first time you build.
+
+# Directory in which to checkout sources and build
+BUILD_DIR=$HOME/or32-elf-src
+
+# Target architecture/OS
+TARGET=or32-elf
+
+# Directory in which to put compiled files, exported headers, etc.
+INSTALL_PREFIX=$HOME/tools/i386-redhat-linux
+
+########################################################################
+
+if [ $1foo = -cfoo ]; then DO_CVS_CHECKOUT=1; else DO_CVS_CHECKOUT=0; fi
+
+#
+# Some common variables
+#
+OK_STR="Build OK"
+FAIL_STR="Build Failed"
+
+mkdir -p $BUILD_DIR
+cd $BUILD_DIR
+
+#
+# Start with binutils
+#
+if [ $DO_CVS_CHECKOUT != 0 ]; then
+date > checkout_binutils.log 2>&1
+cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d binutils or1k/binutils >> \
+ checkout_binutils.log 2>&1
+fi
+
+mkdir -p b-b
+cd b-b
+date > ../build_binutils.log 2>&1
+
+../binutils/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_binutils.log 2>&1
+
+make all install >> ../build_binutils.log 2>&1
+BUILD_BINUTILS_STATUS=$?
+export PATH=$INSTALL_PREFIX/bin:$PATH
+cd ..
+
+#
+# Check if binutils was built and installed correctly
+#
+if [ $BUILD_BINUTILS_STATUS = 0 ]; then
+ echo "$OK_STR (`date`)" >> build_binutils.log
+else
+ echo "$FAIL_STR (`date`)" >> build_binutils.log
+fi
+
+#
+# Build gdb
+#
+if [ $DO_CVS_CHECKOUT != 0 ]; then
+date > checkout_gdb.log 2>&1
+cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d gdb or1k/gdb-5.0 >> checkout_gdb.log 2>&1
+fi
+
+mkdir -p b-gdb
+cd b-gdb
+date > ../build_gdb.log 2>&1
+# Current version of readline has a configuration bug, so you must not specify
+# the prefix
+#../gdb/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_gdb.log 2>&1
+../gdb/configure --target=$TARGET >> ../build_gdb.log 2>&1
+make all >> ../build_gdb.log 2>&1
+BUILD_GDB_STATUS=$?
+cp gdb/gdb $INSTALL_PREFIX/bin/$TARGET-gdb
+cd ..
+
+
+#
+# Check if gdb was built and installed correctly
+#
+if [ $BUILD_GDB_STATUS = 0 ]; then
+ echo "$OK_STR (`date`)" >> build_gdb.log
+else
+ echo "$FAIL_STR (`date`)" >> build_gdb.log
+fi
+
+#
+# Build or1k simulator
+#
+if [ $DO_CVS_CHECKOUT != 0 ]; then
+date > checkout_or1ksim.log 2>&1
+cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d or1ksim or1k/or1ksim >> checkout_or1ksim.log 2>&1
+fi
+
+cd or1ksim
+date > ../build_or1ksim.log 2>&1
+../or1ksim/configure --target=$TARGET --prefix=$INSTALL_PREFIX >> ../build_or1ksim.log 2>&1
+make all install >> ../build_or1ksim.log 2>&1
+BUILD_OR1KSIM_STATUS=$?
+cp sim $INSTALL_PREFIX/bin/or32-elf-sim
+cd ..
+
+#
+# Check if or1ksim was built and installed correctly
+#
+if [ $BUILD_OR1KSIM_STATUS = 0 ]; then
+ echo "$OK_STR (`date`)" >> build_or1ksim.log
+else
+ echo "$FAIL_STR (`date`)" >> build_or1ksim.log
+fi
+
+# For now, bail here
+#exit
+
+#
+# Build gcc
+#
+if [ $DO_CVS_CHECKOUT != 0 ]; then
+date > checkout_gcc.log 2>&1
+cvs -d :pserver:cvs at cvs dot opencores dot org:/home/oc/cvs -z9 co -d gcc or1k/gcc-3.1 >> checkout_gcc.log 2>&1
+fi
+
+# The config script looks for libraries in a weird place. Instead of figuring out what's wrong,
+# I just placate it.
+
+pushd $INSTALL_PREFIX
+cp -pr lib $TARGET
+popd
+
+mkdir -p b-gcc
+cd b-gcc
+date > ../build_gcc.log 2>&1
+../gcc/configure --target=$TARGET \
+ --with-gnu-as --with-gnu-ld --verbose \
+ --enable-threads --prefix=$INSTALL_PREFIX \
+ --enable-languages="c,c++" >> ../build_gcc.log 2>&1
+make all install >> ../build_gcc.log 2>&1
+BUILD_GCC_STATUS=$?
+
+#
+# Check if gcc was built and installed correctly
+#
+if [ $BUILD_GCC_STATUS = 0 ]; then
+ echo "$OK_STR (`date`)" >> build_gcc.log
+else
+ echo "$FAIL_STR (`date`)" >> build_gcc.log
+fi
+
+# Install even though g++ build fails due to inability to build libg++ without C library.
+# (How do we prevent building of libg++ ?)
+make install
+
diff -urN orig/packages/hal/openrisc/arch/current/src/openrisc.ld packages/hal/openrisc/arch/current/src/openrisc.ld
--- orig/packages/hal/openrisc/arch/current/src/openrisc.ld Thu Mar 27 03:38:01 2003
+++ packages/hal/openrisc/arch/current/src/openrisc.ld Fri Apr 25 03:26:21 2003
@@ -53,7 +53,11 @@
#ifdef EXTRAS
INPUT(extras.o)
#endif
+#if (__GNUC__ >= 3)
+GROUP(libtarget.a libgcc.a libsupc++.a)
+#else
GROUP(libtarget.a libgcc.a)
+#endif
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
@@ -63,17 +67,101 @@
#define SECTIONS_BEGIN
+#define SECTION_ROMISC(_region_, _vma_, _lma_) \
+ .interp _vma_ : _lma_ { *(.interp) } > _region_ \
+ .hash : FOLLOWING(.interp) { *(.hash) } > _region_ \
+ .dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \
+ .dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \
+ .gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \
+ .gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \
+ .gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \
+ .plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_
+
+#define SECTION_eh_frame(_region_, _vma_, _lma_) \
+ .eh_frame _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; __EH_FRAME_BEGIN__ = .; \
+ KEEP(*(.eh_frame)) \
+ __FRAME_END__ = .; \
+ . = . + 8; \
+ } > _region_ = 0
+
+#define SECTION_RELOCS(_region_, _vma_, _lma_) \
+ .rel.text : \
+ { \
+ *(.rel.text) \
+ *(.rel.text.*) \
+ *(.rel.gnu.linkonce.t*) \
+ } > _region_ \
+ .rela.text : \
+ { \
+ *(.rela.text) \
+ *(.rela.text.*) \
+ *(.rela.gnu.linkonce.t*) \
+ } > _region_ \
+ .rel.data : \
+ { \
+ *(.rel.data) \
+ *(.rel.data.*) \
+ *(.rel.gnu.linkonce.d*) \
+ } > _region_ \
+ .rela.data : \
+ { \
+ *(.rela.data) \
+ *(.rela.data.*) \
+ *(.rela.gnu.linkonce.d*) \
+ } > _region_ \
+ .rel.rodata : \
+ { \
+ *(.rel.rodata) \
+ *(.rel.rodata.*) \
+ *(.rel.gnu.linkonce.r*) \
+ } > _region_ \
+ .rela.rodata : \
+ { \
+ *(.rela.rodata) \
+ *(.rela.rodata.*) \
+ *(.rela.gnu.linkonce.r*) \
+ } > _region_ \
+ .rel.got : { *(.rel.got) } > _region_ \
+ .rela.got : { *(.rela.got) } > _region_ \
+ .rel.ctors : { *(.rel.ctors) } > _region_ \
+ .rela.ctors : { *(.rela.ctors) } > _region_ \
+ .rel.dtors : { *(.rel.dtors) } > _region_ \
+ .rela.dtors : { *(.rela.dtors) } > _region_ \
+ .rel.init : { *(.rel.init) } > _region_ \
+ .rela.init : { *(.rela.init) } > _region_ \
+ .rel.fini : { *(.rel.fini) } > _region_ \
+ .rela.fini : { *(.rela.fini) } > _region_ \
+ .rel.bss : { *(.rel.bss) } > _region_ \
+ .rela.bss : { *(.rela.bss) } > _region_ \
+ .rel.plt : { *(.rel.plt) } > _region_ \
+ .rela.plt : { *(.rela.plt) } > _region_ \
+ .rel.dyn : { *(.rel.dyn) } > _region_
+
#define SECTION_vectors(_region_, _vma_, _lma_) \
.vectors _vma_ : _lma_ \
{ FORCE_OUTPUT; KEEP(*(.vectors)) } \
> _region_
+#define SECTION_init(_region_, _vma_, _lma_) \
+ .init _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; KEEP (*(.init)) \
+ } > _region_ =0
+
+#define SECTION_fini(_region_, _vma_, _lma_) \
+ .fini _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; KEEP (*(.fini)) \
+ } > _region_ =0
+
// Code that might be executed out of either RAM or ROM
-#define SECTION_text(_region_, _vma_, _lma_) \
- .text _vma_ : _lma_ \
- { __stext = .; \
- *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \
- > _region_ \
+#define SECTION_text(_region_, _vma_, _lma_) \
+ .text _vma_ : _lma_ \
+ { __stext = .; \
+ *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) } \
+ > _region_ \
__etext = .; PROVIDE (etext = .);
// The .text.ram section is for performance-sensitive code that is
@@ -96,19 +184,14 @@
__ram_text_end = .; PROVIDE(__ram_text_end = .); \
__etext_ram = .; PROVIDE (etext_ram = .);
-#define SECTION_fini(_region_, _vma_, _lma_) \
- .fini _vma_ : _lma_ \
- { FORCE_OUTPUT; *(.fini) } \
- > _region_
-
#define SECTION_rodata1(_region_, _vma_, _lma_) \
- .rodata1 _vma_ : _lma_ \
- { FORCE_OUTPUT; *(.rodata1*) } \
+ .rodata1 _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.rodata1) *(.rodata1*) } \
> _region_
-#define SECTION_rodata(_region_, _vma_, _lma_) \
- .rodata _vma_ : _lma_ \
- { FORCE_OUTPUT; *(.rodata*) } \
+#define SECTION_rodata(_region_, _vma_, _lma_) \
+ .rodata _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.rodata) *(.rodata*) *(.gnu.linkonce.r*) } \
> _region_
#define SECTION_fixup(_region_, _vma_, _lma_) \
@@ -122,33 +205,86 @@
__EXCEPT_END__ = ABSOLUTE(.);} \
> _region_
-#define SECTION_data(_region_, _vma_, _lma_) \
- .data _vma_ : _lma_ \
- { __ram_data_start = ABSOLUTE(.); *(.data*) \
- __GOT1_START__ = ABSOLUTE(.); *(.got1) __GOT1_END__ = ABSOLUTE(.); \
- /* Put .ctors and .dtors next to the .got2 section, so that */ \
- /* the pointers get relocated with -mrelocatable. */ \
- . = ALIGN(8); ___CTOR_LIST__ = ABSOLUTE(.); \
- KEEP(*(SORT(.ctors*))) ___CTOR_END__ = ABSOLUTE(.); \
- ___DTOR_LIST__ = ABSOLUTE(.); \
- KEEP(*(SORT(.dtors*))) ___DTOR_END__ = ABSOLUTE(.); \
- . = ALIGN(8); \
- KEEP(*( SORT (.ecos.table.*))) ; \
- . = ALIGN(4); \
- *( .2ram.*) ; \
- __GOT2_START__ = ABSOLUTE(.); *(.got2) __GOT2_END__ = ABSOLUTE(.); \
- __GOT_START = ABSOLUTE(.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768); \
- _SDA_BASE_ = ABSOLUTE(.); *(.got.plt) *(.got) \
- __GOT_END__ = ABSOLUTE(.); *(.dynamic) \
- /* We want the small data sections together, so single-instruction */ \
- /* offsets can access them all, and initialized data all before */ \
- /* uninitialized, so we can shorten the on-disk segment size. */ \
- __SDATA_START__ = ABSOLUTE(.); *(.sdata) *(.sdata.*) \
- __SDATA2_START__ = ABSOLUTE(.); *(.sdata2*) } \
- > _region_ \
- __rom_data_start = LOADADDR(.data); \
- __ram_data_end = .; PROVIDE(__ram_data_end = .); \
- _edata = .; PROVIDE (edata = .);
+#define SECTION_ctors(_region_, _vma_, _lma_) \
+ .ctors _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; \
+ KEEP (*crtbegin.o(.ctors)) \
+ KEEP (*_ctors.o(.ctors)) \
+ __CTOR_LIST__ = .; \
+ PROVIDE (__CTOR_LIST__ = .); \
+ KEEP (*(.ctors)); \
+ KEEP (*(SORT(.ctors.*))) \
+ __CTOR_END__ = .; \
+ PROVIDE (__CTOR_END__ = .); \
+ } > _region_
+
+#define SECTION_dtors(_region_, _vma_, _lma_) \
+ .dtors _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; \
+ KEEP (*crtbegin.o(.dtors)) \
+ __DTOR_LIST__ = .; \
+ PROVIDE (__DTOR_LIST__ = .); \
+ KEEP (*(SORT(.dtors.*))) \
+ __DTOR_END__ = .; \
+ KEEP (*(.dtors)); \
+ PROVIDE (__DTOR_END__ = .); \
+ } > _region_
+
+#define SECTION_got(_region_, _vma_, _lma_) \
+ .got _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; *(.got.plt) *(.got*) \
+ } > _region_
+
+#define SECTION_dynamic(_region_, _vma_, _lma_) \
+ .dynamic _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; *(.dynamic) \
+ } > _region_
+
+#define SECTION_devtab(_region_, _vma_, _lma_) \
+ .devtab _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; \
+ KEEP(*( SORT (.ecos.table.*))) ; \
+ } > _region_
+
+#define SECTION_data(_region_, _vma_, _lma_) \
+ .data _vma_ : _lma_ \
+ { __ram_data_start = ABSOLUTE(.); \
+ *(.data*) *(.data.*) *(.gnu.linkonce.d*) \
+ *( .2ram.*) \
+ . = ALIGN (8); \
+ SORT(CONSTRUCTORS) \
+ } > _region_ \
+ __rom_data_start = LOADADDR(.data);
+
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+
+#define SECTION_sdata(_region_, _vma_, _lma_) \
+ .sdata _vma_ : _lma_ \
+ { \
+ __SDATA_START__ = ABSOLUTE(.); \
+ FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \
+ } > _region_
+
+#define SECTION_lit8(_region_, _vma_, _lma_) \
+ .lit8 _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; *(.lit8) \
+ } > _region_
+
+#define SECTION_lit4(_region_, _vma_, _lma_) \
+ .lit4 : FOLLOWING(.lit8) \
+ { \
+ FORCE_OUTPUT; *(.lit4) \
+ } > _region_ \
+ __ram_data_end = .; _edata = . ; \
+ PROVIDE (edata = .);
#define SECTION_sbss(_region_, _vma_, _lma_) \
.sbss _vma_ : _lma_ \
@@ -161,9 +297,9 @@
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
- { __bss_start = ABSOLUTE (.); \
- FORCE_OUTPUT; *(.dynbss*) *(.bss*) *(COMMON) \
- __bss_end = ABSOLUTE (.); } \
+ { __bss_start = ABSOLUTE (.); \
+ FORCE_OUTPUT; *(.dynbss*) *(.bss) *(.bss.*) *(COMMON) \
+ __bss_end = ABSOLUTE (.); } \
> _region_
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .);
@@ -175,3 +311,5 @@
#include CYGBLD_HAL_TARGET_H
_hal_vsr_table = CYGHWR_HAL_VSR_TABLE;
_hal_virtual_vector_table = CYGHWR_HAL_VIRTUAL_VECTOR_TABLE;
+
+// EOF openrisc.ld
diff -urN orig/packages/hal/openrisc/arch/current/src/openrisc_stub.c packages/hal/openrisc/arch/current/src/openrisc_stub.c
--- orig/packages/hal/openrisc/arch/current/src/openrisc_stub.c Thu Mar 20 02:53:58 2003
+++ packages/hal/openrisc/arch/current/src/openrisc_stub.c Fri Apr 25 03:26:15 2003
@@ -296,3 +296,4 @@
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+// EOF openrisc_stub.c
diff -urN orig/packages/hal/openrisc/arch/current/src/vectors.S.old packages/hal/openrisc/arch/current/src/vectors.S.old
--- orig/packages/hal/openrisc/arch/current/src/vectors.S.old Fri Mar 28 00:59:29 2003
+++ packages/hal/openrisc/arch/current/src/vectors.S.old Thu Jan 1 01:00:00 1970
@@ -1,826 +0,0 @@
-##==========================================================================
-##
-## Vectors.S
-##
-## OpenRISC exception vectors, interrupt-handling, reset and
-## platform-indepent initialization
-##
-##==========================================================================
-#####ECOSGPLCOPYRIGHTBEGIN####
-## -------------------------------------------
-## This file is part of eCos, the Embedded Configurable Operating System.
-## Copyright (C) 2002 Red Hat, Inc.
-##
-## eCos is free software; you can redistribute it and/or modify it under
-## the terms of the GNU General Public License as published by the Free
-## Software Foundation; either version 2 or (at your option) any later version.
-##
-## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-## WARRANTY; without even the implied warranty of MERCHANTABILITY or
-## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-## for more details.
-##
-## You should have received a copy of the GNU General Public License along
-## with eCos; if not, write to the Free Software Foundation, Inc.,
-## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-##
-## As a special exception, if other files instantiate templates or use macros
-## or inline functions from this file, or you compile this file and link it
-## with other works to produce a work based on this file, this file does not
-## by itself cause the resulting work to be covered by the GNU General Public
-## License. However the source code for this file must still be made available
-## in accordance with section (3) of the GNU General Public License.
-##
-## This exception does not invalidate any other reasons why a work based on
-## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
-## -------------------------------------------
-#####ECOSGPLCOPYRIGHTEND####
-##==========================================================================
-#######DESCRIPTIONBEGIN####
-##
-## Author(s): sfurman
-## Contributors:
-## Date: 2003-01-20
-## Purpose: OpenRISC interrupts, exception vectors and reset
-## Description: This file defines the code placed into the exception
-## vectors. It also contains the first level default VSRs
-## that save and restore state for both exceptions and
-## interrupts.
-##
-######DESCRIPTIONEND####
-##
-##==========================================================================
-
-#include <pkgconf/hal.h>
-
-#ifdef CYGPKG_KERNEL
-#include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT
-#endif
-
-#include <cyg/hal/arch.inc>
-#include <cyg/hal/hal_intr.h>
-#include <cyg/hal/hal_cache.h>
-
-#===========================================================================
-
-
- .extern _hal_vsr_table
-
- .extern _cyg_hal_invoke_constructors
- .extern _cyg_instrument
- .extern _cyg_start
- .extern _hal_IRQ_init
- .extern _hal_platform_init
- .extern _initialize_stub
-
- .extern __bss_start
- .extern __bss_end
- .extern __sbss_start
- .extern __sbss_end
-
-# Include variant macros after MSR definition.
-#include <cyg/hal/arch.inc>
-#include <cyg/hal/openrisc.inc>
-
-
-#===========================================================================
-# Start by defining the exceptions vectors that must be placed in low
-# memory, starting at location 0x100.
-
- .section ".vectors","ax"
-
-#---------------------------------------------------------------------------
-# Macros for generating an exception vector service routine
-
-# Reset vector macro
-
- .macro reset_vector name org
- .p2align 8
- .globl __exception_\name
-__exception_\name:
- load32i r3,_start
- l.jr r3
- l.nop # delay slot
- .endm
-
-# Generic vector macro
-
- .macro exception_vector name org
- .p2align 8
- .globl __exception_\name
-__exception_\name:
- l.addi sp,sp,-SIZEOF_OR1KREGS # space for registers
-
- # Store General Purpose Registers (GPRs).
-
- l.sw 3 * OR1K_GPRSIZE(sp), r3
- l.sw 4 * OR1K_GPRSIZE(sp), r4
- l.sw 5 * OR1K_GPRSIZE(sp), r5
- l.sw 6 * OR1K_GPRSIZE(sp), r6
- l.sw 7 * OR1K_GPRSIZE(sp), r7
- l.sw 8 * OR1K_GPRSIZE(sp), r8
- l.sw 9 * OR1K_GPRSIZE(sp), r9
- l.sw 11 * OR1K_GPRSIZE(sp), r11
- l.sw 13 * OR1K_GPRSIZE(sp), r13
- l.sw 15 * OR1K_GPRSIZE(sp), r15
- l.sw 17 * OR1K_GPRSIZE(sp), r17
- l.sw 19 * OR1K_GPRSIZE(sp), r19
- l.sw 21 * OR1K_GPRSIZE(sp), r21
- l.sw 23 * OR1K_GPRSIZE(sp), r23
- l.sw 25 * OR1K_GPRSIZE(sp), r25
- l.sw 27 * OR1K_GPRSIZE(sp), r27
- l.sw 29 * OR1K_GPRSIZE(sp), r29
- l.sw 31 * OR1K_GPRSIZE(sp), r31
-
-
-#ifndef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
-
- # R0 is not typically stored because it is always zero-valued,
- # but we store it here for consistency when examining registers
- # in the debugger.
- l.sw 0 * OR1K_GPRSIZE(sp), r0
-
- # Callee-saved regs don't need to be preserved across a call into
- # an ISR, but we can do so to make debugging easier.
- l.sw 2 * OR1K_GPRSIZE(sp), r2
- l.sw 10 * OR1K_GPRSIZE(sp), r10
- l.sw 12 * OR1K_GPRSIZE(sp), r12
- l.sw 14 * OR1K_GPRSIZE(sp), r14
- l.sw 16 * OR1K_GPRSIZE(sp), r16
- l.sw 18 * OR1K_GPRSIZE(sp), r18
- l.sw 20 * OR1K_GPRSIZE(sp), r20
- l.sw 22 * OR1K_GPRSIZE(sp), r22
- l.sw 24 * OR1K_GPRSIZE(sp), r24
- l.sw 26 * OR1K_GPRSIZE(sp), r26
- l.sw 28 * OR1K_GPRSIZE(sp), r28
- l.sw 30 * OR1K_GPRSIZE(sp), r30
-
- # save MAC LO and HI regs
- l.mfspr r5,r0,SPR_MACLO
- l.sw OR1KREG_MACLO(sp),r5
- l.mfspr r5,r0,SPR_MACHI
- l.sw OR1KREG_MACHI(sp),r5
-#endif
-
- # Save SP of interruptee in reg dump
- l.addi r5,sp,SIZEOF_OR1KREGS
- l.sw 1 * OR1K_GPRSIZE(sp),r5
-
- # ...and the PC
- l.mfspr r5,r0,SPR_EPCR_BASE
- l.sw OR1KREG_PC(sp),r5
-
- # ... and the Supervisor Register
- l.mfspr r5,r0,SPR_ESR_BASE
- l.sw OR1KREG_SR(sp),r5
-
- # ... and the exception's effective address, if there is one.
- # FIXME - don't need to do this for some exceptions
- l.mfspr r5,r0,SPR_EEAR_BASE
- l.sw OR1KREG_EEAR(sp),r5
-
- # Second arg to VSR is exception number
- # First vector is located at 0x100, second at 0x200, etc.
- # Shift right to get vector number for address lookup.
- l.ori r4,r0,(\org>>8)
- l.sw OR1KREG_VECTOR(sp),r4
-
- # Lookup address of VSR in table and jump to it
- # Arg 0: Pointer to HAL_SavedRegisters struct
- # Arg 1: Vector #
- load32i r5,_hal_vsr_table+(\org>>6)
- l.lwz r5,0(r5)
- l.jr r5 # To the VSR, Batman
-
- # First arg to VSR is SP
- l.or r3,r0,sp # Delay slot
-
- .endm
-
-#---------------------------------------------------------------------------
-# Define the exception vectors.
-
-rom_vectors:
- # These are the architecture-defined vectors that
- # are always present.
-
- reset_vector reset 0x100
- exception_vector bus_error 0x200
- exception_vector data_page_fault 0x300
- exception_vector instruction_page_fault 0x400
- exception_vector tick_timer 0x500
- exception_vector unaligned_access 0x600
- exception_vector illegal_instruction 0x700
- exception_vector external_interrupt 0x800
- exception_vector dtlb_miss 0x900
- exception_vector itlb_miss 0xa00
- exception_vector range 0xb00
- exception_vector syscall 0xc00
- exception_vector reserved 0xd00
- exception_vector trap 0xe00
-
-rom_vectors_end:
-
-
-#if defined(CYG_HAL_STARTUP_ROM) || \
- ( defined(CYG_HAL_STARTUP_RAM) && \
- !defined(CYGSEM_HAL_USE_ROM_MONITOR))
-
- .macro hal_vsr_table_init
-
- # Next initialize the VSR table. This happens whether the
- # vectors were copied to RAM or not.
-
- # First fill with exception handlers
- load32i r3,_cyg_hal_default_exception_vsr
- load32i r4,_hal_vsr_table+4 # First entry in table is unused
- l.ori r5,r0,CYGNUM_HAL_VSR_COUNT
-1: l.sw 0(r4),r3
- l.addi r5,r5,-1
- l.sfgtsi r5,0
- l.bf 1b
- l.addi r4,r4,4 # delay slot
-
- # Then fill in the interrupt handlers
- load32i r4,_hal_vsr_table
- load32i r3,_cyg_hal_default_interrupt_vsr
- l.sw CYGNUM_HAL_VECTOR_INTERRUPT*4(r4),r3
- l.sw CYGNUM_HAL_VECTOR_TICK_TIMER*4(r4),r3
- .endm
-
-#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
-
- # Initialize the VSR table entries
- # We only take control of the interrupt vectors,
- # the rest are left to the ROM for now...
-
- .macro hal_vsr_table_init
- load32i r4,_hal_vsr_table
- load32i r3,_cyg_hal_default_interrupt_vsr
- l.sw CYGNUM_HAL_VECTOR_INTERRUPT*4(r4),r3
- l.sw CYGNUM_HAL_VECTOR_TICK_TIMER*4(r4),r3
- .endm
-
-
-#else
-
-#error "Need to define hal_vsr_table_init"
-
-#endif
-
-# I-Cache initialization macro
- .macro hal_icache_init
- /* Disable I-Cache */
- l.mfspr r13,r0,SPR_SR
- l.addi r11,r0,-1
- l.xori r11,r11,SPR_SR_ICE
- l.and r11,r13,r11
- l.mtspr r0,r11,SPR_SR
-
- /* Invalidate I-Cache */
- l.addi r13,r0,0
- l.addi r11,r0,HAL_ICACHE_SIZE
-1:
- l.mtspr r0,r13,SPR_ICBIR
- l.sfne r13,r11
- l.bf 1b
- l.addi r13,r13,HAL_ICACHE_LINE_SIZE
-
- /* Enable I-Cache */
- l.mfspr r13,r0,SPR_SR
- l.ori r13,r13,SPR_SR_ICE
- l.mtspr r0,r13,SPR_SR
-
- /* Flush instructions out of instruction buffer */
- l.nop
- l.nop
- l.nop
- l.nop
- l.nop
- .endm
-
-# D-Cache initialization macro
- .macro hal_dcache_init
-
- /* Flush DC */
- l.addi r10,r0,0
- l.addi r11,r0,HAL_DCACHE_SIZE
-1:
- l.mtspr r0,r10,SPR_DCBIR
- l.sfne r10,r11
- l.bf 1b
- l.addi r10,r10,HAL_DCACHE_LINE_SIZE
-
- /* Enable DC */
- l.mfspr r10,r0,SPR_SR
- l.ori r10,r10,SPR_SR_DCE
- l.mtspr r0,r10,SPR_SR
- .endm
-
-#===========================================================================
-# Startup code: We jump here from the reset vector to set up the world.
-
- .text
-
-FUNC_START(start)
-
- # Initialize Supervision Register:
- # Supervisor mode on, all interrupts off, caches off
- #
- # (If we've entered here from a hardware reset, then the SR is already
- # set to this value, but we may have jumped here as part of a soft
- # system reset.)
- l.ori r3,r0,SPR_SR_SM
- l.mtspr r0,r3,SPR_SR
-
- # Run platform-specific hardware initialization code.
- # This may include memory controller initialization.
- # Hence, it is not safe to access RAM until after this point.
- hal_hardware_init
-
-#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
- # Enable I-Cache
- hal_icache_init
-#endif
-
-#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
- # Enable D-Cache
- hal_dcache_init
-#endif
-
- .globl _hal_hardware_init_done
-_hal_hardware_init_done:
-
- # set up stack
- load32i sp,__interrupt_stack
-
- # Make a dummy frame on the stack, so that stack backtraces are sane
- # for debugging. On return from that function, the restore_state()
- # function is called to resume the interrupted thread.
- l.addi sp,sp,-8
- l.sw 4(sp),r0 # Dummy saved FP
- l.sw 0(sp),r0 # Dummy saved LR
-
- # Set up exception handlers and VSR table, taking care not to
- # step on any ROM monitor VSRs.
- hal_vsr_table_init
-
-#if defined(CYG_HAL_STARTUP_ROM)
- # Copy exception/interrupt vectors from ROM to address 0x100
- load32i r4,0x100
- load32i r3,rom_vectors
- load32i r5,rom_vectors_end
-1: l.sfeq r3,r5
- l.bf 2f
- l.lwz r6,0(r3)
- l.sw 0(r4),r6
- l.addi r3,r3,4
- l.j 1b
- l.addi r4,r4,4 # delay slot
-2:
-
- # Copy .data section into RAM
- load32i r3,__rom_data_start
- load32i r4,__ram_data_start
- load32i r5,__ram_data_end
-1: l.sfeq r4,r5
- l.bf 2f
- l.lwz r6,0(r3)
- l.sw 0(r4),r6
- l.addi r3,r3,4
- l.j 1b
- l.addi r4,r4,4 # delay slot
-2:
-#endif
-
- # clear BSS
- load32i r4,__bss_start
- load32i r5,__bss_end
-1: l.sfeq r4,r5
- l.bf 2f
- l.nop
- l.sw 0(r4),r0
- l.j 1b
- l.addi r4,r4,4
-2:
-
- # Note: no SBSS section to clear with OpenRISC target
-
- # Platform-specific initialization
- l.jal _hal_platform_init
- l.nop # delay slot
-
- # call c++ constructors
- l.jal _cyg_hal_invoke_constructors
- l.nop # delay slot
-
-#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- l.jal _initialize_stub
- l.nop # delay slot
-#endif
-
-#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
- || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
- .extern _hal_ctrlc_isr_init
- l.jal _hal_ctrlc_isr_init
- l.nop # delay slot
-#endif
-
- l.jal _cyg_start # call cyg_start()
- l.nop # delay slot
-9:
- l.j 9b # if we return, loop
-
-FUNC_END(start)
-
-#---------------------------------------------------------------------------
-# This code handles the common part of all exception handlers.
-# On entry, the machine state is already saved on the stack.
-#
-# R3 = pointer to HAL_SavedRegisters struct containing saved machine state
-# R4 = Vector number
-#
-# It calls a C routine to do any work, which may result in
-# thread switches and changes to the saved state. When we return
-# here, the saved state is restored and execution is continued.
-
- .text
-
-FUNC_START(cyg_hal_default_exception_vsr)
-
- .extern _cyg_hal_exception_handler
-
- # Call C code
-
- # When cyg_hal_exception_handler() returns, it will jump
- # directly to restore_state(), which will resume execution
- # at the location of the exception.
- l.movhi r9, hi(restore_state)
- l.j _cyg_hal_exception_handler
- l.ori r9,r9,lo(restore_state) #Delay slot
-
- # Control never reaches this point,
-
-FUNC_END(cyg_hal_default_exception_vsr)
-
-#---------------------------------------------------------------------------
-# This code handles all interrupts and dispatches to a C ISR function
-# On entry, the machine state is already saved on the stack.
-#
-# R3 = pointer to HAL_SavedRegisters struct containing saved machine state
-# R4 = Vector number
-#
-# After we return here, the saved state is restored and execution is continued.
-
-
-FUNC_START(cyg_hal_default_interrupt_vsr)
-
- # Stash away pointer to saved regs for later
- l.or r31,r3,r3
-
- # Set scheduler lock to prevent thread rescheduling while the ISR runs
-#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
- .extern _cyg_scheduler_sched_lock
- load32i r5, _cyg_scheduler_sched_lock
- l.lwz r6,0(r5)
- l.addi r6,r6,1
- l.sw 0(r5),r6
-#endif
-
-#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- # Interrupts execute on their own dedicated stack.
- # If we're on a thread stack, switch to the interrupt stack.
- # If we're called inside a nested interrupt, do nothing.
- l.or r6,sp,sp # Stash SP for later
- load32i r7,__interrupt_stack # stack top (highest addr + 1)
- load32i r8,__interrupt_stack_base # stack base (lowest addr)
- l.sfltu sp,r8 # if (sp < __interrupt_stack_base)
- l.bf 1f # switch to interrupt stack
- l.sfltu sp,r7 # if (sp < __interrupt_stack_top)
- l.bf 2f # already on interrupt stack
- l.nop # delay slot
-1: l.or sp,r7,r7 # Switch to interrupt stack
-2: l.addi sp,sp,-8 # Make space to save old SP...
- l.sw 0(sp),r6 # ...and save it on the stack
-#endif
-
- # Call C code
-
-#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
- # Log the interrupt if kernel tracing is enabled
- l.ori r3,r0,0x0301 # arg1 = type = INTR,RAISE
- # arg2 = vector number
- l.ori r5,r0,r0 # arg3 = 0
- l.jal _cyg_instrument # call instrument function
-
-#endif
-
-#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
- || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
- # If we are supporting Ctrl-C interrupts from GDB, we must squirrel
- # away a pointer to the save interrupt state here so that we can
- # plant a breakpoint at some later time.
-
- .extern _hal_saved_interrupt_state
- load32i r8,_hal_saved_interrupt_state
- l.sw 0(r8),r31
-
-#endif
-
- # In the event of multiple pending interrupts, determine which
- # one will be serviced first. By software convention, the lowest
- # numbered external interrupt gets priority.
- #
- # The (internal) tick timer interrupt is serviced only if no
- # external interrupts are pending.
-
- # Read the PIC interrupt controller's status register
- l.mfspr r9,r0,SPR_PICSR
-
- # Any pending external interrupts ?
- l.sfnei r9,0
- l.bf check_for_external_interrupts
-
- # Theoretically, the only way we could get here is if the tick timer
- # interrupt fired, but we check to be sure that's what happened.
- l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
- l.bf 3f
- l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot
-
-#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
- l.jal _hal_spurious_IRQ
- l.nop
-#endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
- l.j ignore_spurious_interrupt
-
- # Identify the lowest numbered interrupt bit in the PIC's PSR,
- # numbering the MSB as 31 and the LSB as 0
-check_for_external_interrupts:
- l.ori r3,r0,0
-2: l.andi r11,r9,1 # Test low bit
- l.sfnei r11,0
- l.bf 3f
- l.srli r9,r9,1 # Shift right 1 bit
- l.j 2b
- l.addi r3,r3,1 # Delay slot
-3:
-
- # At this point, r3 contains the ISR number, from 0-32
- # which will be used to index the table of ISRs
- l.slli r15,r3,2
- load32i r9, _hal_interrupt_handlers # get interrupt handler table
- l.add r9,r9,r15
- l.lwz r11,0(r9) # load ISR pointer
- load32i r9, _hal_interrupt_data # get interrupt data table
- l.add r9,r9,r15
- l.lwz r4,0(r9) # load data arg to ISR
-
- # Call ISR
- # arg0 = ISR #
- # arg1 = data arg associated with interrupt
- l.jalr r11
- l.nop
-
-ignore_spurious_interrupt:
-
-#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
-
- # If we are returning from the last nested interrupt, move back
- # to the thread stack. interrupt_end() must be called on the
- # thread stack since it potentially causes a context switch.
- # Since we have arranged for the top of stack location to
- # contain the sp we need to go back to here, just pop it off
- # and put it in SP.
-
- l.lwz sp,0(sp)
-#endif
-
-#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
-
- # We only need to call _interrupt_end() when there is a kernel
- # present to do any tidying up.
-
- # on return r11 bit 1 will indicate whether a DSR is
- # to be posted. Pass this together with a pointer to
- # the interrupt object we have just used to the
- # interrupt tidy up routine.
- l.or r3,r11,r11
-
- # Get pointer to HAL_SavedRegisters struct, stashed earlier
- l.or r5,r31,r31
-
- # Get opaque object associated w/ interrupt vector
- load32i r9, _hal_interrupt_objects # get interrupt data table
- l.add r9,r9,r15
- l.lwz r4,0(r9)
-
- # Call interrupt_end() to execute any pending DSRs
- # Arg 0 = return value from ISR
- # Arg 1 = object associated with interrupt
- # Arg 2 = HAL_SavedRegisters struct
-
- .extern _interrupt_end
- l.jal _interrupt_end # call into C to finish off
- l.nop
-#endif
-
- # Fall through to restore_state...
-
-# Return from either an interrupt or an exception
-#
-# On entry:
-# SP = pointer to (HAL_SavedRegisters struct)
-#
-restore_state:
-
- # Restore General Purpose Registers (GPRs).
- # R0 is not restored because it is always zero-valued.
- # R1, R3, and R4 are used as temps, so they are restored a little later
- l.lwz r5, 5 * OR1K_GPRSIZE(sp)
- l.lwz r6, 6 * OR1K_GPRSIZE(sp)
- l.lwz r7, 7 * OR1K_GPRSIZE(sp)
- l.lwz r8, 8 * OR1K_GPRSIZE(sp)
- l.lwz r9, 9 * OR1K_GPRSIZE(sp)
- l.lwz r11, 11 * OR1K_GPRSIZE(sp)
- l.lwz r13, 13 * OR1K_GPRSIZE(sp)
- l.lwz r15, 15 * OR1K_GPRSIZE(sp)
- l.lwz r17, 17 * OR1K_GPRSIZE(sp)
- l.lwz r19, 19 * OR1K_GPRSIZE(sp)
- l.lwz r21, 21 * OR1K_GPRSIZE(sp)
- l.lwz r23, 23 * OR1K_GPRSIZE(sp)
- l.lwz r25, 25 * OR1K_GPRSIZE(sp)
- l.lwz r27, 27 * OR1K_GPRSIZE(sp)
- l.lwz r29, 29 * OR1K_GPRSIZE(sp)
- l.lwz r31, 31 * OR1K_GPRSIZE(sp)
-
-#ifndef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
- # Callee-saved regs don't need to be preserved across a call into
- # an ISR, but we can do so to make debugging easier.
-
- l.lwz r2, 2 * OR1K_GPRSIZE(sp)
- l.lwz r10, 10 * OR1K_GPRSIZE(sp)
- l.lwz r12, 12 * OR1K_GPRSIZE(sp)
- l.lwz r14, 14 * OR1K_GPRSIZE(sp)
- l.lwz r16, 16 * OR1K_GPRSIZE(sp)
- l.lwz r18, 18 * OR1K_GPRSIZE(sp)
- l.lwz r20, 20 * OR1K_GPRSIZE(sp)
- l.lwz r22, 22 * OR1K_GPRSIZE(sp)
- l.lwz r24, 24 * OR1K_GPRSIZE(sp)
- l.lwz r26, 26 * OR1K_GPRSIZE(sp)
- l.lwz r28, 28 * OR1K_GPRSIZE(sp)
- l.lwz r30, 30 * OR1K_GPRSIZE(sp)
-
- # Restore MAC LO and HI regs
- l.lwz r4, OR1KREG_MACLO(sp)
- l.mtspr r0,r4,SPR_MACLO
- l.lwz r4, OR1KREG_MACHI(sp)
- l.mtspr r0,r4,SPR_MACHI
-#endif
-
- # Must disable interrupts, since they could clobber ESR and EPC regs
- l.mfspr r3, r0, SPR_SR
- load32i r4,~(SPR_SR_TEE|SPR_SR_IEE)
- l.and r3, r4, r3
- l.mtspr r0, r3, SPR_SR
-
- # At this point we've restored all the pre-interrupt GPRs except for the SP.
- # Restore pre-interrupt SR, SP, and PC
- l.lwz r4, OR1KREG_SR(sp)
- l.mtspr r0, r4, SPR_ESR_BASE
-
- l.lwz r4, OR1KREG_PC(sp)
- l.mtspr r0, r4, SPR_EPCR_BASE
-
- l.lwz r4, 4 * OR1K_GPRSIZE(sp)
- l.lwz r3, 3 * OR1K_GPRSIZE(sp)
- l.lwz sp, 1 * OR1K_GPRSIZE(sp)
-
- # All done, restore CPU state and continue
- l.rfe
- l.nop # Delay slot
-
-
-##-----------------------------------------------------------------------------
-## Execute pending DSRs on the interrupt stack with interrupts enabled.
-## Note: this can only be called from code running on a thread stack
-
-#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
- .extern _cyg_interrupt_call_pending_DSRs
-
-FUNC_START(hal_interrupt_stack_call_pending_DSRs)
- # Switch to interrupt stack
- l.or r3, sp, sp # Stash entry SP
- load32i sp, __interrupt_stack
- l.addi sp, sp, -16
- l.sw 0(sp), r3 # Save entry SP
- l.mfspr r4,r0,SPR_SR
- l.sw 4(sp), r4 # Save interrupt state
- l.ori r4, r4, SPR_SR_IEE|SPR_SR_TEE
- l.sw 8(sp),lr
-
- l.jal _cyg_interrupt_call_pending_DSRs
- # Enable interrupts before calling DSRs
- l.mtspr r0, r4, SPR_SR # Delay slot
-
- l.lwz r4, 4(sp)
- l.lwz lr, 8(sp)
- l.lwz sp, 0(sp)
-
- # Merge original interrupt state with (possibly altered) SR reg
- l.andi r4, r4, SPR_SR_IEE|SPR_SR_TEE
- l.mfspr r5, r0, SPR_SR
- load32i r6, ~(SPR_SR_IEE|SPR_SR_TEE)
- l.and r5, r5, r6
- l.or r4, r4, r5
-
- l.jr r9
- l.mtspr r0, r4, SPR_SR # Delay slot
-
-FUNC_END(hal_interrupt_stack_call_pending_DSRs)
-#endif
-
-##-----------------------------------------------------------------------------
-## Switch to a new stack.
-## This is used in RedBoot to allow code to execute in a different
-## stack context.
-
-FUNC_START(hal_program_new_stack)
- # Arguments are:
- # r3 = function to call
- # r4 = stack pointer to use
-
- # Dummy prologue, so that debugger is fooled into thinking there
- # is a stack frame. The debugger will use the offsets in the prologue
- # below to read the saved register values out of the *new* stack.
- l.addi sp,sp,-8
- l.sw 0(sp),fp
- l.addi fp,sp,8
- l.sw 4(sp),lr
-
- l.or r5,sp,sp # Remember original SP
- l.addi r6,fp,-8 # Remember original FP
- l.or sp,r4,r4 # Switch to new stack
-
- # "Real prologue" - Offsets here must match dummy prologue above
- l.addi sp,sp,-16
- l.sw 0(sp),r6 # So debugger can know caller's FP
- l.sw 4(sp),lr # So debugger can know caller's PC
- l.sw 8(sp),r5 # Save old SP on stack
-
- # Call function
- l.jalr r3
- l.nop
-
- l.lwz sp, 8(sp) # Restore original SP
- l.lwz lr, 4(sp)
- l.jr lr # Return to caller
- l.addi sp,sp, 8 # Delay slot
-
-FUNC_END(hal_program_new_stack)
-
-#---------------------------------------------------------------------------
-## Temporary interrupt stack
-
- .section ".bss"
-
- .balign 16
- .global _cyg_interrupt_stack_base
-_cyg_interrupt_stack_base:
-__interrupt_stack_base:
- .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
- .byte 0
- .endr
- .balign 16
- .global _cyg_interrupt_stack
-_cyg_interrupt_stack:
-__interrupt_stack:
-
- .long 0,0,0,0,0,0,0,0
-
-#--------------------------------------
- .data
- .extern _hal_default_isr
-
- .globl _hal_interrupt_handlers
-_hal_interrupt_handlers:
- .rept CYGNUM_HAL_ISR_COUNT
- .long _hal_default_isr
- .endr
-
- .globl _hal_interrupt_data
-_hal_interrupt_data:
- .rept CYGNUM_HAL_ISR_COUNT
- .long 0
- .endr
-
- .globl _hal_interrupt_objects
-_hal_interrupt_objects:
- .rept CYGNUM_HAL_ISR_COUNT
- .long 0
- .endr
-
-#---------------------------------------------------------------------------
-# end of vectors.S
diff -urN orig/packages/hal/openrisc/orp/current/ChangeLog packages/hal/openrisc/orp/current/ChangeLog
--- orig/packages/hal/openrisc/orp/current/ChangeLog Thu Mar 6 20:45:04 2003
+++ packages/hal/openrisc/orp/current/ChangeLog Fri Apr 25 04:38:11 2003
@@ -1,3 +1,12 @@
+2003-04-25 Jonathan Larmour <jifl at eCosCentric dot com>
+
+ * cdl/hal_openrisc_orp.cdl: CYGSEM_HAL_USE_ROM_MONITOR need only be a
+ bool.
+ CYGSEM_HAL_ROM_MONITOR should be default off (should be used later...)
+ * include/pkgconf/mlt_openrisc_orp_ram.ldi: Add sections as per
+ changes to arch HAL's openrisc.ld.
+ * include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto.
+
2003-03-06 Scott Furman <sfurman at rosum dot com>
Initial port of eCos to OpenRISC Reference Platform (ORP)
diff -urN orig/packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl
--- orig/packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl Wed Mar 5 01:33:02 2003
+++ packages/hal/openrisc/orp/current/cdl/hal_openrisc_orp.cdl Fri Apr 25 04:14:22 2003
@@ -266,30 +266,20 @@
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
- flavor booldata
- legal_values { "Generic" "CygMon" "GDB_stubs" }
- default_value { CYG_HAL_STARTUP == "RAM" ? "CygMon" : 0 }
+ flavor bool
+ default_value { CYG_HAL_STARTUP == "RAM" ? 1 : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
- Support can be enabled for three different varieties of ROM monitor.
- This support changes various eCos semantics such as the encoding
- of diagnostic output, or the overriding of hardware interrupt
- vectors.
- Firstly there is \"Generic\" support which prevents the HAL
- from overriding the hardware vectors that it does not use, to
- instead allow an installed ROM monitor to handle them. This is
- the most basic support which is likely to be common to most
- implementations of ROM monitor.
- \"CygMon\" provides support for the Cygnus ROM Monitor.
- And finally, \"GDB_stubs\" provides support when GDB stubs are
- included in the ROM monitor or boot ROM."
+ Allow coexistence with ROM monitor (CygMon or GDB stubs) by
+ only initializing interrupt vectors on startup, thus leaving
+ exception handling to the ROM monitor."
}
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
- default_value 1
+ default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
@@ -333,3 +323,5 @@
puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE 0xF00"
}
}
+
+# EOF hal_openrisc_orp.cdl
diff -urN orig/packages/hal/openrisc/orp/current/include/mc.h packages/hal/openrisc/orp/current/include/mc.h
--- orig/packages/hal/openrisc/orp/current/include/mc.h Wed Mar 5 01:41:32 2003
+++ packages/hal/openrisc/orp/current/include/mc.h Fri Apr 25 04:23:43 2003
@@ -141,3 +141,5 @@
#define MC_TMS_SYNC_TRDV_WIDTH 8
#endif
+
+// EOF mc.h
diff -urN orig/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi
--- orig/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi Wed Mar 5 01:28:07 2003
+++ packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi Fri Apr 25 03:12:06 2003
@@ -12,13 +12,26 @@
{
SECTIONS_BEGIN
SECTION_vectors (ram, 0x00000100, LMA_EQ_VMA)
+ SECTION_ROMISC (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_init (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (ram, 0x00008000, LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
- SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_ctors (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_dtors (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_devtab (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_dynamic (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_sdata (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
diff -urN orig/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi
--- orig/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi Sat Apr 12 22:12:22 2003
+++ packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi Fri Apr 25 03:08:52 2003
@@ -12,13 +12,26 @@
{
SECTIONS_BEGIN
SECTION_vectors (rom, 0xF0000100, LMA_EQ_VMA)
+ SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA)
+ SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
- SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table))
+ SECTION_eh_frame (ram, ALIGN (0x8), FOLLOWING (.data))
+ SECTION_ctors (ram, ALIGN (0x8), FOLLOWING (.eh_frame))
+ SECTION_dtors (ram, ALIGN (0x8), FOLLOWING (.ctors))
+ SECTION_devtab (ram, ALIGN (0x8), FOLLOWING (.dtors))
+ SECTION_got (ram, ALIGN (0x8), FOLLOWING (.devtab))
+ SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got))
+ SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic))
+ SECTION_lit8 (ram, ALIGN (0x8), FOLLOWING (.sdata))
+ SECTION_lit4 (ram, ALIGN (0x8), FOLLOWING (.lit8))
+ SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
diff -urN orig/packages/hal/openrisc/orp/current/include/platform.inc packages/hal/openrisc/orp/current/include/platform.inc
--- orig/packages/hal/openrisc/orp/current/include/platform.inc Sat Apr 12 22:50:31 2003
+++ packages/hal/openrisc/orp/current/include/platform.inc Fri Apr 25 04:24:45 2003
@@ -114,3 +114,5 @@
#endif /* ifndef _PLATFORM_INC_ */
#undef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM
+
+// EOF platform.inc
diff -urN orig/packages/hal/openrisc/orp/current/src/hal_diag.c packages/hal/openrisc/orp/current/src/hal_diag.c
--- orig/packages/hal/openrisc/orp/current/src/hal_diag.c Thu Mar 6 20:15:29 2003
+++ packages/hal/openrisc/orp/current/src/hal_diag.c Fri Apr 25 04:27:43 2003
@@ -590,5 +590,4 @@
}
//-----------------------------------------------------------------------------
-// end of ser16c550c.c
-
+// end of hal_diag.c