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xscale icache disable
- From: jani at iv dot ro
- To: ecos-patches at sources dot redhat dot com
- Date: Wed, 7 May 2003 13:32:18 +0300
- Subject: xscale icache disable
Hi
according to the PXA docs the icache disable operation needs a CPWAIT at
the end. Think might be the case for all XScales not just those
in PXA but I have not looked in the docs. If not the PXA should have its
own macro.
Anyway with the current code (no CPWAIT) a "cache off" in redboot resets
the board. This patch solves that one.I also took out the invalidate op
from the disable.
Mark, Gary can you comment on this one?
Thanks
Jani
Index: hal/arm/xscale/cores//current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/cores/current/ChangeLog,v
retrieving revision 1.4
diff -u -r1.4 ChangeLog
--- hal/arm/xscale/cores//current/ChangeLog 4 Feb 2003 22:27:56 -0000 1.4
+++ hal/arm/xscale/cores//current/ChangeLog 7 May 2003 10:08:57 -0000
@@ -1,3 +1,8 @@
+2003-05-07 Jani Monoses <jani@iv.ro>
+
+ * include/hal_cache.h: CPWAIT operation added after disabling icache
+ as required by the specification.
+
2003-02-04 Mark Salter <msalter@redhat.com>
* cdl/hal_arm_xscale_core.cdl (CYGSEM_HAL_ARM_XSCALE_BTB): New option.
Index: hal/arm/xscale/cores//current/include/hal_cache.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/cores/current/include/hal_cache.h,v
retrieving revision 1.3
diff -u -r1.3 hal_cache.h
--- hal/arm/xscale/cores//current/include/hal_cache.h 4 Feb 2003 22:27:56 -0000 1.3
+++ hal/arm/xscale/cores//current/include/hal_cache.h 7 May 2003 10:08:59 -0000
@@ -100,7 +100,10 @@
"mrc p15,0,r1,c1,c0,0;" \
"bic r1,r1,#0x1000;" /* disable Icache */ \
"mcr p15,0,r1,c1,c0,0;" \
- "mcr p15,0,r1,c7,c5,0;" /* invalidate instruction cache */ \
+ /* cpuwait */ \
+ "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
+ "mov r1,r1;" \
+ "sub pc,pc,#4;" \
"nop;" /* next few instructions may be via cache */ \
"nop;" \
"nop;" \