This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
AT91 - hal_delay_us fixed
- From: Nick Garnett <nickg at ecoscentric dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: 15 May 2003 19:11:25 +0100
- Subject: AT91 - hal_delay_us fixed
Index: var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v
retrieving revision 1.1
diff -u -5 -r1.1 ChangeLog
--- var/current/ChangeLog 13 May 2003 18:27:59 -0000 1.1
+++ var/current/ChangeLog 15 May 2003 17:55:28 -0000
@@ -1,5 +1,12 @@
+2003-05-15 Nick Garnett <nickg@balti.calivar.com>
+
+ * src/at91_misc.c (hal_delay_us): Added calculation to better
+ approximate the number of timer ticks for a given number of
+ microseconds. This code also now adjust to the actual CPU clock
+ speed on different platforms.
+
2003-05-12 Nick Garnett <nickg@balti.calivar.com>
* src/at91_misc.c: Change definition of hal_IRQ_handler() to be
variant-indepenendent, and to use HAL_LSBIT_INDEX() rather than an
explicit scan of the ipr bits. Tidied up file a little to make
Index: var/current/src/at91_misc.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/at91_misc.c,v
retrieving revision 1.1
diff -u -5 -r1.1 at91_misc.c
--- var/current/src/at91_misc.c 13 May 2003 18:27:59 -0000 1.1
+++ var/current/src/at91_misc.c 15 May 2003 17:55:28 -0000
@@ -122,24 +122,30 @@
}
// -------------------------------------------------------------------------
//
// Delay for some number of micro-seconds
-// Use timer #2 in 1MHz mode
+// Use timer #2 in MCLOCK/32 mode.
//
void hal_delay_us(cyg_int32 usecs)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2;
cyg_uint32 stat;
+ cyg_uint64 ticks;
+ // Calculate how many timer ticks the required number of
+ // microseconds equate to. We do this calculation in 64 bit
+ // arithmetic to avoid overflow.
+ ticks = (((cyg_uint64)usecs) * ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL;
+
// Disable counter
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
// Set registers
HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz
HAL_WRITE_UINT32(timer+AT91_TC_RA, 0);
- HAL_WRITE_UINT32(timer+AT91_TC_RC, usecs);
+ HAL_WRITE_UINT32(timer+AT91_TC_RC, ticks);
// Start timer
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Wait for the compare
--
Nick Garnett eCos Kernel Architect
http://www.ecoscentric.com/ The eCos and RedBoot experts