This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
OpenRISC arch/platform fixes
- From: Scott Furman <sfurman at rosum dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Tue, 17 Jun 2003 20:40:09 -0700
- Subject: OpenRISC arch/platform fixes
A long time ago, jifl graciously reviewed the OpenRISC port of eCos and
made a number of suggestions and improvements. It's been on my plate
since then to respond. Some of his changes to the architecture
linker script broke compilation (as he warned they might) and the
attached patches fix that. There are other, minor, changes as well in
the attached patch. FYI, although there is minor rearrangement of
source code for better platform/arch separation, there is no new code
whatsoever in this patch.
Here's a summary of the changes, culled from the ChangeLog's:
* include/pkgconf/mlt_openrisc_orp_ram.ldi: Repair memory layout
to accommodate introduction of new sections by jifl.
* include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto.
* src/openrisc.ld: Removed libsupc++ requirement, as it does not
yet compile for OpenRISC. Added underscore prefixes to symbol
names, so they can be accessed from C. Made change to _edata
symbol to accommodate reshuffling of section order in platform
.ldi files.
* src/vectors.S: Add a distinctive (non-0xFF) word at the
beginning of the ROM, so that the RedBoot 'fis free' command does
not mistakenly think that the first sector of the Flash ROM is
empty. Remove tab characters that somehow snuck into the file.
* src/vectors.S: Made it possible for a platform to override
architecture defaults for the selection of ISR based on interrupt
controller state, i.e.so that a platform-specific interrupt
controller could be used or interrupt priorities set differently.
Made it possible for a platform to override the default
architecture exception/reset vector location.
-Scott
Index: arch/current/ChangeLog
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/arch/current/ChangeLog,v
retrieving revision 1.1.1.1
diff -s -c -r1.1.1.1 ChangeLog
*** arch/current/ChangeLog 22 May 2003 00:37:33 -0000 1.1.1.1
--- arch/current/ChangeLog 18 Jun 2003 03:24:00 -0000
***************
*** 1,16 ****
2003-04-25 Jonathan Larmour <jifl@eCosCentric.com>
! * src/openrisc.ld: Add some missing sections mostly just by comparison
! with another HAL..
! * include/hal_cache.h: Include hal_arch.h for MTSPR/MFSPR.
2003-04-17 Scott Furman <sfurman@rosum.com>
!
* src/vectors.S: Init tick timer on boot
* include/hal_arch.h: Ensure stack is aligned in
! HAL_THREAD_INIT_CONTEXT()
! * openrisc.ld: Add .text.ram section for time-critical code
2003-03-06 Scott Furman <sfurman@rosum.com>
--- 1,38 ----
+ 2003-05-15 Scott Furman <sfurman@rosum.com>
+
+ * src/vectors.S: Add a distinctive (non-0xFF) word at the
+ beginning of the ROM, so that the RedBoot 'fis free' command does
+ not mistakenly think that the first sector of the Flash ROM is
+ empty. Remove tab characters that somehow snuck into the file.
+
+ 2003-05-05 Scott Furman <sfurman@rosum.com>
+
+ * src/vectors.S: Made it possible for a platform to override
+ architecture defaults for the selection of ISR based on interrupt
+ controller state, i.e.so that a platform-specific interrupt
+ controller could be used or interrupt priorities set differently.
+ Made it possible for a platform to override the default
+ architecture exception/reset vector location.
+
+ * src/openrisc.ld: Removed libsupc++ requirement, as it does not
+ yet compile for OpenRISC. Added underscore prefixes to symbol
+ names, so they can be accessed from C. Made change to _edata
+ symbol to accommodate reshuffling of section order in platform
+ .ldi files.
+
2003-04-25 Jonathan Larmour <jifl@eCosCentric.com>
! * src/openrisc.ld: Add some missing sections mostly just by comparison
! with another HAL..
! * include/hal_cache.h: Include hal_arch.h for MTSPR/MFSPR.
2003-04-17 Scott Furman <sfurman@rosum.com>
!
* src/vectors.S: Init tick timer on boot
* include/hal_arch.h: Ensure stack is aligned in
! HAL_THREAD_INIT_CONTEXT()
! * openrisc.ld: Add .text.ram section for time-critical code
2003-03-06 Scott Furman <sfurman@rosum.com>
Index: arch/current/include/hal_intr.h
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/arch/current/include/hal_intr.h,v
retrieving revision 1.1.1.1
diff -s -c -r1.1.1.1 hal_intr.h
*** arch/current/include/hal_intr.h 22 May 2003 00:37:33 -0000 1.1.1.1
--- arch/current/include/hal_intr.h 14 Jun 2003 01:00:53 -0000
***************
*** 134,139 ****
--- 134,140 ----
( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
+ // Allow platform to override interrupt numbers
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
Index: arch/current/src/openrisc.ld
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/arch/current/src/openrisc.ld,v
retrieving revision 1.1.1.1
retrieving revision 1.4
diff -s -c -r1.1.1.1 -r1.4
*** arch/current/src/openrisc.ld 22 May 2003 00:37:33 -0000 1.1.1.1
--- arch/current/src/openrisc.ld 16 May 2003 19:10:57 -0000 1.4
***************
*** 53,60 ****
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
! GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
--- 53,63 ----
#ifdef EXTRAS
INPUT(extras.o)
#endif
+
+ /* FIXME: libsupc++ is not needed by eCos, but it might be needed by apps linked w/ eCos.
+ However, it does not yet compile for OpenRISC. */
#if (__GNUC__ >= 3)
! GROUP(libtarget.a libgcc.a /* libsupc++.a */ )
#else
GROUP(libtarget.a libgcc.a)
#endif
***************
*** 211,222 ****
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.ctors)) \
KEEP (*_ctors.o(.ctors)) \
! __CTOR_LIST__ = .; \
! PROVIDE (__CTOR_LIST__ = .); \
KEEP (*(.ctors)); \
KEEP (*(SORT(.ctors.*))) \
! __CTOR_END__ = .; \
! PROVIDE (__CTOR_END__ = .); \
} > _region_
#define SECTION_dtors(_region_, _vma_, _lma_) \
--- 214,225 ----
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.ctors)) \
KEEP (*_ctors.o(.ctors)) \
! ___CTOR_LIST__ = .; \
! PROVIDE (___CTOR_LIST__ = .); \
KEEP (*(.ctors)); \
KEEP (*(SORT(.ctors.*))) \
! ___CTOR_END__ = .; \
! PROVIDE (___CTOR_END__ = .); \
} > _region_
#define SECTION_dtors(_region_, _vma_, _lma_) \
***************
*** 224,235 ****
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.dtors)) \
! __DTOR_LIST__ = .; \
! PROVIDE (__DTOR_LIST__ = .); \
KEEP (*(SORT(.dtors.*))) \
! __DTOR_END__ = .; \
KEEP (*(.dtors)); \
! PROVIDE (__DTOR_END__ = .); \
} > _region_
#define SECTION_got(_region_, _vma_, _lma_) \
--- 227,238 ----
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.dtors)) \
! ___DTOR_LIST__ = .; \
! PROVIDE (___DTOR_LIST__ = .); \
KEEP (*(SORT(.dtors.*))) \
! ___DTOR_END__ = .; \
KEEP (*(.dtors)); \
! PROVIDE (___DTOR_END__ = .); \
} > _region_
#define SECTION_got(_region_, _vma_, _lma_) \
***************
*** 270,276 ****
{ \
__SDATA_START__ = ABSOLUTE(.); \
FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \
! } > _region_
#define SECTION_lit8(_region_, _vma_, _lma_) \
.lit8 _vma_ : _lma_ \
--- 273,281 ----
{ \
__SDATA_START__ = ABSOLUTE(.); \
FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \
! } > _region_ \
! __ram_data_end = .; _edata = . ; \
! PROVIDE (edata = .);
#define SECTION_lit8(_region_, _vma_, _lma_) \
.lit8 _vma_ : _lma_ \
***************
*** 283,290 ****
{ \
FORCE_OUTPUT; *(.lit4) \
} > _region_ \
- __ram_data_end = .; _edata = . ; \
- PROVIDE (edata = .);
#define SECTION_sbss(_region_, _vma_, _lma_) \
.sbss _vma_ : _lma_ \
--- 288,293 ----
Index: arch/current/src/vectors.S
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/arch/current/src/vectors.S,v
retrieving revision 1.1.1.1
diff -s -c -r1.1.1.1 vectors.S
*** arch/current/src/vectors.S 22 May 2003 00:37:33 -0000 1.1.1.1
--- arch/current/src/vectors.S 18 Jun 2003 03:22:22 -0000
***************
*** 84,93 ****
#include <cyg/hal/arch.inc>
#include <cyg/hal/openrisc.inc>
#===========================================================================
# Start by defining the exceptions vectors that must be placed in low
! # memory, starting at location 0x100.
.section ".vectors","ax"
--- 84,153 ----
#include <cyg/hal/arch.inc>
#include <cyg/hal/openrisc.inc>
+ #
+ # During ROM startup, exception code is copied from ROM to this RAM address
+ #
+ #ifndef RAM_EXCEPTION_VECTOR_BASE_ADDRESS
+ #define RAM_EXCEPTION_VECTOR_BASE_ADDRESS 0x00000000
+ #endif
+
+ #
+ # This is a platform-specific macro that dispatches to an ISR based
+ # on the state of the interrupt controller. The default version
+ # below uses the PIC defined by the OpenRISC architecture.
+ #
+ # A compatible (platform-specific) override for this macro must
+ # preserve all callee-saved regs as well as temp reg r31. On exit,
+ # r3 contains the number which will be used to index the table of ISRs.
+ #
+
+ #ifndef HAL_MAP_INTERRUPT_TO_ISR_DEFINED
+ .macro hal_map_interrupt_to_isr
+
+ # Read the PIC interrupt controller's status register
+ l.mfspr r9,r0,SPR_PICSR
+
+ # In the event of multiple pending interrupts, determine which
+ # one will be serviced first. By software convention, the lowest
+ # numbered external interrupt gets priority.
+ #
+ # The (internal) tick timer interrupt is serviced only if no
+ # external interrupts are pending.
+
+ # Any pending external interrupts ?
+ l.sfnei r9,0
+ l.bf check_for_external_interrupts
+
+ # Theoretically, the only way we could get here is if the tick timer
+ # interrupt fired, but we check to be sure that's what happened.
+ l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
+ l.bf 3f
+ l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot
+
+ #ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
+ l.jal _hal_spurious_IRQ
+ l.nop
+ #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
+ l.j ignore_spurious_interrupt
+
+ # Identify the lowest numbered interrupt bit in the PIC's PSR,
+ # numbering the MSB as 31 and the LSB as 0
+ check_for_external_interrupts:
+ l.ori r3,r0,0
+ 2: l.andi r11,r9,1 # Test low bit
+ l.sfnei r11,0
+ l.bf 3f
+ l.srli r9,r9,1 # Shift right 1 bit
+ l.j 2b
+ l.addi r3,r3,1 # Delay slot
+ 3:
+ .endm
+ #endif # ifndef HAL_MAP_INTERRUPT_TO_ISR_DEFINED
+
#===========================================================================
# Start by defining the exceptions vectors that must be placed in low
! # memory, starting at location 0x100 by default.
.section ".vectors","ax"
***************
*** 157,163 ****
l.sw 28 * OR1K_GPRSIZE(sp), r28
l.sw 30 * OR1K_GPRSIZE(sp), r30
! # save MAC LO and HI regs
l.mfspr r5,r0,SPR_MACLO
l.sw OR1KREG_MACLO(sp),r5
l.mfspr r5,r0,SPR_MACHI
--- 217,223 ----
l.sw 28 * OR1K_GPRSIZE(sp), r28
l.sw 30 * OR1K_GPRSIZE(sp), r30
! # save MAC LO and HI regs
l.mfspr r5,r0,SPR_MACLO
l.sw OR1KREG_MACLO(sp),r5
l.mfspr r5,r0,SPR_MACHI
***************
*** 182,188 ****
l.sw OR1KREG_EEAR(sp),r5
# Second arg to VSR is exception number
! # First vector is located at 0x100, second at 0x200, etc.
# Shift right to get vector number for address lookup.
l.ori r4,r0,(\org>>8)
l.sw OR1KREG_VECTOR(sp),r4
--- 242,248 ----
l.sw OR1KREG_EEAR(sp),r5
# Second arg to VSR is exception number
! # First vector is located at offset 0x100, second at 0x200, etc.
# Shift right to get vector number for address lookup.
l.ori r4,r0,(\org>>8)
l.sw OR1KREG_VECTOR(sp),r4
***************
*** 198,207 ****
l.or r3,r0,sp # Delay slot
.endm
#---------------------------------------------------------------------------
! # Define the exception vectors.
rom_vectors:
# These are the architecture-defined vectors that
# are always present.
--- 258,275 ----
l.or r3,r0,sp # Delay slot
.endm
+
+ #ifndef CYG_HAL_STARTUP_RAM
#---------------------------------------------------------------------------
! # Add distinctive (non-0xFF) word at the beginning of the ROM, so that
! # 'fis free' does not mistakenly think the Flash sector is empty.
! .word 0xbeeff00d
! .p2align 8
! #endif
+ #---------------------------------------------------------------------------
+ # Define the exception vectors.
rom_vectors:
# These are the architecture-defined vectors that
# are always present.
***************
*** 350,360 ****
hal_dcache_init
#endif
! # Start the tick timer, in case timer polling routine hal_delay_us() is called.
! # Initially, no interrupts are generated by the tick timer. Later on, that
! # may change when the kernel is initialized.
! l.movhi r3, hi(0x40000000|CYGNUM_HAL_RTC_PERIOD)
! l.mtspr r0,r3, SPR_TTMR
.globl _hal_hardware_init_done
_hal_hardware_init_done:
--- 418,428 ----
hal_dcache_init
#endif
! # Start the tick timer, in case timer polling routine hal_delay_us() is called.
! # Initially, no interrupts are generated by the tick timer. Later on, that
! # may change when the kernel is initialized.
! l.movhi r3, hi(0x40000000|CYGNUM_HAL_RTC_PERIOD)
! l.mtspr r0,r3, SPR_TTMR
.globl _hal_hardware_init_done
_hal_hardware_init_done:
***************
*** 374,381 ****
hal_vsr_table_init
#if defined(CYG_HAL_STARTUP_ROM)
! # Copy exception/interrupt vectors from ROM to address 0x100
! load32i r4,0x100
load32i r3,rom_vectors
load32i r5,rom_vectors_end
1: l.sfeq r3,r5
--- 442,449 ----
hal_vsr_table_init
#if defined(CYG_HAL_STARTUP_ROM)
! # Copy exception/interrupt vectors from ROM to address RAM
! load32i r4,RAM_EXCEPTION_VECTOR_BASE_ADDRESS + 0x100
load32i r3,rom_vectors
load32i r5,rom_vectors_end
1: l.sfeq r3,r5
***************
*** 462,469 ****
# Call C code
# When cyg_hal_exception_handler() returns, it will jump
! # directly to restore_state(), which will resume execution
! # at the location of the exception.
l.movhi r9, hi(restore_state)
l.j _cyg_hal_exception_handler
l.ori r9,r9,lo(restore_state) #Delay slot
--- 530,537 ----
# Call C code
# When cyg_hal_exception_handler() returns, it will jump
! # directly to restore_state(), which will resume execution
! # at the location of the exception.
l.movhi r9, hi(restore_state)
l.j _cyg_hal_exception_handler
l.ori r9,r9,lo(restore_state) #Delay slot
***************
*** 482,492 ****
# After we return here, the saved state is restored and execution is continued.
#ifdef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM
! .section .text.ram,"ax"
#else
! .section .text,"ax"
#endif
!
FUNC_START(cyg_hal_default_interrupt_vsr)
# Stash away pointer to saved regs for later
--- 550,560 ----
# After we return here, the saved state is restored and execution is continued.
#ifdef CYGIMP_FORCE_INTERRUPT_HANDLING_CODE_IN_RAM
! .section .text.ram,"ax"
#else
! .section .text,"ax"
#endif
!
FUNC_START(cyg_hal_default_interrupt_vsr)
# Stash away pointer to saved regs for later
***************
*** 541,584 ****
#endif
! # In the event of multiple pending interrupts, determine which
! # one will be serviced first. By software convention, the lowest
! # numbered external interrupt gets priority.
! #
! # The (internal) tick timer interrupt is serviced only if no
! # external interrupts are pending.
!
! # Read the PIC interrupt controller's status register
! l.mfspr r9,r0,SPR_PICSR
!
! # Any pending external interrupts ?
! l.sfnei r9,0
! l.bf check_for_external_interrupts
!
! # Theoretically, the only way we could get here is if the tick timer
! # interrupt fired, but we check to be sure that's what happened.
! l.sfeqi r4,CYGNUM_HAL_VECTOR_TICK_TIMER
! l.bf 3f
! l.ori r3,r0,CYGNUM_HAL_INTERRUPT_RTC # delay slot
- #ifndef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
- l.jal _hal_spurious_IRQ
- l.nop
- #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
- l.j ignore_spurious_interrupt
-
- # Identify the lowest numbered interrupt bit in the PIC's PSR,
- # numbering the MSB as 31 and the LSB as 0
- check_for_external_interrupts:
- l.ori r3,r0,0
- 2: l.andi r11,r9,1 # Test low bit
- l.sfnei r11,0
- l.bf 3f
- l.srli r9,r9,1 # Shift right 1 bit
- l.j 2b
- l.addi r3,r3,1 # Delay slot
- 3:
-
# At this point, r3 contains the ISR number, from 0-32
# which will be used to index the table of ISRs
l.slli r15,r3,2
--- 609,617 ----
#endif
! # Dispatch to ISR based on interrupt controller status
! hal_map_interrupt_to_isr
# At this point, r3 contains the ISR number, from 0-32
# which will be used to index the table of ISRs
l.slli r15,r3,2
***************
*** 721,727 ****
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
.extern _cyg_interrupt_call_pending_DSRs
! .text
FUNC_START(hal_interrupt_stack_call_pending_DSRs)
# Switch to interrupt stack
l.or r3, sp, sp # Stash entry SP
--- 754,760 ----
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
.extern _cyg_interrupt_call_pending_DSRs
! .text
FUNC_START(hal_interrupt_stack_call_pending_DSRs)
# Switch to interrupt stack
l.or r3, sp, sp # Stash entry SP
***************
*** 734,741 ****
l.sw 8(sp),lr
l.jal _cyg_interrupt_call_pending_DSRs
! # Enable interrupts before calling DSRs
! l.mtspr r0, r4, SPR_SR # Delay slot
l.lwz r4, 4(sp)
l.lwz lr, 8(sp)
--- 767,774 ----
l.sw 8(sp),lr
l.jal _cyg_interrupt_call_pending_DSRs
! # Enable interrupts before calling DSRs
! l.mtspr r0, r4, SPR_SR # Delay slot
l.lwz r4, 4(sp)
l.lwz lr, 8(sp)
Index: orp/current/ChangeLog
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/orp/current/ChangeLog,v
retrieving revision 1.1.1.1
diff -s -c -r1.1.1.1 ChangeLog
*** orp/current/ChangeLog 22 May 2003 00:37:33 -0000 1.1.1.1
--- orp/current/ChangeLog 18 Jun 2003 03:21:02 -0000
***************
*** 1,11 ****
2003-04-25 Jonathan Larmour <jifl@eCosCentric.com>
! * cdl/hal_openrisc_orp.cdl: CYGSEM_HAL_USE_ROM_MONITOR need only be a
! bool.
! CYGSEM_HAL_ROM_MONITOR should be default off (should be used later...)
! * include/pkgconf/mlt_openrisc_orp_ram.ldi: Add sections as per
! changes to arch HAL's openrisc.ld.
! * include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto.
2003-03-06 Scott Furman <sfurman@rosum.com>
--- 1,17 ----
+ 2003-05-10 Scott Furman <sfurman@rosum.com>
+
+ * include/pkgconf/mlt_openrisc_orp_ram.ldi: Repair memory layout
+ to accommodate introduction of new sections by jifl.
+ * include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto.
+
2003-04-25 Jonathan Larmour <jifl@eCosCentric.com>
! * cdl/hal_openrisc_orp.cdl: CYGSEM_HAL_USE_ROM_MONITOR need only be a
! bool.
! CYGSEM_HAL_ROM_MONITOR should be default off (should be used later...)
! * include/pkgconf/mlt_openrisc_orp_ram.ldi: Add sections as per
! changes to arch HAL's openrisc.ld.
! * include/pkgconf/mlt_openrisc_orp_rom.ldi: Ditto.
2003-03-06 Scott Furman <sfurman@rosum.com>
Index: orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi,v
retrieving revision 1.1.1.1
diff -s -c -r1.1.1.1 mlt_openrisc_orp_ram.ldi
*** orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi 22 May 2003 00:37:33 -0000 1.1.1.1
--- orp/current/include/pkgconf/mlt_openrisc_orp_ram.ldi 18 Jun 2003 02:55:53 -0000
***************
*** 11,38 ****
SECTIONS
{
SECTIONS_BEGIN
! SECTION_vectors (ram, 0x00000100, LMA_EQ_VMA)
SECTION_ROMISC (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_init (ram, ALIGN (0x8), LMA_EQ_VMA)
- SECTION_text (ram, 0x00008000, LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
- SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_ctors (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_dtors (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_devtab (ram, ALIGN (0x8), LMA_EQ_VMA)
- SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
- SECTION_dynamic (ram, ALIGN (0x8), LMA_EQ_VMA)
- SECTION_sdata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
--- 11,40 ----
SECTIONS
{
SECTIONS_BEGIN
! SECTION_vectors (ram, 0x00000000, LMA_EQ_VMA)
! SECTION_text (ram, 0x00008000, LMA_EQ_VMA)
!
! SECTION_data (ram, ALIGN(0x8), LMA_EQ_VMA)
! SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_dynamic (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_sdata (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
SECTION_ROMISC (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_init (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_ctors (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_dtors (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_devtab (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA)
!
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
Index: orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi
===================================================================
RCS file: /export/CVS/dave/ecos/packages/hal/openrisc/orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi,v
retrieving revision 1.1.1.1
diff -s -c -r1.1.1.1 mlt_openrisc_orp_rom.ldi
*** orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi 22 May 2003 00:37:33 -0000 1.1.1.1
--- orp/current/include/pkgconf/mlt_openrisc_orp_rom.ldi 18 Jun 2003 03:00:41 -0000
***************
*** 11,17 ****
SECTIONS
{
SECTIONS_BEGIN
! SECTION_vectors (rom, 0xF0000100, LMA_EQ_VMA)
SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA)
--- 11,31 ----
SECTIONS
{
SECTIONS_BEGIN
!
! SECTION_vectors (rom, 0xF0000000, LMA_EQ_VMA)
!
! // All eCos code is put in the .text section unless explicitly placed
! // into a section named section .text.ram*.
! SECTION_text_ram (ram, 0x00001000, AT(0xF0001000))
! SECTION_data (ram, ALIGN(0x8), FOLLOWING(.text.ram))
! SECTION_got (ram, ALIGN (0x8), FOLLOWING (.data))
! SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got))
! SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic))
! SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
! CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
!
! . = LOADADDR(.sdata) + SIZEOF(.sdata);
SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA)
***************
*** 21,38 ****
SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
! SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table))
! SECTION_eh_frame (ram, ALIGN (0x8), FOLLOWING (.data))
! SECTION_ctors (ram, ALIGN (0x8), FOLLOWING (.eh_frame))
! SECTION_dtors (ram, ALIGN (0x8), FOLLOWING (.ctors))
! SECTION_devtab (ram, ALIGN (0x8), FOLLOWING (.dtors))
! SECTION_got (ram, ALIGN (0x8), FOLLOWING (.devtab))
! SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got))
! SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic))
! SECTION_lit8 (ram, ALIGN (0x8), FOLLOWING (.sdata))
! SECTION_lit4 (ram, ALIGN (0x8), FOLLOWING (.lit8))
! SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
! CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
--- 35,46 ----
SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
! SECTION_eh_frame (rom, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_ctors (rom, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_dtors (rom, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_devtab (rom, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_lit8 (rom, ALIGN (0x8), LMA_EQ_VMA)
! SECTION_lit4 (rom, ALIGN (0x8), LMA_EQ_VMA)
!
SECTIONS_END
}