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fix CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR handling
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Mon, 30 Jun 2003 08:16:56 -0400 (EDT)
- Subject: fix CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR handling
Index: hal/arm/arch/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arch/current/ChangeLog,v
retrieving revision 1.91
diff -u -p -5 -r1.91 ChangeLog
--- hal/arm/arch/current/ChangeLog 24 Jun 2003 08:43:00 -0000 1.91
+++ hal/arm/arch/current/ChangeLog 30 Jun 2003 12:15:08 -0000
@@ -1,5 +1,9 @@
+2003-06-30 Mark Salter <msalter@redhat.com>
+
+ * src/vectors.S: Fix CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR handling.
+
2003-06-24 Jonathan Larmour <jifl@eCosCentric.com>
* include/hal_arch.h: Include plf_arch.h or var_arch.h if platform
or variant requires it to do overrides.
(HAL_IDLE_THREAD_ACTION): Default to empty statement but allow to be
Index: hal/arm/arch/current/src/vectors.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arch/current/src/vectors.S,v
retrieving revision 1.51
diff -u -p -5 -r1.51 vectors.S
--- hal/arm/arch/current/src/vectors.S 6 May 2003 21:00:20 -0000 1.51
+++ hal/arm/arch/current/src/vectors.S 30 Jun 2003 12:15:08 -0000
@@ -642,11 +642,10 @@ call_exception_handler:
// Return from exception
//
return_from_exception:
ldr r0,[sp,#armreg_cpsr]
- msr spsr,r0
// return to supervisor mode is simple
and r1,r0,#CPSR_MODE_BITS
cmp r1,#CPSR_SUPERVISOR_MODE
@@ -655,11 +654,21 @@ return_from_exception:
ldmeqfd sp,{r0-r14,pc}^
#else
// we must take care of not corrupting the current (svc)
// spsr which happens to be also the pre-exception spsr
bne 1f
- // we are returning to svc mode thus we must restore the
+ tst r0, #CPSR_THUMB_ENABLE
+
+ // when returning to thumb/svc mode, there is no easy way to preserve
+ // spsr. It is possible to do so, but would add a lot of instructions.
+ // The purpose of CYGOPT_HAL_ARM_PRESERVE_SVC_SPSR is to allow stepping
+ // through SWI exception handling code, so not preserving spsr in this
+ // case should be okay.
+ msrne spsr,r0
+ ldmnefd sp,{r0-r14,pc}^
+
+ // we are returning to arm/svc mode thus we must restore the
// pre-exception cpsr before returning to interrupted code
msr cpsr, r0
ldmfd sp, {r0-r14, pc}
1:
// we are not returning to svc mode thus we can safely restore