This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
uE250 - Improve PCI handling
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 08 Aug 2003 13:32:03 -0600
- Subject: uE250 - Improve PCI handling
- Organization: MLB Associates
Fix PCI handling to support external bus masters (like networking
cards that use CPU buffers)
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/arm/xscale/pxa2x0/current/ChangeLog
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/pxa2x0/current/ChangeLog,v
retrieving revision 1.3
diff -u -5 -p -r1.3 ChangeLog
--- hal/arm/xscale/pxa2x0/current/ChangeLog 1 Aug 2003 17:00:38 -0000 1.3
+++ hal/arm/xscale/pxa2x0/current/ChangeLog 8 Aug 2003 19:20:55 -0000
@@ -1,5 +1,10 @@
+2003-08-08 Gary Thomas <gary@mind.be>
+
+ * src/pxa2x0_misc.c:
+ * include/hal_pxa2x0.h: Support GPIO alternate functions.
+
2003-07-18 Nick Garnett <nickg@balti.calivar.com>
* cdl/hal_arm_xscale_pxa2x0.cdl:
Changed values for CYGNUM_HAL_RTC_NUMERATOR,
CYGNUM_HAL_RTC_DENOMINATOR and CYGNUM_HAL_RTC_PERIOD to
Index: hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h,v
retrieving revision 1.1
diff -u -5 -p -r1.1 hal_pxa2x0.h
--- hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h 22 Feb 2003 14:09:06 -0000 1.1
+++ hal/arm/xscale/pxa2x0/current/include/hal_pxa2x0.h 8 Aug 2003 19:20:32 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -431,10 +432,18 @@
#define PXA2X0_GAFR0_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0058 )
#define PXA2X0_GAFR1_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x005c )
#define PXA2X0_GAFR1_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0060 )
#define PXA2X0_GAFR2_L PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0064 )
#define PXA2X0_GAFR2_U PXA2X0_REGISTER( PXA2X0_GPIO_BASE+0x0068 )
+
+#define PXA2X0_GPIO_NORM 0x00
+#define PXA2X0_GPIO_AF1 0x01
+#define PXA2X0_GPIO_AF2 0x02
+#define PXA2X0_GPIO_AF3 0x03
+#define PXA2X0_GPIO_IN 0
+#define PXA2X0_GPIO_OUT 1
+
// Power Manager and Reset Control
#define PXA2X0_PM_BASE ( PXA2X0_PERIPHERALS_BASE + 0x0f00000 )
#define PXA2X0_PMCR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0000 )
#define PXA2X0_PSSR PXA2X0_REGISTER( PXA2X0_PM_BASE+0x0004 )
Index: hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 pxa2x0_misc.c
--- hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c 27 Feb 2003 20:59:46 -0000 1.2
+++ hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c 8 Aug 2003 19:20:56 -0000
@@ -7,10 +7,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -98,10 +99,30 @@ void hal_hardware_init(void)
#endif
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
HAL_ICACHE_ENABLE();
#endif
}
+
+//
+// GPIO support functions
+//
+void
+_pxa2x0_set_GPIO_mode(int bit, int mode, int dir)
+{
+ int bank = bit / 32;
+ unsigned long *gpdr, *gafr;
+
+ gpdr = &PXA2X0_GPDR0[bank];
+ gafr = &PXA2X0_GAFR0_L[(bit&0x30)>>4];
+ bit %= 32;
+ // Data direction registers have 1 bit per GPIO
+ *gpdr = (*gpdr & ~(1<<bit)) | (dir<<bit);
+ // Alternate function regusters have 2 bits per GPIO
+ bit = (bit & 0x0F) * 2;
+ *gafr = (*gafr & ~(3<<bit)) | (mode<<bit);
+}
+
// Initialize the clock
static cyg_uint32 clock_period;
void hal_clock_initialize(cyg_uint32 period)
Index: hal/arm/xscale/uE250/current/ChangeLog
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/uE250/current/ChangeLog,v
retrieving revision 1.5
diff -u -5 -p -r1.5 ChangeLog
--- hal/arm/xscale/uE250/current/ChangeLog 24 Jun 2003 15:31:02 -0000 1.5
+++ hal/arm/xscale/uE250/current/ChangeLog 8 Aug 2003 19:22:25 -0000
@@ -1,5 +1,13 @@
+2003-08-08 Gary Thomas <gary@mind.be>
+
+ * src/uE250_pci.c:
+ * src/uE250_misc.c: Improve PCI initialization, including support
+ for external bus masters.
+
+ * include/plf_io.h: Define CYGARC_PCI_DMA_ADDRESS()
+
2003-05-28 Gary Thomas <gary@mind.be>
* src/xilinx-load.c: Improve feedback during FPGA downloads.
2003-03-08 Gary Thomas <gary@mind.be>
Index: hal/arm/xscale/uE250/current/include/plf_io.h
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/uE250/current/include/plf_io.h,v
retrieving revision 1.4
diff -u -5 -p -r1.4 plf_io.h
--- hal/arm/xscale/uE250/current/include/plf_io.h 24 Jun 2003 15:31:02 -0000 1.4
+++ hal/arm/xscale/uE250/current/include/plf_io.h 8 Aug 2003 17:01:44 -0000
@@ -233,9 +233,10 @@ static inline unsigned cygarc_virtual_ad
return pa - 0xa0000000;
return pa;
}
#define CYGARC_VIRTUAL_ADDRESS(_x_) cygarc_virtual_address(_x_)
+#define CYGARC_PCI_DMA_ADDRESS(_x_) (_x_)
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
Index: hal/arm/xscale/uE250/current/src/uE250_misc.c
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/uE250/current/src/uE250_misc.c,v
retrieving revision 1.3
diff -u -5 -p -r1.3 uE250_misc.c
--- hal/arm/xscale/uE250/current/src/uE250_misc.c 27 Feb 2003 20:59:46 -0000 1.3
+++ hal/arm/xscale/uE250/current/src/uE250_misc.c 8 Aug 2003 19:14:38 -0000
@@ -131,16 +131,10 @@ plf_hardware_init(void)
#endif // ! CYG_HAL_STARTUP_ROM - RAM start only
hal_if_init();
cyg_hal_plf_pci_init();
- // Set up to handle PCI interrupts
- HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_GPIO1, 0, 0); // Falling edge
- HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GPIO1);
- PCICTL_INT_RESET = 0xFF; // Clear all pending interrupts
- PCICTL_INT_EDGE = 0xFF; // Generate interrupts
- PCICTL_IRQ_MASK = 0x00; // All masked
initialize_plx_bridge();
}
//
Index: hal/arm/xscale/uE250/current/src/uE250_pci.c
===================================================================
RCS file: /home/gthomas/my_cvs/develop/ecos/packages/hal/arm/xscale/uE250/current/src/uE250_pci.c,v
retrieving revision 1.3
diff -u -5 -p -r1.3 uE250_pci.c
--- hal/arm/xscale/uE250/current/src/uE250_pci.c 27 Feb 2003 20:59:46 -0000 1.3
+++ hal/arm/xscale/uE250/current/src/uE250_pci.c 8 Aug 2003 19:13:45 -0000
@@ -112,25 +112,36 @@ cyg_hal_plf_pci_init(void)
*PXA2X0_GPSR0 |= (0x01 << 7);
*PXA2X0_GPDR1 |= (0x01 << (45-32));
*PXA2X0_GPCR1 |= (0x01 << (45-32));
// Set busmastering
+ _pxa2x0_set_GPIO_mode(13, PXA2X0_GPIO_AF2, PXA2X0_GPIO_OUT);
+ _pxa2x0_set_GPIO_mode(14, PXA2X0_GPIO_AF1, PXA2X0_GPIO_IN);
+
// diag_printf("Activating PCI bridge.\n");
- PCICTL_MISC |= (1 | PCI_SDRAM_128) | PCI_TIMER;
+ PCICTL_MISC |= (1 | PCI_SDRAM_256) | PCI_TIMER;
// Set command master
- cyg_hal_plf_pci_cfg_write_byte(0,0, CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MASTER);
+ cyg_hal_plf_pci_cfg_write_word(0, 0, CYG_PCI_CFG_COMMAND,
+ CYG_PCI_CFG_COMMAND_MEMORY|CYG_PCI_CFG_COMMAND_MASTER);
// diag_printf("Scanning PCI bridge...\n");
// Initialize PCI support
cyg_pci_init();
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
+ // Set up to handle PCI interrupts
+ HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_GPIO1, 0, 0); // Falling edge
+ HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GPIO1);
+ PCICTL_INT_RESET = 0xFF; // Clear all pending interrupts
+ PCICTL_INT_EDGE = 0xFF; // Generate interrupts
+ PCICTL_IRQ_MASK = 0x00; // All masked
+
if (0){
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
@@ -144,10 +155,11 @@ cyg_hal_plf_pci_init(void)
diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
diag_printf("Device Id : 0x%08X\n", dev_info.device);
+ diag_printf("Command: 0x%04X\n", dev_info.command);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}