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PowerPC - minor GCC-3.3.1/BINUTILS-2.14.90 tweaks
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at ecos dot sourceware dot org>
- Date: 15 Oct 2003 08:38:49 -0600
- Subject: PowerPC - minor GCC-3.3.1/BINUTILS-2.14.90 tweaks
- Organization: MLB Associates
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/powerpc/moab/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/ChangeLog,v
retrieving revision 1.12
diff -u -5 -p -r1.12 ChangeLog
--- hal/powerpc/moab/current/ChangeLog 9 Oct 2003 20:34:54 -0000 1.12
+++ hal/powerpc/moab/current/ChangeLog 15 Oct 2003 14:35:06 -0000
@@ -1,5 +1,9 @@
+2003-10-15 Gary Thomas <gary@mlbassoc.com>
+
+ * cdl/hal_powerpc_moab.cdl: Remove [unused] tests so "make tests" works.
+
2003-10-09 Gary Thomas <gary@mlbassoc.com>
* include/plf.inc: Define vector 0, to make ROMRAM mode program startup
safer (don't need to remember the "-e XXX" option)
Index: hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl,v
retrieving revision 1.5
diff -u -5 -p -r1.5 hal_powerpc_moab.cdl
--- hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl 2 Oct 2003 20:12:41 -0000 1.5
+++ hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl 15 Oct 2003 13:12:55 -0000
@@ -251,11 +251,11 @@ cdl_package CYGPKG_HAL_POWERPC_MOAB {
cdl_option CYGPKG_HAL_POWERPC_MOAB_TESTS {
display "MOAB tests"
flavor data
no_define
- calculated { "tests/moabtime" }
+ calculated { "" }
description "
This option specifies the set of tests for the MOAB HAL."
}
}
Index: hal/powerpc/mpc8xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/ChangeLog,v
retrieving revision 1.32
diff -u -5 -p -r1.32 ChangeLog
--- hal/powerpc/mpc8xx/current/ChangeLog 19 Aug 2003 17:29:47 -0000 1.32
+++ hal/powerpc/mpc8xx/current/ChangeLog 15 Oct 2003 14:35:50 -0000
@@ -1,5 +1,10 @@
+2003-10-15 Gary Thomas <gary@mlbassoc.com>
+
+ * include/var_regs.h: Changes to allow building with GCC-3.3.x
+ since the newest GAS doesn't like spaces in expressions :-(
+
2003-08-19 Gary Thomas <gary@mlbassoc.com>
* src/var_misc.c:
* include/var_cache.h:
* cdl/hal_powerpc_mpc8xx.cdl: New variant 866T.
Index: hal/powerpc/mpc8xx/current/include/var_regs.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xx/current/include/var_regs.h,v
retrieving revision 1.8
diff -u -5 -p -r1.8 var_regs.h
--- hal/powerpc/mpc8xx/current/include/var_regs.h 25 Nov 2002 23:20:52 -0000 1.8
+++ hal/powerpc/mpc8xx/current/include/var_regs.h 15 Oct 2003 14:32:20 -0000
@@ -10,11 +10,11 @@
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
+// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -199,54 +199,54 @@
#ifndef CYGARC_REG_IMM_BASE // Can be defined by platform
#define CYGARC_REG_IMM_BASE 0xfa200000 // the internal memory map base
#endif
// CP Microcode Revision Number
-#define CYGARC_REG_REV_NUM (CYGARC_REG_IMM_BASE + 0x3cb0)
+#define CYGARC_REG_REV_NUM ((CYGARC_REG_IMM_BASE)+0x3cb0)
// system protection control
-#define CYGARC_REG_IMM_SYPCR (CYGARC_REG_IMM_BASE + 0x004)
+#define CYGARC_REG_IMM_SYPCR ((CYGARC_REG_IMM_BASE)+0x004)
#define CYGARC_REG_IMM_SYPCR_SWTC_MASK 0xffff0000
#define CYGARC_REG_IMM_SYPCR_BMT_MASK 0x0000ff00
#define CYGARC_REG_IMM_SYPCR_BME 0x00000080
#define CYGARC_REG_IMM_SYPCR_SWF 0x00000008
#define CYGARC_REG_IMM_SYPCR_SWE 0x00000004
#define CYGARC_REG_IMM_SYPCR_SWRI 0x00000002
#define CYGARC_REG_IMM_SYPCR_SWP 0x00000001
// interrupt pend register
-#define CYGARC_REG_IMM_SIPEND (CYGARC_REG_IMM_BASE + 0x010)
+#define CYGARC_REG_IMM_SIPEND ((CYGARC_REG_IMM_BASE)+0x010)
#define CYGARC_REG_IMM_SIPEND_IRQ0 0x80000000 // irq0 is bit 0...
// interrupt mask
-#define CYGARC_REG_IMM_SIMASK (CYGARC_REG_IMM_BASE + 0x014)
+#define CYGARC_REG_IMM_SIMASK ((CYGARC_REG_IMM_BASE)+0x014)
#define CYGARC_REG_IMM_SIMASK_IRQ0 0x80000000 // ... irq n is bit n*2
// interrupt edge level mask
-#define CYGARC_REG_IMM_SIEL (CYGARC_REG_IMM_BASE + 0x018)
+#define CYGARC_REG_IMM_SIEL ((CYGARC_REG_IMM_BASE)+0x018)
#define CYGARC_REG_IMM_SIEL_IRQ0 0x80000000
// interrupt vector
-#define CYGARC_REG_IMM_SIVEC (CYGARC_REG_IMM_BASE + 0x01c)
+#define CYGARC_REG_IMM_SIVEC ((CYGARC_REG_IMM_BASE)+0x01c)
// memory controller
-#define CYGARC_REG_IMM_BR0 (CYGARC_REG_IMM_BASE + 0x100)
-#define CYGARC_REG_IMM_OR0 (CYGARC_REG_IMM_BASE + 0x104)
-#define CYGARC_REG_IMM_BR1 (CYGARC_REG_IMM_BASE + 0x108)
-#define CYGARC_REG_IMM_OR1 (CYGARC_REG_IMM_BASE + 0x10c)
-#define CYGARC_REG_IMM_BR2 (CYGARC_REG_IMM_BASE + 0x110)
-#define CYGARC_REG_IMM_OR2 (CYGARC_REG_IMM_BASE + 0x114)
-#define CYGARC_REG_IMM_BR3 (CYGARC_REG_IMM_BASE + 0x118)
-#define CYGARC_REG_IMM_OR3 (CYGARC_REG_IMM_BASE + 0x11c)
-#define CYGARC_REG_IMM_BR4 (CYGARC_REG_IMM_BASE + 0x120)
-#define CYGARC_REG_IMM_OR4 (CYGARC_REG_IMM_BASE + 0x124)
-#define CYGARC_REG_IMM_BR5 (CYGARC_REG_IMM_BASE + 0x128)
-#define CYGARC_REG_IMM_OR5 (CYGARC_REG_IMM_BASE + 0x12c)
-#define CYGARC_REG_IMM_BR6 (CYGARC_REG_IMM_BASE + 0x130)
-#define CYGARC_REG_IMM_OR6 (CYGARC_REG_IMM_BASE + 0x134)
-#define CYGARC_REG_IMM_BR7 (CYGARC_REG_IMM_BASE + 0x138)
-#define CYGARC_REG_IMM_OR7 (CYGARC_REG_IMM_BASE + 0x13c)
+#define CYGARC_REG_IMM_BR0 ((CYGARC_REG_IMM_BASE)+0x100)
+#define CYGARC_REG_IMM_OR0 ((CYGARC_REG_IMM_BASE)+0x104)
+#define CYGARC_REG_IMM_BR1 ((CYGARC_REG_IMM_BASE)+0x108)
+#define CYGARC_REG_IMM_OR1 ((CYGARC_REG_IMM_BASE)+0x10c)
+#define CYGARC_REG_IMM_BR2 ((CYGARC_REG_IMM_BASE)+0x110)
+#define CYGARC_REG_IMM_OR2 ((CYGARC_REG_IMM_BASE)+0x114)
+#define CYGARC_REG_IMM_BR3 ((CYGARC_REG_IMM_BASE)+0x118)
+#define CYGARC_REG_IMM_OR3 ((CYGARC_REG_IMM_BASE)+0x11c)
+#define CYGARC_REG_IMM_BR4 ((CYGARC_REG_IMM_BASE)+0x120)
+#define CYGARC_REG_IMM_OR4 ((CYGARC_REG_IMM_BASE)+0x124)
+#define CYGARC_REG_IMM_BR5 ((CYGARC_REG_IMM_BASE)+0x128)
+#define CYGARC_REG_IMM_OR5 ((CYGARC_REG_IMM_BASE)+0x12c)
+#define CYGARC_REG_IMM_BR6 ((CYGARC_REG_IMM_BASE)+0x130)
+#define CYGARC_REG_IMM_OR6 ((CYGARC_REG_IMM_BASE)+0x134)
+#define CYGARC_REG_IMM_BR7 ((CYGARC_REG_IMM_BASE)+0x138)
+#define CYGARC_REG_IMM_OR7 ((CYGARC_REG_IMM_BASE)+0x13c)
#define CYGARC_REG_IMM_BR_BA_MASK 0xffff8000 // base address
#define CYGARC_REG_IMM_BR_AT_MASK 0x00007000 // address type
#define CYGARC_REG_IMM_BR_PS_8 0x00000400 // port size 8 bits
#define CYGARC_REG_IMM_BR_PS_16 0x00000800 // port size 16 bits
@@ -273,27 +273,27 @@
#define CYGARC_REG_IMM_OR_SETA 0x00000008 // external transfer ack
#define CYGARC_REG_IMM_OR_TRLX 0x00000004 // timing relaxed
#define CYGARC_REG_IMM_OR_EHTR 0x00000002 // extended hold time on read
// timebase status and control
-#define CYGARC_REG_IMM_TBSCR (CYGARC_REG_IMM_BASE + 0x200)
+#define CYGARC_REG_IMM_TBSCR ((CYGARC_REG_IMM_BASE)+0x200)
#define CYGARC_REG_IMM_TBSCR_REFA 0x0080 // reference interrupt status A
#define CYGARC_REG_IMM_TBSCR_REFB 0x0040 // reference interrupt status B
#define CYGARC_REG_IMM_TBSCR_REFAE 0x0008 // reference interrupt enable A
#define CYGARC_REG_IMM_TBSCR_REFBE 0x0004 // reference interrupt enable B
#define CYGARC_REG_IMM_TBSCR_TBF 0x0002 // timebase freeze
#define CYGARC_REG_IMM_TBSCR_TBE 0x0001 // timebase enable
#define CYGARC_REG_IMM_TBSCR_IRQ0 0x8000 // highest interrupt level
#define CYGARC_REG_IMM_TBSCR_IRQMASK 0xff00 // irq priority mask
// timebase reference register 0
-#define CYGARC_REG_IMM_TBREF0 (CYGARC_REG_IMM_BASE + 0x204)
+#define CYGARC_REG_IMM_TBREF0 ((CYGARC_REG_IMM_BASE)+0x204)
// timebase reference register 1
-#define CYGARC_REG_IMM_TBREF1 (CYGARC_REG_IMM_BASE + 0x208)
+#define CYGARC_REG_IMM_TBREF1 ((CYGARC_REG_IMM_BASE)+0x208)
// real time clock
-#define CYGARC_REG_IMM_RTCSC (CYGARC_REG_IMM_BASE + 0x220)
+#define CYGARC_REG_IMM_RTCSC ((CYGARC_REG_IMM_BASE)+0x220)
#define CYGARC_REG_IMM_RTCSC_SEC 0x0080 // once per second interrupt
#define CYGARC_REG_IMM_RTCSC_ALR 0x0040 // alarm interrupt
#define CYGARC_REG_IMM_RTCSC_38K 0x0010 // source select
#define CYGARC_REG_IMM_RTCSC_SIE 0x0008 // second interrupt enable
#define CYGARC_REG_IMM_RTCSC_ALE 0x0004 // alarm interrupt enable
@@ -301,45 +301,45 @@
#define CYGARC_REG_IMM_RTCSC_RTE 0x0001 // real time clock enable
#define CYGARC_REG_IMM_RTCSC_IRQ0 0x8000 // highest interrupt level
#define CYGARC_REG_IMM_RTCSC_IRQMASK 0xff00 // irq priority mask
// periodic interrupt status & ctrl
-#define CYGARC_REG_IMM_PISCR (CYGARC_REG_IMM_BASE + 0x240)
+#define CYGARC_REG_IMM_PISCR ((CYGARC_REG_IMM_BASE)+0x240)
#define CYGARC_REG_IMM_PISCR_PS 0x0080 // periodic interrupt status
#define CYGARC_REG_IMM_PISCR_PIE 0x0004 // periodic interrupt enable
#define CYGARC_REG_IMM_PISCR_PITF 0x0002 // periodic interrupt timer freeze
#define CYGARC_REG_IMM_PISCR_PTE 0x0001 // periodic timer enable
#define CYGARC_REG_IMM_PISCR_IRQ0 0x8000 // highest interrupt level
#define CYGARC_REG_IMM_PISCR_IRQMASK 0xff00 // irq priority mask
// periodic interrupt timer count
-#define CYGARC_REG_IMM_PITC (CYGARC_REG_IMM_BASE + 0x244)
+#define CYGARC_REG_IMM_PITC ((CYGARC_REG_IMM_BASE)+0x244)
#define CYGARC_REG_IMM_PITC_COUNT_SHIFT 16 // count is stored in bits 0-15
// system clock control
-#define CYGARC_REG_IMM_SCCR (CYGARC_REG_IMM_BASE + 0x280)
+#define CYGARC_REG_IMM_SCCR ((CYGARC_REG_IMM_BASE)+0x280)
#define CYGARC_REG_IMM_SCCR_TBS 0x02000000 // timebase source
#define CYGARC_REG_IMM_SCCR_RTDIV 0x01000000 // rtc clock divide
#define CYGARC_REG_IMM_SCCR_RTSEL 0x00800000 // rtc clock select
// CPM interrupt vector register
-#define CYGARC_REG_IMM_CIVR (CYGARC_REG_IMM_BASE + 0x930)
+#define CYGARC_REG_IMM_CIVR ((CYGARC_REG_IMM_BASE)+0x930)
#define CYGARC_REG_IMM_CIVR_IACK 0x0001 // set this to update register
#define CYGARC_REG_IMM_CIVR_VECTOR_SHIFT 11 // vector is at bits 0-4
// CPM interrupt configuration reg
-#define CYGARC_REG_IMM_CICR (CYGARC_REG_IMM_BASE + 0x940)
+#define CYGARC_REG_IMM_CICR ((CYGARC_REG_IMM_BASE)+0x940)
#define CYGARC_REG_IMM_CICR_IEN 0x00000080 // interrupt enable
#define CYGARC_REG_IMM_CICR_IRQMASK 0x0000e000 // irq priority mask
#define CYGARC_REG_IMM_CICR_IRQ_SHIFT 13
// CPM interrupt in-pending register
-#define CYGARC_REG_IMM_CIPR (CYGARC_REG_IMM_BASE + 0x944)
+#define CYGARC_REG_IMM_CIPR ((CYGARC_REG_IMM_BASE)+0x944)
// CPM interrupt mask register
-#define CYGARC_REG_IMM_CIMR (CYGARC_REG_IMM_BASE + 0x948)
+#define CYGARC_REG_IMM_CIMR ((CYGARC_REG_IMM_BASE)+0x948)
// CPM interrupt in-service register
-#define CYGARC_REG_IMM_CISR (CYGARC_REG_IMM_BASE + 0x94C)
+#define CYGARC_REG_IMM_CISR ((CYGARC_REG_IMM_BASE)+0x94C)
#define CYGARC_SIU_PRIORITY_LOW 7 // the lowest irq priority
#define CYGARC_SIU_PRIORITY_HIGH 0 // the highest irq priority
Index: hal/powerpc/ppc40x/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc40x/current/ChangeLog,v
retrieving revision 1.11
diff -u -5 -p -r1.11 ChangeLog
--- hal/powerpc/ppc40x/current/ChangeLog 2 Oct 2003 20:12:59 -0000 1.11
+++ hal/powerpc/ppc40x/current/ChangeLog 15 Oct 2003 14:36:22 -0000
@@ -1,5 +1,10 @@
+2003-10-15 Gary Thomas <gary@mlbassoc.com>
+
+ * include/var_regs.h: Changes to allow building with GCC-3.3.x
+ since the newest GAS doesn't like spaces in expressions :-(
+
2003-10-02 Gary Thomas <gary@mlbassoc.com>
* include/var_regs.h: Add CPU serial number registers (405 only)
2003-09-26 Gary Thomas <gary@mlbassoc.com>
Index: hal/powerpc/ppc40x/current/include/var_regs.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ppc40x/current/include/var_regs.h,v
retrieving revision 1.7
diff -u -5 -p -r1.7 var_regs.h
--- hal/powerpc/ppc40x/current/include/var_regs.h 2 Oct 2003 20:12:59 -0000 1.7
+++ hal/powerpc/ppc40x/current/include/var_regs.h 15 Oct 2003 13:23:47 -0000
@@ -173,15 +173,15 @@
#define DCR_OCM0_ISCNTL 0x19 // Instruction side control
#define DCR_OCM0_DSARC 0x1A // Data side address compare
#define DCR_OCM0_DSCNTL 0x1B // Data side control
// I2C controller
-#define IIC0_MDBUF (_PPC405GP_IIC0+0x00) // Master data buffer
-#define IIC0_SDBUF (_PPC405GP_IIC0+0x02) // Slave data buffer
-#define IIC0_LMADR (_PPC405GP_IIC0+0x04) // Master address (low)
-#define IIC0_HMADR (_PPC405GP_IIC0+0x05) // Master address (high)
-#define IIC0_CNTL (_PPC405GP_IIC0+0x06) // Control
+#define IIC0_MDBUF ((_PPC405GP_IIC0)+0x00) // Master data buffer
+#define IIC0_SDBUF ((_PPC405GP_IIC0)+0x02) // Slave data buffer
+#define IIC0_LMADR ((_PPC405GP_IIC0)+0x04) // Master address (low)
+#define IIC0_HMADR ((_PPC405GP_IIC0)+0x05) // Master address (high)
+#define IIC0_CNTL ((_PPC405GP_IIC0)+0x06) // Control
#define IIC0_CNTL_HMT 0x80 // Halt master transfer
#define IIC0_CNTL_AMD 0x40 // Address mode (0=7 bit, 1=10 bit)
#define IIC0_CNTL_TCT 0x30 // Transfer size (1-4 bytes)
#define IIC0_CNTL_TCT_SHIFT 4
#define IIC0_CNTL_TCT_1 0x00
@@ -192,28 +192,28 @@
#define IIC0_CNTL_CHT 0x04 // Chain transfer
#define IIC0_CNTL_RW 0x02 // Read/write
#define IIC0_CNTL_RW_READ 0x02
#define IIC0_CNTL_RW_WRITE 0x00
#define IIC0_CNTL_PT 0x01 // Pending transfer
-#define IIC0_MDCNTL (_PPC405GP_IIC0+0x07) // Mode control
+#define IIC0_MDCNTL ((_PPC405GP_IIC0)+0x07) // Mode control
#define IIC0_MDCNTL_FSDB 0x80 // Flush slave data buffer
#define IIC0_MDCNTL_FMDB 0x40 // Flush master data buffer
#define IIC0_MDCNTL_FSM 0x10 // Fast/standard mode (1=fast)
#define IIC0_MDCNTL_ESM 0x08 // Enable slave mode
#define IIC0_MDCNTL_EINT 0x04 // Enable interrupt
#define IIC0_MDCNTL_EUBS 0x02 // Exit unknown bus state
#define IIC0_MDCNTL_HSCL 0x01 // Hold serial clock low (slave only)
-#define IIC0_STS (_PPC405GP_IIC0+0x08) // Status
+#define IIC0_STS ((_PPC405GP_IIC0)+0x08) // Status
#define IIC0_STS_SSS 0x80 // Slave operation in progress
#define IIC0_STS_SLPR 0x40 // Sleep request
#define IIC0_STS_MDBS 0x20 // Master data buffer status (0=empty)
#define IIC0_STS_MDBF 0x10 // Master data buffer status (1=full)
#define IIC0_STS_SCMP 0x08 // Stop complete
#define IIC0_STS_ERR 0x04 // Error
#define IIC0_STS_IRQA 0x02 // Interrupt active
#define IIC0_STS_PT 0x01 // Transfer pending
-#define IIC0_EXTSTS (_PPC405GP_IIC0+0x09) // Extended status
+#define IIC0_EXTSTS ((_PPC405GP_IIC0)+0x09) // Extended status
#define IIC0_EXTSTS_IRQP 0x80 // Interrupt pending
#define IIC0_EXTSTS_BCS 0x70 // Bus status
#define IIC0_EXTSTS_BCS_ss 0x10 // Slave selected
#define IIC0_EXTSTS_BCS_st 0x20 // Slave transfer
#define IIC0_EXTSTS_BCS_mt 0x30 // Master transfer
@@ -221,58 +221,58 @@
#define IIC0_EXTSTS_BCS_busy 0x50 // Bus busy
#define IIC0_EXTSTS_IRQD 0x08 // IRQ on deck
#define IIC0_EXTSTS_LA 0x04 // Lost arbitration
#define IIC0_EXTSTS_ICT 0x02 // Incomplete transfer
#define IIC0_EXTSTS_XFRA 0x01 // Transfer aborted
-#define IIC0_LSADR (_PPC405GP_IIC0+0x0A) // Slave address (low)
-#define IIC0_HSADR (_PPC405GP_IIC0+0x0B) // Slave address (high)
-#define IIC0_CLKDIV (_PPC405GP_IIC0+0x0C) // Clock divide
-#define IIC0_INTRMSK (_PPC405GP_IIC0+0x0D) // Interrupt mask
-#define IIC0_XFRCNT (_PPC405GP_IIC0+0x0E) // Transfer count
+#define IIC0_LSADR ((_PPC405GP_IIC0)+0x0A) // Slave address (low)
+#define IIC0_HSADR ((_PPC405GP_IIC0)+0x0B) // Slave address (high)
+#define IIC0_CLKDIV ((_PPC405GP_IIC0)+0x0C) // Clock divide
+#define IIC0_INTRMSK ((_PPC405GP_IIC0)+0x0D) // Interrupt mask
+#define IIC0_XFRCNT ((_PPC405GP_IIC0)+0x0E) // Transfer count
#define IIC0_XFRCNT_STC 0x70 // Slave transfer count
#define IIC0_XFRCNT_STC_SHIFT 4
#define IIC0_XFRCNT_MTC 0x07 // Master transfer count
#define IIC0_XFRCNT_MTC_SHIFT 0
-#define IIC0_XTCNTLSS (_PPC405GP_IIC0+0x0F) // Extended control & slave status
-#define IIC0_DIRECT (_PPC405GP_IIC0+0x10) // Direct control over I/O lines
+#define IIC0_XTCNTLSS ((_PPC405GP_IIC0)+0x0F) // Extended control & slave status
+#define IIC0_DIRECT ((_PPC405GP_IIC0)+0x10) // Direct control over I/O lines
// GPIO (General Purpose I/O)
-#define GPIO_OR (_PPC405GP_GPIO+0x00) // Output register
-#define GPIO_TCR (_PPC405GP_GPIO+0x04) // Tri-state control
-#define GPIO_OSRH (_PPC405GP_GPIO+0x08) // Output select (high)
-#define GPIO_OSRL (_PPC405GP_GPIO+0x0C) // Output select (low)
-#define GPIO_TSRH (_PPC405GP_GPIO+0x10) // Tri-state select (high)
-#define GPIO_TSRL (_PPC405GP_GPIO+0x14) // Tri-state select (low)
-#define GPIO_ODR (_PPC405GP_GPIO+0x18) // Open drain
-#define GPIO_IR (_PPC405GP_GPIO+0x1C) // Input register
-#define GPIO_RR (_PPC405GP_GPIO+0x20) // Receive register
-#define GPIO_ISRH (_PPC405GP_GPIO+0x30) // Input select (high)
-#define GPIO_ISRL (_PPC405GP_GPIO+0x34) // Input select (low)
+#define GPIO_OR ((_PPC405GP_GPIO)+0x00) // Output register
+#define GPIO_TCR ((_PPC405GP_GPIO)+0x04) // Tri-state control
+#define GPIO_OSRH ((_PPC405GP_GPIO)+0x08) // Output select (high)
+#define GPIO_OSRL ((_PPC405GP_GPIO)+0x0C) // Output select (low)
+#define GPIO_TSRH ((_PPC405GP_GPIO)+0x10) // Tri-state select (high)
+#define GPIO_TSRL ((_PPC405GP_GPIO)+0x14) // Tri-state select (low)
+#define GPIO_ODR ((_PPC405GP_GPIO)+0x18) // Open drain
+#define GPIO_IR ((_PPC405GP_GPIO)+0x1C) // Input register
+#define GPIO_RR ((_PPC405GP_GPIO)+0x20) // Receive register
+#define GPIO_ISRH ((_PPC405GP_GPIO)+0x30) // Input select (high)
+#define GPIO_ISRL ((_PPC405GP_GPIO)+0x34) // Input select (low)
// PCI
// PCI Bridge
-#define PCIL0_PMM0LA (_PPC405GP_PCI_BRIDGE+0x00) // PMM 0 Local address
-#define PCIL0_PMM0MA (_PPC405GP_PCI_BRIDGE+0x04) // PMM 0 Mask/Attributes
-#define PCIL0_PMM0PCILA (_PPC405GP_PCI_BRIDGE+0x08) // PMM 0 PCI Low Address
-#define PCIL0_PMM0PCIHA (_PPC405GP_PCI_BRIDGE+0x0C) // PMM 0 PCI High Address
-#define PCIL0_PMM1LA (_PPC405GP_PCI_BRIDGE+0x10) // PMM 1 Local address
-#define PCIL0_PMM1MA (_PPC405GP_PCI_BRIDGE+0x14) // PMM 1 Mask/Attributes
-#define PCIL0_PMM1PCILA (_PPC405GP_PCI_BRIDGE+0x18) // PMM 1 PCI Low Address
-#define PCIL0_PMM1PDIHA (_PPC405GP_PCI_BRIDGE+0x1C) // PMM 1 PCI High Address
-#define PCIL0_PMM2LA (_PPC405GP_PCI_BRIDGE+0x20) // PMM 2 Local address
-#define PCIL0_PMM2MA (_PPC405GP_PCI_BRIDGE+0x24) // PMM 2 Mask/Attributes
-#define PCIL0_PMM2PCILA (_PPC405GP_PCI_BRIDGE+0x28) // PMM 2 PCI Low Address
-#define PCIL0_PMM2PCIHA (_PPC405GP_PCI_BRIDGE+0x2C) // PMM 2 PCI High Address
-#define PCIL0_PTM1MS (_PPC405GP_PCI_BRIDGE+0x30) // PTM 1 Memory Size/Attribute
-#define PCIL0_PTM1LA (_PPC405GP_PCI_BRIDGE+0x34) // PTM 1 Local address
-#define PCIL0_PTM2MS (_PPC405GP_PCI_BRIDGE+0x38) // PTM 2 Memory Size/Attribute
-#define PCIL0_PTM2LA (_PPC405GP_PCI_BRIDGE+0x3C) // PTM 2 Local address
+#define PCIL0_PMM0LA ((_PPC405GP_PCI_BRIDGE)+0x00) // PMM 0 Local address
+#define PCIL0_PMM0MA ((_PPC405GP_PCI_BRIDGE)+0x04) // PMM 0 Mask/Attributes
+#define PCIL0_PMM0PCILA ((_PPC405GP_PCI_BRIDGE)+0x08) // PMM 0 PCI Low Address
+#define PCIL0_PMM0PCIHA ((_PPC405GP_PCI_BRIDGE)+0x0C) // PMM 0 PCI High Address
+#define PCIL0_PMM1LA ((_PPC405GP_PCI_BRIDGE)+0x10) // PMM 1 Local address
+#define PCIL0_PMM1MA ((_PPC405GP_PCI_BRIDGE)+0x14) // PMM 1 Mask/Attributes
+#define PCIL0_PMM1PCILA ((_PPC405GP_PCI_BRIDGE)+0x18) // PMM 1 PCI Low Address
+#define PCIL0_PMM1PDIHA ((_PPC405GP_PCI_BRIDGE)+0x1C) // PMM 1 PCI High Address
+#define PCIL0_PMM2LA ((_PPC405GP_PCI_BRIDGE)+0x20) // PMM 2 Local address
+#define PCIL0_PMM2MA ((_PPC405GP_PCI_BRIDGE)+0x24) // PMM 2 Mask/Attributes
+#define PCIL0_PMM2PCILA ((_PPC405GP_PCI_BRIDGE)+0x28) // PMM 2 PCI Low Address
+#define PCIL0_PMM2PCIHA ((_PPC405GP_PCI_BRIDGE)+0x2C) // PMM 2 PCI High Address
+#define PCIL0_PTM1MS ((_PPC405GP_PCI_BRIDGE)+0x30) // PTM 1 Memory Size/Attribute
+#define PCIL0_PTM1LA ((_PPC405GP_PCI_BRIDGE)+0x34) // PTM 1 Local address
+#define PCIL0_PTM2MS ((_PPC405GP_PCI_BRIDGE)+0x38) // PTM 2 Memory Size/Attribute
+#define PCIL0_PTM2LA ((_PPC405GP_PCI_BRIDGE)+0x3C) // PTM 2 Local address
// Access to local/bridge PCI configuration registers
-#define PCIC0_CFGADDR (_PPC405GP_PCI_IO+0x00C00000) // Indirect address pointer
-#define PCIC0_CFGDATA (_PPC405GP_PCI_IO+0x00C00004) // Indirect data
+#define PCIC0_CFGADDR ((_PPC405GP_PCI_IO)+0x00C00000) // Indirect address pointer
+#define PCIC0_CFGDATA ((_PPC405GP_PCI_IO)+0x00C00004) // Indirect data
// Debug control registers (SPR)
#define SPR_DBCR0 0x3F2
#endif // PPC4XX_405 || PPC4XX_405GP