diff -r -u5 -N -x CVS -x '*~' -x '.#*' -x '*bak' -x '*org' clean/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog devo/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog
--- clean/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog	2003-10-13 11:36:16.000000000 -0400
+++ devo/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog	2003-10-29 10:10:06.000000000 -0500
@@ -1,5 +1,10 @@
+2003-10-29  Radu Cernea  <rc@unusus.com>
+
+	* src/quicc_smc_serial.c: SMC2 port initialization fixed for MPC850
+    processor.
+
 2003-10-13  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/quicc_smc_serial.c: Add some I/O barriers to make sure that
 	operations happen in the correct order.  Fixes BUG #90391
 
diff -r -u5 -N -x CVS -x '*~' -x '.#*' -x '*bak' -x '*org' clean/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c devo/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
--- clean/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	2003-10-13 11:36:16.000000000 -0400
+++ devo/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c	2003-10-29 10:21:52.000000000 -0500
@@ -371,11 +371,11 @@
                            volatile struct smc_regs *ctl,
                            int TxBD, int TxNUM, int TxSIZE,
                            cyg_uint8 *TxBUF,
                            int RxBD, int RxNUM, int RxSIZE,
                            cyg_uint8 *RxBUF,
-                           int portBmask,
+                           int portMask,
                            int port)
 {
     EPPC *eppc = eppc_base();
     struct cp_bufdesc *txbd, *rxbd;
     int i;
@@ -387,17 +387,39 @@
     smc_chan->brg = _mpc8xx_allocate_brg(port);
 
     // Disable channel during setup
     ctl->smc_smcmr = QUICC_SMCMR_UART;  // Disabled, UART mode
 
-    /*
-     *  Set up the PortB pins for UART operation.
-     *  Set PAR and DIR to allow SMCTXDx and SMRXDx
-     *  (Table 16-39)
-     */
-    eppc->pip_pbpar |= portBmask;
-    eppc->pip_pbdir &= ~portBmask;
+	if(port == QUICC_CPM_SMC1){
+        /*
+         *  Set up the PortB pins for UART operation.
+         *  Set PAR and DIR to allow SMCTXDx and SMRXDx
+         *  (Table 34-6 in MPC860UM.pdf)
+         */
+        eppc->pip_pbpar |= portMask;
+        eppc->pip_pbdir &= ~portMask;
+    }
+	else{
+        // QUICC_CPM_SMC2 port
+#if defined(CYGHWR_HAL_POWERPC_850) || defined(CYGHWR_HAL_POWERPC_823)
+        /*
+         *  Set up the PortA pins for UART operation.
+         *  Set PAR and DIR to allow SMCTXDx and SMRXDx
+         *  (Table 34-1 in MPC850UM.pdf)
+         */
+        eppc->pip_papar |= portMask;
+        eppc->pip_padir &= ~portMask;
+#else
+        /*
+         *  Set up the PortB pins for UART operation.
+         *  Set PAR and DIR to allow SMCTXDx and SMRXDx
+         *  (Table 34-6 in MPC860UM.pdf)
+         */
+        eppc->pip_pbpar |= portMask;
+        eppc->pip_pbdir &= ~portMask;
+#endif
+    }
     /*
      *  SDMA & LCD bus request level 5
      *  (Section 16.10.2.1)
      */
     eppc->dma_sdcr = 1;
@@ -663,11 +685,15 @@
                                    &quicc_smc2_txbuf[0],
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
                                    &quicc_smc2_rxbuf[0],
+#if defined(CYGHWR_HAL_POWERPC_850) || defined(CYGHWR_HAL_POWERPC_823)
+                                   0xC0, // PortA mask
+#else
                                    0xC00, // PortB mask
+#endif
                                    QUICC_CPM_SMC2
             );
     }
 #endif
 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SCC1
diff -r -u5 -N -x CVS -x '*~' -x '.#*' -x '*bak' -x '*org' clean/ecos/packages/hal/powerpc/quicc/current/ChangeLog devo/ecos/packages/hal/powerpc/quicc/current/ChangeLog
--- clean/ecos/packages/hal/powerpc/quicc/current/ChangeLog	2003-09-08 10:55:36.000000000 -0400
+++ devo/ecos/packages/hal/powerpc/quicc/current/ChangeLog	2003-10-29 09:46:46.000000000 -0500
@@ -1,5 +1,10 @@
+2003-10-29  Radu Cernea  <rc@unusus.com>
+
+	* src/quicc_smc1.c: Fix SMC2 port pins initialization 
+    for MPC860 and MPC821 (different from MPC850).
+
 2003-09-08  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/quicc_smc1.c: Fix baud rate clock setup - was off by 1.
 	Reported by Tord Andersson <Tord.Andersson@combitechsystems.com>
 
diff -r -u5 -N -x CVS -x '*~' -x '.#*' -x '*bak' -x '*org' clean/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c devo/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
--- clean/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c	2003-09-08 10:55:36.000000000 -0400
+++ devo/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c	2003-10-29 09:45:46.000000000 -0500
@@ -161,16 +161,21 @@
 #if CYGNUM_HAL_QUICC_SMC2 > 0
     case QUICC_CPM_SMC2:
         /*
          *  Set up the PortA pins for UART operation.
          *  Set PAR and DIR to allow SMCTXD2 and SMRXD2
-         *  (Table 16-39)
+         *  (Table 34-1 and 34-6 in MPC860UM.pdf and MPC850UM.pdf)
          */
+#if defined(CYGHWR_HAL_POWERPC_860) || defined(CYGHWR_HAL_POWERPC_860T) || defined (CYGHWR_HAL_POWERPC_821)
+        eppc->pip_pbpar |=  0x00000C00;
+        eppc->pip_pbdir &= ~0x00000C00;
+        eppc->pip_pbodr &= ~0x00000C00;
+#else
         eppc->pio_papar |= 0xc0;
         eppc->pio_padir &= ~0xc0;
         eppc->pio_paodr &= ~0xc0;
-
+#endif
         break;
 #endif
     }
 
     // Set up baud rate generator.  These are allocated from a