This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
EC555 (PowerPC) target updates
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at ecos dot sourceware dot org>
- Date: 24 Nov 2003 07:29:04 -0700
- Subject: EC555 (PowerPC) target updates
- Organization: MLB Associates
on behalf of Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ChangeLog,v
retrieving revision 1.129
diff -u -5 -p -r1.129 ChangeLog
--- ChangeLog 22 Nov 2003 13:05:57 -0000 1.129
+++ ChangeLog 24 Nov 2003 14:06:01 -0000
@@ -4,10 +4,14 @@
2003-11-09 Gary Thomas <gary@mlbassoc.com>
* ecos.db: Add serial I/O package for Motorola MPC8xxx (QUICC-II)
+2003-11-05 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * ecos.db: New packages - ethernet and watchdog for EC555
+
2003-11-04 Andrew Lunn <andrew.lunn@ascom.ch>
* ecos.db: Modified the e7t to use the new 39VFXXX flash driver
2003-11-04 Andrew Lunn <andrew.lunn@ascom.ch>
Index: ecos.db
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/ecos.db,v
retrieving revision 1.113
diff -u -5 -p -r1.113 ecos.db
--- ecos.db 22 Nov 2003 13:05:57 -0000 1.113
+++ ecos.db 24 Nov 2003 14:06:02 -0000
@@ -1490,10 +1490,18 @@ package CYGPKG_DEVS_ETH_POWERPC_VIPER {
directory devs/eth/powerpc/viper
script viper_eth_drivers.cdl
description "Ethernet driver specifics for A&M Viper (MPC8xxT) based boards."
}
+package CYGPKG_DEVS_ETH_POWERPC_EC555 {
+ alias { "Crystal LAN ethernet driver for ec555 boards" ec555_eth_driver }
+ hardware
+ directory devs/eth/powerpc/ec555
+ script ec555_eth_drivers.cdl
+ description "Ethernet driver for Crystal LAN on ec555 board."
+}
+
package CYGPKG_DEVS_ETH_INTEL_I82559 {
alias { "Intel 82559 ethernet driver"
devs_eth_intel_i82559 i82559_eth_driver }
hardware
directory devs/eth/intel/i82559
@@ -1850,10 +1858,20 @@ package CYGPKG_DEVICES_WATCHDOG_MN10300_
script watchdog_mn10300.cdl
hardware
description "
This package provides a watchdog driver implementation for the
MN10300 chip."
+}
+
+package CYGPKG_DEVICES_WATCHDOG_MPC5xx {
+ alias { "Watchdog driver for mpc5xx processor" devices_watchdog_mpc5xx device_watchdog_mpc5xx }
+ directory devs/watchdog/powerpc/mpc5xx
+ script watchdog_mpc5xx.cdl
+ hardware
+ description "
+ This package provides a watchdog driver implementation for the
+ mpc5xx processor family."
}
package CYGPKG_DEVICES_WATCHDOG_SH_SH3 {
alias { "Watchdog driver for the Hitachi SH3 chip" devices_watchdog_sh3 device_watchdog_sh3 }
directory devs/watchdog/sh/sh3
Index: devs/eth/cl/cs8900a/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/cl/cs8900a/current/ChangeLog,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ChangeLog
--- devs/eth/cl/cs8900a/current/ChangeLog 12 Apr 2003 03:50:18 -0000 1.7
+++ devs/eth/cl/cs8900a/current/ChangeLog 5 Nov 2003 21:08:42 -0000
@@ -1,5 +1,9 @@
+2003-11-05 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * src/if_cs8900a.c: Fix handling of odd bytes on big endian machines
+
2003-04-12 Jonathan Larmour <jifl@eCosCentric.com>
* src/if_cs8900a.c (cs8900a_send): Allow for data not being 16-bit
aligned. Thanks to Laurent Gonzalez <laurent.gonzalez@ri.silicomp.fr>
for reporting this and his initial patch.
Index: devs/eth/cl/cs8900a/current/src/if_cs8900a.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c,v
retrieving revision 1.7
diff -u -5 -p -r1.7 if_cs8900a.c
--- devs/eth/cl/cs8900a/current/src/if_cs8900a.c 12 Apr 2003 03:50:19 -0000 1.7
+++ devs/eth/cl/cs8900a/current/src/if_cs8900a.c 5 Nov 2003 21:01:58 -0000
@@ -470,21 +470,22 @@ cs8900a_send(struct eth_drv_sc *sc, stru
len = sg_list[i].len;
if (len > 0) {
/* Finish the last word. */
if (odd_byte) {
- // Add data to the most significant byte
#if(CYG_BYTEORDER == CYG_LSBFIRST)
+ // Add data to the most significant byte
saved_data |= ((cyg_uint16)*data++) << 8;
#elif(CYG_BYTEORDER == CYG_MSBFIRST)
- saved_data = ((cyg_uint16)*data++) | (saved_data << 8);
+ // Add data to the least significant byte
+ saved_data |= *data++;
#endif
HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
len--;
odd_byte = false;
}
- if ((CYG_ADDRESS)data & 0x1 == 0) {
+ if (((CYG_ADDRESS)data & 0x1) == 0) {
/* Aligned on 16-bit boundary, so output contiguous words. */
sdata = (cyg_uint16 *)data;
while (len > 1) {
HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, *sdata++);
len -= sizeof(cyg_uint16);
@@ -504,10 +505,13 @@ cs8900a_send(struct eth_drv_sc *sc, stru
}
}
/* Save last byte, if necessary. */
if (len == 1) {
saved_data = (cyg_uint16)*data;
+#if CYG_BYTEORDER == CYG_MSBFIRST
+ saved_data = (saved_data << 8);
+#endif
odd_byte = true;
}
}
}
if (odd_byte) {
Index: devs/eth/powerpc/ec555/current/ChangeLog
===================================================================
RCS file: devs/eth/powerpc/ec555/current/ChangeLog
diff -N devs/eth/powerpc/ec555/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/ec555/current/ChangeLog 24 Nov 2003 14:25:50 -0000
@@ -0,0 +1,39 @@
+2003-11-05 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * include/devs_eth_powerpc_ec555.inl:
+ * cdl/ec555_eth_drivers.cdl: New package - support on PowerPC EC555
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/eth/powerpc/ec555/current/cdl/ec555_eth_drivers.cdl
===================================================================
RCS file: devs/eth/powerpc/ec555/current/cdl/ec555_eth_drivers.cdl
diff -N devs/eth/powerpc/ec555/current/cdl/ec555_eth_drivers.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/ec555/current/cdl/ec555_eth_drivers.cdl 5 Nov 2003 21:01:58 -0000
@@ -0,0 +1,149 @@
+# ====================================================================
+#
+# ec555_eth_drivers.cdl
+#
+# Ethernet drivers - platform dependent support for ether555 on ec555
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Bob Koninckx
+# Contributors: Bob Koninckx
+# Date: 2002-11-20
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_POWERPC_EC555 {
+ display "Crystal LAN ethernet driver for ec555 boards"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_POWERPC_EC555
+
+ implements CYGINT_DEVS_ETH_CL_CS8900A_REQUIRED
+ implements CYGINT_DEVS_ETH_CL_CS8900A_STATIC_ESA
+
+ requires CYGPKG_DEVS_ETH_CL_CS8900A
+
+ include_dir cyg/io
+
+ description "Ethernet driver for Crystal LAN based ether555 ethernet card for ec555"
+
+ # FIXME: This really belongs in the CL CS8900A package
+ cdl_interface CYGINT_DEVS_ETH_CL_CS8900A_REQUIRED {
+ display "CS8900A ethernet driver required"
+ }
+
+ define_proc {
+ puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_CL_CS8900A_INL <cyg/io/devs_eth_powerpc_ec555.inl>"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_CL_CS8900A_CFG <pkgconf/devs_eth_powerpc_ec555.h>"
+ puts $::cdl_system_header "/***** ethernet driver proc output end *****/"
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_POWERPC_EC555_ETH0 {
+ display "ec555 ethernet port driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the ethernet device driver for the
+ ec555 port."
+
+ implements CYGHWR_NET_DRIVER_ETH0
+ implements CYGINT_DEVS_ETH_CL_CS8900A_REQUIRED
+ implements CYGINT_DEVS_ETH_CL_CS8900A_STATIC_ESA
+
+ cdl_option CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME {
+ display "Device name for the ETH0 ethernet driver"
+ flavor data
+ default_value {"\"eth0\""}
+ description "
+ This option sets the name of the ethernet device."
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS {
+ display "Memory bank (CS2 / CS3) to use for accessing the device"
+ flavor data
+ default_value 2
+ legal_values 2 to 3
+ description "
+ This option controls which memory controller will be set up for access to
+ the ethernet card. The choise must correspond to the position of jumper
+ X3 on the device"
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_BASE {
+ display "Base address to use for accessing the device"
+ flavor data
+ default_value 0xd0000000
+ description "
+ This option determines the base address to use for the memory controller.
+ Make sure that it does not conflict with aother settings. Leaving it to the
+ default should be ok"
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_IRQ {
+ display "Interrupt line on the ec555 to use"
+ flavor data
+ default_value 4
+ legal_values 4 to 7
+ description "
+ This option determines which interrupt line of the ec555 will be used by the
+ device. The choise must match the position of jumper X2."
+ }
+
+ cdl_component CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA {
+ display "Set the ethernet station address"
+ flavor bool
+ calculated 0
+ description "Enabling this option will allow the ethernet
+ station address to be forced to the value set by the
+ configuration. This may be required if the hardware does
+ not include a serial EEPROM for the ESA."
+
+ cdl_option CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_ESA {
+ display "The ethernet station address"
+ flavor data
+ default_value {"{0x08, 0x88, 0x12, 0x34, 0x56, 0x78}"}
+ description "The ethernet station address"
+ }
+ }
+ }
+
+}
+
Index: devs/eth/powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl
===================================================================
RCS file: devs/eth/powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl
diff -N devs/eth/powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/eth/powerpc/ec555/current/include/devs_eth_powerpc_ec555.inl 5 Nov 2003 21:01:58 -0000
@@ -0,0 +1,246 @@
+//==========================================================================
+//
+// devs_eth_powerpc_ec555.inl
+//
+// ec555 ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Bob Koninckx
+// Contributors:Bob Koninckx
+// Date: 2002-11-20
+// Purpose: ec555 ethernet defintions
+//
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_if.h>
+
+#ifdef CYGPKG_REDBOOT
+# include <pkgconf/redboot.h>
+# ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+# include <redboot.h>
+# include <flash_config.h>
+# endif
+#endif
+
+#ifdef __WANT_CONFIG
+# define CS8900A_step 2
+#endif
+
+#ifdef __WANT_DEVS
+
+#ifdef CYGPKG_DEVS_ETH_POWERPC_EC555_ETH0
+
+#ifndef CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
+# if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
+RedBoot_config_option("Set " CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME " network hardware address [MAC]",
+ eth0_esa,
+ ALWAYS_ENABLED, true,
+ CONFIG_BOOL, false
+ );
+RedBoot_config_option(CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME " network hardware address [MAC]",
+ eth0_esa_data,
+ "eth0_esa", true,
+ CONFIG_ESA, 0
+ );
+# endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
+
+# ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+// Note that this section *is* active in an application, outside RedBoot,
+// where the above section is not included.
+
+# include <cyg/hal/hal_if.h>
+
+# ifndef CONFIG_ESA
+# define CONFIG_ESA (6)
+# endif
+# ifndef CONFIG_BOOL
+# define CONFIG_BOOL (1)
+# endif
+
+cyg_bool
+_ec555_provide_eth0_esa(struct cs8900a_priv_data* cpd)
+{
+ cyg_bool set_esa;
+ int ok;
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "eth0_esa", &set_esa, CONFIG_BOOL);
+ if (ok && set_esa) {
+ ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
+ "eth0_esa_data", cpd->esa, CONFIG_ESA);
+ }
+ return ok && set_esa;
+}
+
+# endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+#endif // ! CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
+
+// ------------------------------------------------------------------------
+// EEPROM access functions
+// These are byte swapped
+#define PP_ECR 0x4000
+#define PP_EE_READ_CMD 0x0002
+#define PP_EE_WRITE_CMD 0x0001
+#define PP_EE_DATA 0x4200
+
+#define PP_EE_ADDR_W0 0x001C // Notice that the EEPROM is not programmed when you got the
+#define PP_EE_ADDR_W1 0x001D // Module from Wuerz. Make sure to program the address to these
+#define PP_EE_ADDR_W2 0x001E // locations before using the adapter. This is fairly easy using GDB
+
+// The example below programs the MAC address aa bb cc dd ee ff to the eeprom, supposed that the module
+// is mapped to adresses 0xd000 0000
+//
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x3000 erase/write enable
+// set *(unsigned short *)0xd000030a = 0x4200 select eeprom data
+// set *(unsigned short *)0xd000030c = 0xaabb write data
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x1c01 write to offset 1c
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x0000 erase/write disable
+
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x3000 erase/write enable
+// set *(unsigned short *)0xd000030a = 0x4200 select eeprom data
+// set *(unsigned short *)0xd000030c = 0xccdd write data
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x1d01 write to offset 1d
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x0000 erase/write disable
+
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x3000 erase/write enable
+// set *(unsigned short *)0xd000030a = 0x4200 select eeprom data
+// set *(unsigned short *)0xd000030c = 0xeeff write data
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x1e01 write to offset 1c
+// set *(unsigned short *)0xd000030a = 0x4000 select eeprom command
+// set *(unsigned short *)0xd000030c = 0x0000 erase/write disable
+
+static __inline__ cyg_uint16
+read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
+{
+ while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
+ ;
+
+ // Swap the offset, this is a BIG-ENDIAN machine
+ put_reg(base, PP_ECR, (CYG_SWAP16(offset) | PP_EE_READ_CMD));
+
+ while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
+ ;
+
+ return get_reg(base, PP_EE_DATA);
+}
+
+static __inline__ void
+copy_eeprom(cyg_addrword_t base)
+{
+ volatile cyg_uint16 esa_word;
+ cyg_uint16 i;
+ for (i = 0; i < 6; i += 2)
+ { // Offset in the eeprom is WORD oriented, in the packetpage BYTE oriented
+ esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
+ put_reg(base, (PP_IA + CYG_SWAP16(i)), esa_word);
+ }
+}
+
+// Not so nice, but reading these will never conflict on the ec555
+// They certainly differ in A18
+#define FIRSTRAM 0x00400000
+#define LASTRAM 0x004ffffe
+
+static __inline__ void
+post_reset(cyg_addrword_t base)
+{
+ cyg_uint16 tmp;
+
+ // The following must toggle Address line 18, connected to SBHE on the CS8900a
+ HAL_READ_UINT16( LASTRAM, tmp);
+ HAL_READ_UINT16( FIRSTRAM, tmp);
+ HAL_READ_UINT16( LASTRAM, tmp);
+ HAL_READ_UINT16( FIRSTRAM, tmp);
+}
+
+#undef CYGHWR_CL_CS8900A_PLF_POST_RESET
+#define CYGHWR_CL_CS8900A_PLF_POST_RESET(base) post_reset(base)
+
+#undef CYGHWR_CL_CS8900A_PLF_RESET
+#define CYGHWR_CL_CS8900A_PLF_RESET(base) copy_eeprom(base)
+
+static cs8900a_priv_data_t cs8900a_eth0_priv_data = {
+ base : (cyg_addrword_t) (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_BASE + 0x300),
+ interrupt:((CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_IRQ*2)+1),
+#ifdef CYGSEM_DEVS_ETH_POWERPC_EC555_ETH0_SET_ESA
+ esa : CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_ESA,
+ hardwired_esa : true,
+#else
+ hardwired_esa : false,
+# ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+ provide_esa : &_ec555_provide_eth0_esa,
+# else
+ provide_esa : NULL,
+# endif
+#endif
+
+};
+
+
+ETH_DRV_SC(cs8900a_sc,
+ &cs8900a_eth0_priv_data, // Driver specific data
+ CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME,
+ cs8900a_start,
+ cs8900a_stop,
+ cs8900a_control,
+ cs8900a_can_send,
+ cs8900a_send,
+ cs8900a_recv,
+ cs8900a_deliver, // "pseudoDSR" called from fast net thread
+ cs8900a_poll, // poll function, encapsulates ISR and DSR
+ cs8900a_int_vector);
+
+NETDEVTAB_ENTRY(cs8900a_netdev,
+ "cs8900a_" CYGDAT_DEVS_ETH_POWERPC_EC555_ETH0_NAME,
+ cs8900a_init,
+ &cs8900a_sc);
+
+#endif // CYGPKG_DEVS_ETH_POWERPC_EC555_ETH0
+
+#endif // __WANT_DEVS
+
+// EOF devs_eth_powerpc_ec555.inl
Index: devs/flash/amd/am29xxxxx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/amd/am29xxxxx/current/ChangeLog,v
retrieving revision 1.28
diff -u -5 -p -r1.28 ChangeLog
--- devs/flash/amd/am29xxxxx/current/ChangeLog 21 Oct 2003 22:36:00 -0000 1.28
+++ devs/flash/amd/am29xxxxx/current/ChangeLog 5 Nov 2003 20:46:45 -0000
@@ -1,19 +1,19 @@
2003-10-21 Jay Foster <jay@systech.com>
* include/flash_am29xxxxx_parts.inl (CYGHWR_DEVS_FLASH_AMD_AM29LV033C):
- Fixed device definition to allow erasing of the upper half of the
- device. The Sector Protect Verify command would erroneously report
- the upper half of the device as locked.
+ Fixed device definition to allow erasing of the upper half of the
+ device. The Sector Protect Verify command would erroneously report
+ the upper half of the device as locked.
2003-10-02 Jay Foster <jay@systech.com>
* include/flash_am29xxxxx_parts.inl (CYGHWR_DEVS_FLASH_AMD_AM29LV081B,
- CYGHWR_DEVS_FLASH_AMD_AM29LV017D, CYGHWR_DEVS_FLASH_AMD_AM29LV033C,
- CYGHWR_DEVS_FLASH_AMD_AM29LV065D):
+ CYGHWR_DEVS_FLASH_AMD_AM29LV017D, CYGHWR_DEVS_FLASH_AMD_AM29LV033C,
+ CYGHWR_DEVS_FLASH_AMD_AM29LV065D):
* cdl/flash_amd_am29xxxxx.cdl: Add support for Am29LV081B, Am29LV017D,
- Am29LV033C, and Am29LV065D parts.
+ Am29LV033C, and Am29LV065D parts.
2003-09-09 Thomas Koeller <thomas.koeller@baslerweb.com>
* include/flash_am29xxxxx.inl:
* include/flash_am29xxxxx_parts.inl: Added support for write
@@ -67,10 +67,15 @@
* include/flash_am29xxxxx_parts.inl (CYGHWR_DEVS_FLASH_AMD_AM29DL640D):
Now tested in 16 bit configurations.
* include/flash_am29xxxxx.inl: Fix problems with CYGNUM_FLASH_16AS8.
The definition was inconsistent/confusing.
+
+2002-11-17 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * include/flash_am29xxxxx_parts.inl:
+ * cdl/flash_am29xxxxx.cdl: Definition for AM29F010 part added. Used by cme555.
2002-10-11 Gary Thomas <gary@mlbassoc.com>
* include/flash_am29xxxxx_parts.inl:
* include/flash_am29xxxxx.inl: Better support for devices with
Index: devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl,v
retrieving revision 1.16
diff -u -5 -p -r1.16 flash_amd_am29xxxxx.cdl
--- devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl 20 Oct 2003 17:37:36 -0000 1.16
+++ devs/flash/amd/am29xxxxx/current/cdl/flash_amd_am29xxxxx.cdl 5 Nov 2003 20:45:03 -0000
@@ -65,10 +65,20 @@ cdl_package CYGPKG_DEVS_FLASH_AMD_AM29XX
cdl_interface CYGINT_DEVS_FLASH_AMD_VARIANTS {
display "Number of included variants"
}
+ cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F010 {
+ display "AMD AM29F010 flash memory support"
+ default_value 0
+ implements CYGINT_DEVS_FLASH_AMD_VARIANTS
+ description "
+ When this option is enabled, the AMD flash driver will be
+ able to recognize and handle the AMD29F010
+ part in the family."
+ }
+
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F040B {
display "AMD AM29F040B flash memory support"
default_value 0
implements CYGINT_DEVS_FLASH_AMD_VARIANTS
description "
Index: devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl,v
retrieving revision 1.19
diff -u -5 -p -r1.19 flash_am29xxxxx_parts.inl
--- devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 21 Oct 2003 22:36:00 -0000 1.19
+++ devs/flash/amd/am29xxxxx/current/include/flash_am29xxxxx_parts.inl 5 Nov 2003 20:45:03 -0000
@@ -78,10 +78,21 @@
// should be 16 blocks.
//
#define _LAST_BOOTBLOCK (-1)
#if CYGNUM_FLASH_WIDTH == 8
+#ifdef CYGHWR_DEVS_FLASH_AMD_AM29F010
+ { // AM29F010
+ device_id : FLASHWORD(0x20),
+ block_size : 0x4000 * CYGNUM_FLASH_INTERLEAVE,
+ block_count: 8,
+ device_size: 0x20000 * CYGNUM_FLASH_INTERLEAVE,
+ base_mask : ~(0x20000 * CYGNUM_FLASH_INTERLEAVE - 1),
+ bootblock : false,
+ banked : false
+ },
+#endif
#ifdef CYGHWR_DEVS_FLASH_AMD_AM29F040B
{ // AM29F040B
device_id : FLASHWORD(0xa4),
block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
block_count: 8,
Index: devs/serial/powerpc/cme555/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/cme555/current/ChangeLog,v
retrieving revision 1.3
diff -u -5 -p -r1.3 ChangeLog
--- devs/serial/powerpc/cme555/current/ChangeLog 24 Feb 2003 14:18:18 -0000 1.3
+++ devs/serial/powerpc/cme555/current/ChangeLog 5 Nov 2003 20:48:57 -0000
@@ -1,9 +1,14 @@
2003-02-24 Jonathan Larmour <jifl@eCosCentric.com>
* cdl/ser_powerpc_cme555.cdl: Remove irrelevant doc link.
+2002-11-11 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * src/cme555_serial_with_ints.c:
+ interrupt arbiter slightly modified to make GDB CTRL-C work
+
2002-04-24 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
* New package.
//===========================================================================
Index: devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 cme555_serial_with_ints.c
--- devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c 23 May 2002 23:01:22 -0000 1.2
+++ devs/serial/powerpc/cme555/current/src/cme555_serial_with_ints.c 5 Nov 2003 20:47:56 -0000
@@ -205,40 +205,42 @@ DEVTAB_ENTRY(mpc555_serial_io1,
//-----------------------------
// The arbitration isr.
// I think this is the best place to implement it. The device driver is the only place
// in the code where the knowledge is present about how the hardware is used
+//
+// Always check receive interrupts. Some rom monitor might be waiting for CTRL-C
static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, CYG_ADDRWORD a_data)
{
cyg_uint16 status;
cyg_uint16 control;
-#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A // Do not waist time on unused hardware
HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status);
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control);
+ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
+ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
+#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_A // Do not waist time on unused hardware
if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE))
return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC);
- if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
- return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE);
#endif
-#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B // Do not waist time on unused hardware
HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status);
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control);
+ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
+ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
+#ifdef CYGPKG_IO_SERIAL_POWERPC_CME555_SERIAL_B // Do not waist time on unused hardware
if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE))
return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC);
- if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
- return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE);
#if 0
@@ -413,11 +415,11 @@ static bool mpc555_serial_init(struct cy
arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI;
arbiter.data = 0;
arbiter.arbiter = hal_arbitration_isr_qsci;
// Install the arbitration isr, Make sure that is is not installed twice
- hal_mpc5xx_remove_arbitration_isr(&arbiter);
+ hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
hal_mpc5xx_install_arbitration_isr(&arbiter);
// Create the Tx interrupt, do not enable it yet
cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_num,
mpc555_chan->tx_interrupt_priority,
Index: devs/serial/powerpc/ec555/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/ec555/current/ChangeLog,v
retrieving revision 1.3
diff -u -5 -p -r1.3 ChangeLog
--- devs/serial/powerpc/ec555/current/ChangeLog 24 Feb 2003 14:18:41 -0000 1.3
+++ devs/serial/powerpc/ec555/current/ChangeLog 5 Nov 2003 20:49:22 -0000
@@ -1,9 +1,14 @@
2003-02-24 Jonathan Larmour <jifl@eCosCentric.com>
* cdl/ser_powerpc_ec555.cdl: Remove irrelevant doc link.
+2002-11-11 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * src/ec555_serial_with_ints:
+ arbiter slightly modified to make GDB-CTRLC work.
+
2002-04-24 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
* New package.
//===========================================================================
Index: devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 ec555_serial_with_ints.c
--- devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c 23 May 2002 23:01:22 -0000 1.2
+++ devs/serial/powerpc/ec555/current/src/ec555_serial_with_ints.c 5 Nov 2003 20:47:56 -0000
@@ -205,40 +205,44 @@ DEVTAB_ENTRY(mpc555_serial_io1,
//-----------------------------
// The arbitration isr.
// I think this is the best place to implement it. The device driver is the only place
// in the code where the knowledge is present about how the hardware is used
+//
+// Always check receiver interrupts. Some rom monitor might be listening to CTRL-C
static cyg_uint32 hal_arbitration_isr_qsci(CYG_ADDRWORD a_vector, CYG_ADDRWORD a_data)
{
cyg_uint16 status;
cyg_uint16 control;
-#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A // Do not waist time on unused hardware
HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, status);
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, control);
+ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
+ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
+
+#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_A // Do not waist time on unused hardware
if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE))
return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC);
- if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
- return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE);
#endif
-#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B // Do not waist time on unused hardware
HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, status);
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, control);
+ if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
+ return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
+
+#ifdef CYGPKG_IO_SERIAL_POWERPC_EC555_SERIAL_B // Do not waist time on unused hardware
if((status & CYGARC_REG_IMM_SCxSR_TDRE) && (control & CYGARC_REG_IMM_SCCxR1_TIE))
return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_TC) && (control & CYGARC_REG_IMM_SCCxR1_TCIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC);
- if((status & CYGARC_REG_IMM_SCxSR_RDRF) && (control & CYGARC_REG_IMM_SCCxR1_RIE))
- return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
// Don't waist time on unused interrupts
// if((status & CYGARC_REG_IMM_SCxSR_IDLE) && (control & CYGARC_REG_IMM_SCCxR1_ILIE))
// return hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE);
#if 0
@@ -413,11 +417,11 @@ static bool mpc555_serial_init(struct cy
arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI;
arbiter.data = 0;
arbiter.arbiter = hal_arbitration_isr_qsci;
// Install the arbitration isr, Make sure that is is not installed twice
- hal_mpc5xx_remove_arbitration_isr(&arbiter);
+ hal_mpc5xx_remove_arbitration_isr(CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
hal_mpc5xx_install_arbitration_isr(&arbiter);
// Create the Tx interrupt, do not enable it yet
cyg_drv_interrupt_create(mpc555_chan->tx_interrupt_num,
mpc555_chan->tx_interrupt_priority,
Index: devs/watchdog/powerpc/mpc5xx/current/ChangeLog
===================================================================
RCS file: devs/watchdog/powerpc/mpc5xx/current/ChangeLog
diff -N devs/watchdog/powerpc/mpc5xx/current/ChangeLog
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/watchdog/powerpc/mpc5xx/current/ChangeLog 5 Nov 2003 20:50:37 -0000
@@ -0,0 +1,37 @@
+
+2003-05-25 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * new package
+
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
Index: devs/watchdog/powerpc/mpc5xx/current/cdl/watchdog_mpc5xx.cdl
===================================================================
RCS file: devs/watchdog/powerpc/mpc5xx/current/cdl/watchdog_mpc5xx.cdl
diff -N devs/watchdog/powerpc/mpc5xx/current/cdl/watchdog_mpc5xx.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/watchdog/powerpc/mpc5xx/current/cdl/watchdog_mpc5xx.cdl 5 Nov 2003 20:50:37 -0000
@@ -0,0 +1,122 @@
+# ====================================================================
+#
+# watchdog_mpc5xx.cdl
+#
+# eCos watchdog for powerpc/mpc5xx driver configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Bob Koninckx
+# Contributors: Bob Koninckx
+# Date: 2003-05-19
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVICES_WATCHDOG_MPC5xx {
+ parent CYGPKG_IO_WATCHDOG
+ active_if CYGPKG_IO_WATCHDOG
+ display "mpc5xx watchdog driver"
+ requires CYGPKG_HAL_POWERPC_MPC5xx
+ hardware
+ compile watchdog_mpc5xx.cxx
+ implements CYGINT_WATCHDOG_HW_IMPLEMENTATIONS
+ implements CYGINT_WATCHDOG_RESETS_ON_TIMEOUT
+ active_if CYGIMP_WATCHDOG_HARDWARE
+
+ cdl_option CYGIMP_WATCHDOG_HARDWARE {
+ parent CYGPKG_IO_WATCHDOG_IMPLEMENTATION
+ display "Hardware watchdog"
+ default_value 1
+ implements CYGINT_WATCHDOG_IMPLEMENTATIONS
+ }
+
+ cdl_option CYGNUM_DEVICES_WATCHDOG_POWERPC_MPC5XX_RELOAD {
+ display "mpc5xx watchog reload value"
+ flavor data
+ default_value 0xffff
+ legal_values 0 to 0xffff
+ description "
+ This option determines the number of ticks before the watchdog
+ times out and resets the board. The watchdog is timed from the
+ same clock source as the Periodic interrupt timer (PIT), but
+ can be additionaly prescaled by a factor 2048."
+ }
+
+ cdl_option CYGDAT_DEVICES_WATCHDOG_POWERPC_MPC5XX_PRESCALE {
+ display "mpc5xx watchdog prescaler"
+ flavor bool
+ default_value 1
+ description "
+ This option determines wether to prescale the watchdog timer with
+ a factor 2048 or not."
+ }
+
+ cdl_component CYGPKG_DEVICES_WATCHDOG_POWERPC_MPC5XX_OPTIONS {
+ display "mpc5xx watchdog build options"
+ flavor none
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+
+ cdl_option CYGPKG_DEVICES_WATCHDOG_POWERPC_MPC5XX_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the watchdog device. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_DEVICES_WATCHDOG_POWERPC_MPC5XXX_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the watchdog device. These flags are removed from
+ the set of global flags if present."
+ }
+
+ }
+}
Index: devs/watchdog/powerpc/mpc5xx/current/src/watchdog_mpc5xx.cxx
===================================================================
RCS file: devs/watchdog/powerpc/mpc5xx/current/src/watchdog_mpc5xx.cxx
diff -N devs/watchdog/powerpc/mpc5xx/current/src/watchdog_mpc5xx.cxx
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ devs/watchdog/powerpc/mpc5xx/current/src/watchdog_mpc5xx.cxx 5 Nov 2003 20:50:37 -0000
@@ -0,0 +1,127 @@
+//==========================================================================
+//
+// devs/watchdog/powerpc/mpc5xx/watchdog_mpc5xx.cxx
+//
+// Watchdog implementation for MPC5XX
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Bob Koninckx
+// Contributors: Bob Koninckx
+// Date: 2003-05-18
+// Purpose: Watchdog class implementation
+// Description: Contains an implementation of the Watchdog class for use
+// with the mpc5xx watchdog timer.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h> // system configuration file
+#include <pkgconf/watchdog.h> // configuration for this package
+
+#include <cyg/infra/cyg_trac.h> // tracing macros
+
+#include <cyg/hal/hal_io.h> // IO register access
+#include <cyg/hal/hal_arch.h> // Register definitions
+
+#include <cyg/io/watchdog.hxx> // watchdog API
+
+// -------------------------------------------------------------------------
+// MPC5xx SYPCR register bit definitions
+#define MPC5XX_SYPCR_SWTC 0xffff0000
+#define MPC5XX_SYPCR_SWP 0x00000001
+#define MPC5XX_SYPCR_SWRI 0x00000002
+#define MPC5XX_SYPCR_SWE 0x00000004
+#define MPC5XX_SYPCR_SWF 0x00000008
+
+// -------------------------------------------------------------------------
+// Constructor
+
+void
+Cyg_Watchdog::init_hw(void)
+{
+ CYG_REPORT_FUNCTION();
+
+ cyg_uint32 sypcr;
+ HAL_READ_UINT32(CYGARC_REG_IMM_SYPCR, sypcr);
+
+ resolution = (sypcr & MPC5XX_SYPCR_SWTC) >> 16;
+ if(sypcr & MPC5XX_SYPCR_SWP)
+ resolution *= 2048;
+
+ // Now we have it in ticks, convert to nanoseconds
+ // This holds for a system clock of 40 Mhz (25 nanosecond ticks) which is normal
+ // for the MPC5xx
+ resolution *= 25;
+
+ CYG_REPORT_RETURN();
+}
+
+// -------------------------------------------------------------------------
+// Start the watchdog running.
+// On powerpc, the watchdog is enabled by default. If the watchdog package
+// is present, board setup does not disable it, so, nothing special to be
+// done here.
+void
+Cyg_Watchdog::start(void)
+{
+ CYG_REPORT_FUNCTION();
+
+ CYG_REPORT_RETURN();
+}
+
+// -------------------------------------------------------------------------
+// Reset watchdog timer. This needs to be called regularly to prevent
+// the watchdog firing.
+
+void
+Cyg_Watchdog::reset()
+{
+ CYG_REPORT_FUNCTION();
+
+ cyg_uint16 swsr;
+ swsr = 0x556c;
+ HAL_WRITE_UINT16(CYGARC_REG_IMM_SWSR, swsr);
+ swsr = 0xaa39;
+ HAL_WRITE_UINT16(CYGARC_REG_IMM_SWSR, swsr);
+
+ CYG_REPORT_RETURN();
+}
+
+// -------------------------------------------------------------------------
+// EOF watchdog_mpc5xx.cxx
Index: hal/powerpc/arch/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/ChangeLog,v
retrieving revision 1.54
diff -u -5 -p -r1.54 ChangeLog
--- hal/powerpc/arch/current/ChangeLog 28 Oct 2003 08:47:50 -0000 1.54
+++ hal/powerpc/arch/current/ChangeLog 5 Nov 2003 21:20:04 -0000
@@ -69,10 +69,17 @@
2002-11-20 Gary Thomas <gary@mlbassoc.com>
* src/hal_mk_defs.c: Allow platforms to provide their own definitions.
+2002-11-14 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * include/hal_arch.h:
+ * include/ppc_stub.h:
+ * src/ppc_stub.c:
+ floating point support in GDB - definitions/implementation
+
2002-11-13 Gary Thomas <gthomas@ecoscentric.com>
* src/hal_misc.c (hal_enable_caches): Support new CDL options for
how [mode] to enable DATA cache.
Index: hal/powerpc/arch/current/include/hal_arch.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/include/hal_arch.h,v
retrieving revision 1.12
diff -u -5 -p -r1.12 hal_arch.h
--- hal/powerpc/arch/current/include/hal_arch.h 8 Mar 2003 03:39:19 -0000 1.12
+++ hal/powerpc/arch/current/include/hal_arch.h 5 Nov 2003 21:17:14 -0000
@@ -200,49 +200,108 @@ asm volatile (" .globl " #_label_ ";"
#define HAL_BREAKINST_SIZE 4
//-----------------------------------------------------------------------------
// Thread register state manipulation for GDB support.
+typedef struct {
+ cyg_uint32 gpr[32]; // General purpose registers
+ double f0[16]; // First sixteen floating point regs
+ cyg_uint32 pc;
+ cyg_uint32 msr;
+ cyg_uint32 cr;
+ cyg_uint32 lr;
+ cyg_uint32 ctr;
+ cyg_uint32 xer;
+ cyg_uint32 mq;
+#ifdef CYGHWR_HAL_POWERPC_FPU
+ double f16[16]; // Last sixteen floating point regs
+ // Could probably also be inserted in the middle
+ // Adding them at the end minimises the risk of
+ // breaking existing implementations that do not
+ // have floating point registers.
+#endif
+} GDB_Registers;
// Translate a stack pointer as saved by the thread context macros above into
// a pointer to a HAL_SavedRegisters structure.
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
(_regs_) = (HAL_SavedRegisters *)(_sp_)
+// Copy floating point registers from a HAL_SavedRegisters structure into a
+// GDB_Registers structure
+#ifdef CYGHWR_HAL_POWERPC_FPU
+#define HAL_GET_GDB_FLOATING_POINT_REGISTERS( _gdb_, _regs_ ) \
+ CYG_MACRO_START \
+ double * _p_ = _gdb_->f0; \
+ double * _q_ = _regs_->f; \
+ for( _i_ = 0; _i_ < 16; _i_++) \
+ *_p_++ = *_q_++; \
+ \
+ _p_ = _gdb_->f16; \
+ for( _i_ = 0; _i_ < 16; _i_++) \
+ *_p_++ = *_q_++; \
+ CYG_MACRO_END
+#else
+#define HAL_GET_GDB_FLOATING_POINT_REGISTERS( _gdb_, _regs_ ) \
+ CYG_MACRO_START \
+ CYG_MACRO_END
+#endif
+
+// Copy a GDB_Registers structure into a HAL_SavedRegisters structure
+#ifdef CYGHWR_HAL_POWERPC_FPU
+#define HAL_SET_GDB_FLOATING_POINT_REGISTERS( _regs_, _gdb_) \
+ CYG_MACRO_START \
+ double * _p_ = _regs_->f; \
+ double * _q_ = _gdb_->f0; \
+ for( _i_ = 0; _i_ < 16; _i_++) \
+ *_p_++ = *_q_++; \
+ \
+ _q_ = _gdb_->f16; \
+ for( _i_ = 0; _i_ < 16; _i_++) \
+ *_p_++ = *_q_++; \
+ CYG_MACRO_END
+#else
+#define HAL_SET_GDB_FLOATING_POINT_REGISTERS( _regs_, _gdb_) \
+ CYG_MACRO_START \
+ CYG_MACRO_END
+#endif
+
// Copy a set of registers from a HAL_SavedRegisters structure into a
// GDB ordered array.
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
CYG_MACRO_START \
- CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
+ GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 32; _i_++ ) \
- _regval_[_i_] = (_regs_)->d[_i_]; \
+ _gdb_->gpr[_i_] = (_regs_)->d[_i_]; \
\
- _regval_[64] = (_regs_)->pc; \
- _regval_[65] = (_regs_)->msr; \
- _regval_[66] = (_regs_)->cr; \
- _regval_[67] = (_regs_)->lr; \
- _regval_[68] = (_regs_)->ctr; \
- _regval_[69] = (_regs_)->xer; \
+ _gdb_->pc = (_regs_)->pc; \
+ _gdb_->msr = (_regs_)->msr; \
+ _gdb_->cr = (_regs_)->cr; \
+ _gdb_->lr = (_regs_)->lr; \
+ _gdb_->ctr = (_regs_)->ctr; \
+ _gdb_->xer = (_regs_)->xer; \
+ HAL_GET_GDB_FLOATING_POINT_REGISTERS(_gdb_, _regs_); \
CYG_MACRO_END
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
CYG_MACRO_START \
- CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
+ GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 32; _i_++ ) \
- (_regs_)->d[_i_] = _regval_[_i_]; \
+ (_regs_)->d[_i_] = _gdb_->gpr[_i_]; \
\
- (_regs_)->pc = _regval_[64]; \
- (_regs_)->msr = _regval_[65]; \
- (_regs_)->cr = _regval_[66]; \
- (_regs_)->lr = _regval_[67]; \
- (_regs_)->ctr = _regval_[68]; \
- (_regs_)->xer = _regval_[69]; \
+ (_regs_)->pc = _gdb_->pc; \
+ (_regs_)->msr = _gdb_->msr; \
+ (_regs_)->cr = _gdb_->cr; \
+ (_regs_)->lr = _gdb_->lr; \
+ (_regs_)->ctr = _gdb_->ctr; \
+ (_regs_)->xer = _gdb_->xer; \
+ HAL_SET_GDB_FLOATING_POINT_REGISTERS(_regs_, _gdb_); \
CYG_MACRO_END
//-----------------------------------------------------------------------------
// HAL setjmp
Index: hal/powerpc/arch/current/include/ppc_stub.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/include/ppc_stub.h,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ppc_stub.h
--- hal/powerpc/arch/current/include/ppc_stub.h 23 May 2002 23:04:13 -0000 1.7
+++ hal/powerpc/arch/current/include/ppc_stub.h 5 Nov 2003 21:17:14 -0000
@@ -55,15 +55,29 @@
#ifdef __cplusplus
extern "C" {
#endif
+typedef unsigned long target_register_t;
+
#define NUMREGS 71
+
+#ifdef CYGHWR_HAL_POWERPC_FPU
+// The PowerPC has floating point registers that are larger than what it
+// can hold in a target_register_t
+#define TARGET_HAS_LARGE_REGISTERS
+// PowerPC stub has special needs for register handling because flating point
+// registers are bigger than the rest. Special put_register and get_register
+// are provided
+#define CYGARC_STUB_REGISTER_ACCESS_DEFINED 1
+
+// extra space needed for floating point registers
+#define HAL_STUB_REGISTERS_SIZE ((sizeof(GDB_Registers) + sizeof(target_register_t) - 1)/sizeof(target_register_t))
+#endif
+
#define REGSIZE( _x_ ) (((_x_) >= F0 && (_x_) <= F31) ? 8 : 4)
-
-typedef unsigned long target_register_t;
enum regnames {
R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
R16, R17, R18, R19, R20, R21, R22, R23,
Index: hal/powerpc/arch/current/src/ppc_stub.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/arch/current/src/ppc_stub.c,v
retrieving revision 1.11
diff -u -5 -p -r1.11 ppc_stub.c
--- hal/powerpc/arch/current/src/ppc_stub.c 23 May 2002 23:04:14 -0000 1.11
+++ hal/powerpc/arch/current/src/ppc_stub.c 5 Nov 2003 21:17:14 -0000
@@ -70,10 +70,14 @@
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id
#endif
+#ifndef OFFSETOF
+#define OFFSETOF(_struct_, _member_) (int)((char *)(&(((_struct_*)0)->_member_))-(char *)((_struct_*)0))
+#endif
+
/* Given a trap value TRAP, return the corresponding signal. */
int __computeSignal (unsigned int trap_number)
{
switch (trap_number)
@@ -196,10 +200,92 @@ int __get_trap_number (void)
void set_pc (target_register_t pc)
{
put_register (PC, pc);
}
+#ifdef CYGHWR_HAL_POWERPC_FPU
+static int
+reg_offset(regnames_t reg)
+{
+ // We let the compiler determine the offsets in order to avoid all
+ // possible alignment problems
+ int base_offset;
+ // 32 general purpose registers
+ if(reg < F0) return reg * 4;
+
+ // first sixteen floating point regs
+ base_offset = OFFSETOF(GDB_Registers, f0);
+ if(reg < F16) return base_offset + ((reg - F0) * 8);
+
+ // last sixteen floating point regs
+ base_offset = OFFSETOF(GDB_Registers, f16);
+ if(reg < PC) return base_offset + ((reg - F16) * 8);
+
+ // Other 32 bit regs
+ if(reg < PS) return(OFFSETOF(GDB_Registers, pc));
+ if(reg < CND) return(OFFSETOF(GDB_Registers, msr));
+ if(reg < LR) return(OFFSETOF(GDB_Registers, cr));
+ if(reg < CNT) return(OFFSETOF(GDB_Registers, lr));
+ if(reg < XER) return(OFFSETOF(GDB_Registers, ctr));
+ if(reg < MQ) return(OFFSETOF(GDB_Registers, xer));
+
+ return OFFSETOF(GDB_Registers, mq);
+}
+
+// Return the currently-saved value corresponding to register REG of
+// the exception context.
+target_register_t
+get_register (regnames_t reg)
+{
+ target_register_t val;
+ int offset = reg_offset(reg);
+
+ if (REGSIZE(reg) > sizeof(target_register_t))
+ return -1;
+
+ val = _registers[offset/sizeof(target_register_t)];
+
+ return val;
+}
+
+// Store VALUE in the register corresponding to WHICH in the exception
+// context.
+void
+put_register (regnames_t which, target_register_t value)
+{
+ int offset = reg_offset(which);
+
+ if (REGSIZE(which) > sizeof(target_register_t))
+ return;
+
+ _registers[offset/sizeof(target_register_t)] = value;
+}
+
+// Write the contents of register WHICH into VALUE as raw bytes. This
+// is only used for registers larger than sizeof(target_register_t).
+// Return non-zero if it is a valid register.
+int
+get_register_as_bytes (regnames_t which, char *value)
+{
+ int offset = reg_offset(which);
+
+ memcpy (value, (char *)_registers + offset, REGSIZE(which));
+ return 1;
+}
+
+// Alter the contents of saved register WHICH to contain VALUE. This
+// is only used for registers larger than sizeof(target_register_t).
+// Return non-zero if it is a valid register.
+int
+put_register_as_bytes (regnames_t which, char *value)
+{
+ int offset = reg_offset(which);
+
+ memcpy ((char *)_registers + offset, value, REGSIZE(which));
+ return 1;
+}
+#endif
/*----------------------------------------------------------------------
* Single-step support
*/
Index: hal/powerpc/ec555/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ec555/current/ChangeLog,v
retrieving revision 1.5
diff -u -5 -p -r1.5 ChangeLog
--- hal/powerpc/ec555/current/ChangeLog 24 Jul 2003 20:24:07 -0000 1.5
+++ hal/powerpc/ec555/current/ChangeLog 5 Nov 2003 21:17:18 -0000
@@ -4,17 +4,26 @@
Changed values for CYGNUM_HAL_RTC_NUMERATOR,
CYGNUM_HAL_RTC_DENOMINATOR and CYGNUM_HAL_RTC_PERIOD to
"default_value" from "calculated". This makes it easier
to change these values globally.
+2003-05-25 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * include/plf_intr.h: Use the watchdog (if present) to reset the board
+
2003-03-07 Gary Thomas <gary@mlbassoc.com>
* include/plf_stub.h: Remove [confusing] platform specific include.
2003-02-10 Nick Garnett <nickg@calivar.com>
* misc/redboot_RAM.ecm: Brought up to date with ROM version.
+
+2002-11-11 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * src/ec555.S: Removed statements to disable processor serialization,
+ this is already done in the variant initialization code.
2002-05-13 Jesper Skov <jskov@redhat.com>
* cdl/hal_powerpc_ec555.cdl: Removed implemntation of
CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED.
Index: hal/powerpc/ec555/current/include/plf_intr.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ec555/current/include/plf_intr.h,v
retrieving revision 1.2
diff -u -5 -p -r1.2 plf_intr.h
--- hal/powerpc/ec555/current/include/plf_intr.h 23 May 2002 23:04:20 -0000 1.2
+++ hal/powerpc/ec555/current/include/plf_intr.h 5 Nov 2003 21:17:19 -0000
@@ -55,14 +55,24 @@
//
//####DESCRIPTIONEND####
//
//==========================================================================
+#include <pkgconf/system.h>
//----------------------------------------------------------------------------
// Reset.
+#ifdef CYGPKG_IO_WATCHDOG
+#define HAL_PLATFORM_RESET() \
+ { \
+ cyg_uint32 old_state; \
+ HAL_DISABLE_INTERRUPTS(old_state); \
+ while(1); \
+ }
+#else
#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
+#endif
#define HAL_PLATFORM_RESET_ENTRY 0x00000100
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
Index: hal/powerpc/ec555/current/src/ec555.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ec555/current/src/ec555.S,v
retrieving revision 1.2
diff -u -5 -p -r1.2 ec555.S
--- hal/powerpc/ec555/current/src/ec555.S 23 May 2002 23:04:20 -0000 1.2
+++ hal/powerpc/ec555/current/src/ec555.S 5 Nov 2003 21:17:19 -0000
@@ -54,23 +54,40 @@
#include <pkgconf/hal.h>
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/arch.inc>
+#include <pkgconf/system.h>
+#ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
+#include <pkgconf/devs_eth_powerpc_ec555.h>
+#endif
+
+## FIXME
+## The following probably belongs in the variant hal rather than the board specifics ...
+#ifdef CYGPKG_DEVICES_WATCHDOG_MPC5xx
+#include <pkgconf/devices_watchdog_mpc5xx.h>
+#define CYG_SYPCR 0x0000ff8d | (CYGNUM_DEVICES_WATCHDOG_POWERPC_MPC5XX_RELOAD << 16) | CYGDAT_DEVICES_WATCHDOG_POWERPC_MPC5XX_PRESCALE
+#else
+#define CYG_SYPCR 0x0000ff88
+#endif
+
#------------------------------------------------------------------------------
.globl hal_hardware_init
hal_hardware_init:
#if defined(CYGPKG_HAL_POWERPC_EC555) && defined(CYGPKG_HAL_POWERPC_MPC5xx)
lwi r3, CYGARC_REG_IMM_BASE # Base address of control registers
+#if defined(CYG_HAL_STARTUP_ROM)
// Burst enable
lwi r0, 0x00002000
mtspr 560, r0
- // Disable the Watchdog (for now)
- lwi r4, 0xffffff88
+ // FIXME
+ // The following probably belongs in the variant hal rather than the board specifics ...
+ // Disable / enable the Watchdog
+ lwi r4, CYG_SYPCR
stw r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0x00000000
stw r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3)
// Unlock locked registers
@@ -87,10 +104,11 @@ hal_hardware_init:
stw r4, (CYGARC_REG_IMM_PITCK-CYGARC_REG_IMM_BASE)(r3)
stw r4, (CYGARC_REG_IMM_SCCRK-CYGARC_REG_IMM_BASE)(r3)
stw r4, (CYGARC_REG_IMM_PLPRCRK-CYGARC_REG_IMM_BASE)(r3)
stw r4, (CYGARC_REG_IMM_RSRK-CYGARC_REG_IMM_BASE)(r3)
+ // Either Redboot or BDM will have already done it otherwise
// Boost the clock to 40MHz
lwi r4, 0x03000000
stw r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0x009150c0
stw r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3)
@@ -106,18 +124,41 @@ hal_hardware_init:
stw r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0x00400011
stw r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0xfff00000
stw r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3)
+#endif
+
+#ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
+
+ lwi r4, (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_BASE & 0xffff0000) | 0x00000803
+#if (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 2)
+ stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
+ lwi r4, 0xffff8e60
+ stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
+ lwi r4, 0
+ stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
+#elif (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 3)
+ stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
+ lwi r4, 0xffff8e60
+ stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
+ lwi r4, 0
+ stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
+#else
+#error "Invalid chip select for ethernet card specified"
+#endif
+
+#else
lwi r4, 0x00c00000
stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0xffff8000
stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0x00e00000
stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
lwi r4, 0xffff8000
stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
+#endif
#if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP)
lwi r4, 1
#else
lwi r4, 0
@@ -183,16 +224,10 @@ hal_hardware_init:
// Enable 32 interrupt priorities on the IMB3 unit
lwi r4, 0x60000000
lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE)
stwx r4, r3, r5
-
- // Finally, disable serialization
- // Motorola claims that failing to do so results in a performance
- // penalty of a facor three !!
- lwi r0, 0x00000007
- mtspr 158, r0
#endif
sync
blr
#------------------------------------------------------------------------------
Index: hal/powerpc/ec555/current/src/hal_diag.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/ec555/current/src/hal_diag.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 hal_diag.c
--- hal/powerpc/ec555/current/src/hal_diag.c 23 May 2002 23:04:20 -0000 1.2
+++ hal/powerpc/ec555/current/src/hal_diag.c 5 Nov 2003 21:17:19 -0000
@@ -144,16 +144,16 @@ cyg_hal_plf_comms_init(void)
#define SCSR_FE 0x0002 // Framing error
#define SCSR_PF 0x0001 // Parity error
//-----------------------------------------------------------------------------
typedef struct {
- cyg_uint16* base;
- cyg_int32 msec_timeout;
- int siu_vector;
- int imb3_vector;
- unsigned int level;
- int baud_rate;
+ cyg_uint16* base; // Base address of the register set
+ cyg_int32 msec_timeout; // How long do we wait
+ int imb3_vector; // The vector on the IMB3. No need to worry
+ // about SIU levels or vectors, that's the
+ // responsibility of the application
+ int baud_rate;
} channel_data_t;
//-----------------------------------------------------------------------------
static void
init_serial_channel(const channel_data_t* __ch_data)
@@ -161,53 +161,54 @@ init_serial_channel(const channel_data_t
cyg_uint16 * base = __ch_data->base;
cyg_uint16 br;
switch(__ch_data->baud_rate)
{
- case 300:
+ case 300:
br = CYG_DEV_SERIAL_RS232_SCxBR_300;
- break;
- case 600:
+ break;
+ case 600:
br = CYG_DEV_SERIAL_RS232_SCxBR_600;
- break;
- case 1200:
+ break;
+ case 1200:
br = CYG_DEV_SERIAL_RS232_SCxBR_1200;
- break;
- case 2400:
+ break;
+ case 2400:
br = CYG_DEV_SERIAL_RS232_SCxBR_2400;
- break;
- case 4800:
+ break;
+ case 4800:
br = CYG_DEV_SERIAL_RS232_SCxBR_4800;
- break;
- case 9600:
+ break;
+ case 9600:
br = CYG_DEV_SERIAL_RS232_SCxBR_9600;
- break;
- case 14400:
+ break;
+ case 14400:
br = CYG_DEV_SERIAL_RS232_SCxBR_14400;
- break;
- case 19200:
+ break;
+ case 19200:
br = CYG_DEV_SERIAL_RS232_SCxBR_19200;
- break;
- case 28800:
+ break;
+ case 28800:
br = CYG_DEV_SERIAL_RS232_SCxBR_28800;
- break;
- case 38400:
+ break;
+ case 38400:
br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
- break;
- case 57600:
+ break;
+ case 57600:
br = CYG_DEV_SERIAL_RS232_SCxBR_57600;
- break;
- case 115200:
+ break;
+ case 115200:
br = CYG_DEV_SERIAL_RS232_SCxBR_115200;
- break;
- default:
- // Use the default if something unknown is requested
+ break;
+ default:
+ // Use the default if something unknown is requested
br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
- break;
+ break;
}
- // 8-1-No parity
+ // 8-1-No parity, enable transmitter and receiver, leave interrupts
+ // as they are
HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, (SCCR1_TE | SCCR1_RE));
// Set baud rate
HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR0, br);
}
@@ -269,20 +270,16 @@ cyg_hal_plf_serial_putc(void* __ch_data,
// to change the timeout parameter ... (Is this a bug in other)
// PowerPC platform hals ?? You only see it when you really start from
// flash ....
static channel_data_t channels[2] = {
{ (cyg_uint16*)CYG_DEV_SERIAL_BASE_A,
- 1000,
- CYGNUM_HAL_INTERRUPT_SIU_LVL0,
+ 1000,
CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX,
- 0,
CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
{ (cyg_uint16*)CYG_DEV_SERIAL_BASE_B,
1000,
- CYGNUM_HAL_INTERRUPT_SIU_LVL0,
CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX,
- 0,
CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }
};
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
@@ -340,35 +337,35 @@ cyg_hal_plf_serial_control(void *__ch_da
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
- {
- va_list ap;
- va_start(ap, __func);
+ {
+ va_list ap;
+ va_start(ap, __func);
- ret = chan->baud_rate;
- chan->baud_rate = va_arg(ap, cyg_int32);
- init_serial_channel(chan);
+ ret = chan->baud_rate;
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ init_serial_channel(chan);
- va_end(ap);
- }
- break;
+ va_end(ap);
+ }
+ break;
case __COMMCTL_IRQ_ENABLE:
- HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level);
- HAL_INTERRUPT_UNMASK(chan->imb3_vector);
- HAL_INTERRUPT_UNMASK(chan->siu_vector);
+ // Just enable the interrupt on the IMB3. The debugged application is
+ // must make sure that the interrupt is properly decoded
+ HAL_INTERRUPT_UNMASK(chan->imb3_vector);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
+ // Same remark as above
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->imb3_vector);
- HAL_INTERRUPT_MASK(chan->siu_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
- ret = chan->siu_vector;
+ ret = chan->imb3_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
@@ -376,11 +373,11 @@ cyg_hal_plf_serial_control(void *__ch_da
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
- break;
+ break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
@@ -410,12 +407,12 @@ cyg_hal_plf_serial_isr(void *__ch_data,
c = cyg_hal_plf_serial_getc(__ch_data);
if(cyg_hal_is_break(&c, 1))
*__ctrlc = 1;
- HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector);
- res = CYG_ISR_HANDLED;
+ HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector);
+ res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
Index: hal/powerpc/moab/current/src/hal_aux.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/src/hal_aux.c,v
retrieving revision 1.3
diff -u -5 -p -r1.3 hal_aux.c
--- hal/powerpc/moab/current/src/hal_aux.c 3 Oct 2003 23:04:51 -0000 1.3
+++ hal/powerpc/moab/current/src/hal_aux.c 22 Nov 2003 13:45:45 -0000
@@ -61,10 +61,12 @@
#include <cyg/hal/hal_intr.h> // interrupt definitions
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_io.h> // I/O macros
#include <cyg/infra/diag.h>
#include CYGHWR_MEMORY_LAYOUT_H
+#include <cyg/io/pci_hw.h>
+#include <cyg/io/pci.h>
#ifdef CYGPKG_REDBOOT
#include <redboot.h>
#endif
@@ -94,10 +96,12 @@ unsigned char _moab_eth1_ESA[] = { 0x00,
void
hal_platform_init(void)
{
unsigned long munged_serial_no;
+ cyg_pci_device USB_info;
+ cyg_pci_device_id USB_dev = CYG_PCI_NULL_DEVID;
CYGARC_MFDCR(DCR_CPC0_ECID0, _moab_serial_no[0]);
CYGARC_MFDCR(DCR_CPC0_ECID1, _moab_serial_no[1]);
// Set default ethernet ESA - using 16 bits of munged serial number
munged_serial_no = ((_moab_serial_no[0] & 0x0000000F) << 12) | (_moab_serial_no[1] & 0x00000FFF);
@@ -106,10 +110,26 @@ hal_platform_init(void)
_moab_eth1_ESA[4] = ((munged_serial_no & 0x0000FF00) >> 8);
_moab_eth1_ESA[5] = ((munged_serial_no & 0x000000FF) >> 0);
#ifdef CYGPKG_REDBOOT
diag_printf("CPU serial number: %08x/%08x\n", _moab_serial_no[0], _moab_serial_no[1]);
#endif
+ // Configure USB controller (if present)
+ while (cyg_pci_find_next(USB_dev, &USB_dev)) {
+ cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(USB_dev);
+ cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(USB_dev);
+ cyg_uint16 v, d;
+ cyg_uint32 ext_reg;
+
+ cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_VENDOR, &v);
+ cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_DEVICE, &d);
+ if ((v == 0x1033) && ((d == 0x0035) || (d == 0x00E0))) {
+ // NEC USB controller
+ cyg_pcihw_read_config_uint32(bus, devfn, 0xE4, &ext_reg);
+ ext_reg |= (1<<5); // 48MHz clock
+ cyg_pcihw_write_config_uint32(bus, devfn, 0xE4, ext_reg);
+ }
+ }
}
#ifdef CYGSEM_REDBOOT_PLF_STARTUP
void
cyg_plf_redboot_startup(void)
Index: hal/powerpc/mpc5xx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/ChangeLog,v
retrieving revision 1.2
diff -u -5 -p -r1.2 ChangeLog
--- hal/powerpc/mpc5xx/current/ChangeLog 23 May 2002 23:04:26 -0000 1.2
+++ hal/powerpc/mpc5xx/current/ChangeLog 5 Nov 2003 21:17:19 -0000
@@ -1,5 +1,18 @@
+2002-11-11 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * include/var_regs.h: Removed double definitions for ICTRL, ICTRL_SERSHOW
+ and ICTRL_NOSERSHOW
+ * src/var_intr.c: Added a very simple serial arbitration isr to make GDB-CTRC
+ work in the absence of any device drivers.
+ * include/var_intr.h: Added a definition for hal_arbitration_isr_sci
+ * include/variant.inc: Make sure FREEZE gets negated before returning from an
+ exception. Failing to do so prevents proper operation of timers etc when
+ debugging.
+ * tests/intr0.c: completely rewritten to something that actually tests something.
+ Not completely finished.
+
2002-04-25 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
2002-04-25 Jonathan Larmour <jlarmour@redhat.com>
* New package.
Index: hal/powerpc/mpc5xx/current/include/var_intr.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/include/var_intr.h,v
retrieving revision 1.2
diff -u -5 -p -r1.2 var_intr.h
--- hal/powerpc/mpc5xx/current/include/var_intr.h 23 May 2002 23:04:26 -0000 1.2
+++ hal/powerpc/mpc5xx/current/include/var_intr.h 5 Nov 2003 21:17:19 -0000
@@ -77,12 +77,12 @@ typedef struct t_hal_mpc5xx_arbitration_
} hal_mpc5xx_arbitration_data;
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data *adata);
-externC void
-hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data *adata);
+externC hal_mpc5xx_arbitration_data *
+hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority);
//-----------------------------------------------------------------------------
// Exception vectors.
// Additional exceptions on the MPC5xx CPUs
@@ -2707,10 +2707,12 @@ externC cyg_uint32 hal_arbitration_isr_t
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
+externC cyg_uint32 hal_arbitration_isr_sci (CYG_ADDRWORD vector,
+ CYG_ADDRWORD data);
//-----------------------------------------------------------------------------
// Symbols used by assembly code
#define CYGARC_VARIANT_DEFS \
DEFINE(CYGNUM_HAL_VECTOR_NMI, CYGNUM_HAL_VECTOR_NMI);
Index: hal/powerpc/mpc5xx/current/include/var_regs.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/include/var_regs.h,v
retrieving revision 1.2
diff -u -5 -p -r1.2 var_regs.h
--- hal/powerpc/mpc5xx/current/include/var_regs.h 23 May 2002 23:04:26 -0000 1.2
+++ hal/powerpc/mpc5xx/current/include/var_regs.h 5 Nov 2003 21:17:19 -0000
@@ -80,11 +80,10 @@
#define CYGARC_REG_CMPF 153
#define CYGARC_REG_CMPG 154
#define CYGARC_REG_CMPH 155
#define CYGARC_REG_LCTRL1 156
#define CYGARC_REG_LCTRL2 157
-#define CYGARC_REG_ICTRL 158
#define CYGARC_REG_BAR 159
#define CYGARC_REG_MI_GRA 528
#define CYGARC_REG_L2U_GRA 536
#define CYGARC_REG_BBCMCR 560
#define CYGARC_REG_L2U_MCR 568
@@ -127,11 +126,10 @@
# define CMPF CYGARC_REG_CMPF
# define CMPG CYGARC_REG_CMPG
# define CMPH CYGARC_REG_CMPH
# define LCTRL1 CYGARC_REG_LCTRL1
# define LCTRL2 CYGARC_REG_LCTRL2
-# define ICTRL CYGARC_REG_ICTRL
# define BAR CYGARC_REG_BAR
# define MI_GRA CYGARC_REG_MI_GRA
# define L2U_GRA CYGARC_REG_L2U_GRA
# define BBCMCR CYGARC_REG_BBCMCR
# define L2U_MCR CYGARC_REG_L2U_MCR
Index: hal/powerpc/mpc5xx/current/include/variant.inc
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/include/variant.inc,v
retrieving revision 1.2
diff -u -5 -p -r1.2 variant.inc
--- hal/powerpc/mpc5xx/current/include/variant.inc 23 May 2002 23:04:26 -0000 1.2
+++ hal/powerpc/mpc5xx/current/include/variant.inc 5 Nov 2003 21:17:19 -0000
@@ -152,10 +152,16 @@
.endm
##-----------------------------------------------------------------------------
## MPC5xx exception state handling
.macro hal_variant_save regs
+#ifdef CYGSEM_HAL_ROM_MONITOR
+ ## This is not really a save of this registers. It just clears any pending
+ ## flags so that vwe can be sure that FREEZE will be negated after returning
+ ## from the interrupt. Failing to do can block a number of devices.
+ mfspr r3, 148;
+#endif
.endm
.macro hal_variant_load regs
.endm
Index: hal/powerpc/mpc5xx/current/src/var_intr.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/src/var_intr.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 var_intr.c
--- hal/powerpc/mpc5xx/current/src/var_intr.c 23 May 2002 23:04:26 -0000 1.2
+++ hal/powerpc/mpc5xx/current/src/var_intr.c 5 Nov 2003 21:17:19 -0000
@@ -151,10 +151,46 @@ hal_arbitration_isr_rtc (CYG_ADDRWORD ve
}
return 0;
}
+// Default arbitration ISR for serial interrupts. Although such arbitration
+// belongs in the serial device driver, we require this default implementation
+// for CTRL-C interrupts to be delivered correctly to any running ROM monitor.
+// A device driver that uses more than just receive interrupts may of course
+// provide its own arbiter.
+externC cyg_uint32
+hal_arbitration_isr_sci(CYG_ADDRWORD vector, CYG_ADDRWORD data)
+{
+ cyg_uint32 isr_ret;
+ cyg_uint16 scc_sr;
+ cyg_uint16 scc_cr;
+
+ // Try SCI0
+ HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scc_sr);
+ HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, scc_cr);
+ if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) {
+ isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX);
+#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
+ if (isr_ret & CYG_ISR_HANDLED)
+#endif
+ return isr_ret;
+ }
+
+ HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scc_sr);
+ HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, scc_cr);
+ if ((scc_sr & CYGARC_REG_IMM_SCxSR_RDRF) && (scc_cr & CYGARC_REG_IMM_SCCxR1_RIE)) {
+ isr_ret = hal_call_isr(CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX);
+#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
+ if (isr_ret & CYG_ISR_HANDLED)
+#endif
+ return isr_ret;
+ }
+
+ return 0;
+}
+
// -------------------------------------------------------------------------
// IMB3 interrupt decoding
//
// All interrupt priorities higher than 7 are mapped to SIU level 7. As much
// as 15 interrupting devices can be behind this. If more than one IMB3
@@ -210,40 +246,52 @@ mpc5xx_insert(hal_mpc5xx_arbitration_dat
ptmp->reserved = data;
return (hal_mpc5xx_arbitration_data *)(tmp.reserved);
}
+// This returns either the removed object or NULL if the priority
+// was not found in the list.
+// If a valid pointer is returned, the new start of the list is chained to it.
static hal_mpc5xx_arbitration_data *
mpc5xx_remove(hal_mpc5xx_arbitration_data * list,
- hal_mpc5xx_arbitration_data * data)
+ cyg_uint32 apriority)
{
- hal_mpc5xx_arbitration_data tmp;
+ hal_mpc5xx_arbitration_data tmp;
+ hal_mpc5xx_arbitration_data result = 0;
hal_mpc5xx_arbitration_data * ptmp = &tmp;
tmp.reserved = list;
while(ptmp->reserved)
{
- if(ptmp->reserved == data)
+ if(((hal_mpc5xx_arbitration_data *)(ptmp->reserved))->priority == apriority)
break;
+ // move on
ptmp = (hal_mpc5xx_arbitration_data *)(ptmp->reserved);
}
+ // When we come here, ptmp is either chained to NULL or to the one we were looking for.
if(ptmp->reserved)
+ { // remove it
+ result = (hal_mpc5xx_arbitration_data *)(ptmp->reserved);
+ result->reserved = tmp.reserved;
+
ptmp->reserved = ((hal_mpc5xx_arbitration_data *)(ptmp->reserved))->reserved;
+ }
- return (hal_mpc5xx_arbitration_data *)(tmp.reserved);
+ return result;
}
#endif
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
-{
+{ // Find the SIU vector from the priority
CYG_ADDRWORD vector = 2*(1 + adata->priority);
+
if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
- {
- HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, 0);
+ { // Store adata in the objects table
+ HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, adata);
HAL_INTERRUPT_UNMASK(vector);
}
else
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
@@ -251,35 +299,97 @@ hal_mpc5xx_install_arbitration_isr(hal_m
// the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_insert(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#else
- HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, 0);
+ HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
}
-externC void
-hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
+externC hal_mpc5xx_arbitration_data *
+hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority)
{
+ hal_mpc5xx_arbitration_data * result = 0;
+
+ // Find the SIU vector from the priority
+ CYG_ADDRWORD vector = 2*(1 + apriority);
+ if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
+ {
+ result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[vector]);
+ HAL_INTERRUPT_DETACH(vector, hal_interrupt_handlers[vector]);
+ }
+ else
+ {
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
- // Prevent anything from coming through while manipulating the list
- HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
- imb3_data_head = mpc5xx_remove(imb3_data_head, adata);
- HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
+ // Prevent anything from coming through while manipulating the list
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
+ result = mc5xx_remove(imb3_data_head, apriority);
+
+ // If something was removed, update the list.
+ if(result) imb3_data_head = result->reserved;
+ HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
+#else
+ result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[CYGNUM_HAL_INTERRUPT_SIU_LVL7]);
+ HAL_INTERRUPT_DETACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SIU_LVL7]);
#endif
+ }
+
+ return result;
}
// -------------------------------------------------------------------------
// Variant specific interrupt setup
+#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
+ || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
+static hal_mpc5xx_arbitration_data sci_arbiter;
+#endif
+
externC void
hal_variant_IRQ_init(void)
{
+ // Mask off everything. This guarantees that we can safely install a handler on the decrementer
+ // later on
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ0);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ1);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ2);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ3);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ4);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ5);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ6);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ7);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL0);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL1);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL2);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL3);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL4);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL5);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL6);
+ HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
+
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
+#endif
+
+#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
+ || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
+ // GDB-CTRLC
+ // Install a default arbiter for serial interrupts. This allows
+ // to make a boot monitor simply turn on the required Rx interrupt
+ // and still be delivered the necessary default isr. Without this,
+ // redboot would be informed of a level interrupt on the SIU instead
+ // of the Rx interrupt that really happened.
+ // Make sure the interrupts are set up on the correct level
+ sci_arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI;
+ sci_arbiter.data = 0;
+ sci_arbiter.arbiter = hal_arbitration_isr_sci;
+
+ hal_mpc5xx_install_arbitration_isr(&sci_arbiter);
+ HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
+ HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
#endif
}
// -------------------------------------------------------------------------
// EOF var_intr.c
Index: hal/powerpc/mpc5xx/current/src/variant.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/src/variant.S,v
retrieving revision 1.2
diff -u -5 -p -r1.2 variant.S
--- hal/powerpc/mpc5xx/current/src/variant.S 23 May 2002 23:04:27 -0000 1.2
+++ hal/powerpc/mpc5xx/current/src/variant.S 5 Nov 2003 21:17:19 -0000
@@ -1,10 +1,10 @@
##=============================================================================
##
## variant.S
##
-## POWERPC MPC8xx variant code
+## POWERPC MPC5xx variant code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
@@ -38,15 +38,15 @@
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
-## Author(s): jskov
-## Contributors:jskov
-## Date: 2000-02-04
-## Purpose: PowerPC MPC8xx variant code
-## Description: Variant specific code for PowerPC MPC8xx CPUs.
+## Author(s): Bob Koninckx
+## Contributors: Bob Koninckx
+## Date: 2000-02-04
+## Purpose: PowerPC MPC5xx variant code
+## Description: Variant specific code for PowerPC MPC5xx CPUs.
##
######DESCRIPTIONEND####
##
##=============================================================================
Index: hal/powerpc/mpc5xx/current/tests/intr0.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc5xx/current/tests/intr0.c,v
retrieving revision 1.2
diff -u -5 -p -r1.2 intr0.c
--- hal/powerpc/mpc5xx/current/tests/intr0.c 23 May 2002 23:04:27 -0000 1.2
+++ hal/powerpc/mpc5xx/current/tests/intr0.c 5 Nov 2003 21:17:19 -0000
@@ -38,270 +38,193 @@
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=================================================================
//#####DESCRIPTIONBEGIN####
//
-// Author(s): jskov
-// Contributors: jskov
-// Date: 1998-12-01
-// Description: Simple test of MPC860 interrupt handling when the
+// Author(s): Bob Koninckx
+// Contributors: Bob Koninckx
+// Date: 2002-11-16
+// Description: Simple test of MPC5xx interrupt handling when the
// kernel has not been configured. Uses timer interrupts.
// Options:
//####DESCRIPTIONEND####
-//#define DEBUG_PRINTFS
-#ifdef DEBUG_PRINTFS
-extern diag_printf( char *format, ... );
-#endif
-
#include <pkgconf/hal.h>
-
-#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
-#include <cyg/hal/ppc_regs.h>
-
-#include <cyg/hal/hal_intr.h>
+#include <pkgconf/infra.h>
#include <cyg/infra/testcase.h>
+#include <cyg/infra/cyg_trac.h>
-#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
-
-#undef CHECK(b)
-#define CHECK(b) CYG_TEST_CHECK(b,#b)
+#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/ppc_regs.h>
-// Can't rely on Cyg_Interrupt class being defined.
-#define Cyg_InterruptHANDLED 1
+#define ID_RTC_SEC 12345
+#define ID_RTC_ALR 23451
+#define ID_PIT 34512
+#define ID_TBA 45123
+#define ID_TBB 51234
-// This is the period between interrupts, measured in decrementer ticks.
-// Period must be longer than the time required for setting up all the
-// interrupt handlers.
+#define CYG_InterruptHANDLED 1
#define PIT_PERIOD 5000
+#define TB_PERIOD (PIT_PERIOD*160)
-#ifdef CYGPKG_HAL_POWERPC_MBX
-#define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS
-#else
-#define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors
-#endif
-
-#define ID_RTC_SEC 12345
-#define ID_RTC_ALR 23451
-#define ID_PIT 34512
-#define ID_TBA 45123
-#define ID_TBB 51234
+// Factor 160 comes from setting SCCR = 0x0300. Thus, TBS = 1 -->> Time base is clocked by
+// system clock / 16 = 40MHz / 16
+// RTDIV = 1 -->> RTC/PIT clocked by OSCM / 256
+// or 4 MHz / 256
+// Factor of 160 between the two
volatile cyg_uint32 count = 0;
-
-// Time/PERIOD 0 1 2 3 4 5 6 7 8 9 10
-// Interrupt PIT TBA PIT PIT TBB PIT PIT
-// pit_count 0 0 0 1 1 2 2 3 3 4 4
-// count 0 0 1 3 4 4 5 40 41 42
-
-static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42};
static int pit_count = 0;
+static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42};
// These are useful for debugging:
static cyg_uint32 count_actual_table[] = { -1, -1, -1, -1, -1};
static cyg_uint32 tbr_actual_table[] = { -1, -1, -1, -1, -1};
-// Periodic timer ISR. Should be executing 5 times.
-static cyg_uint32 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data)
-{
- cyg_uint32 verify_value;
-
- CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
-
- CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_PIT == vector, "Wrong vector!");
- CYG_ASSERT (ID_PIT == data, "Wrong data!");
-
- HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT);
-
- count++;
-
- count_actual_table[pit_count] = count;
- {
- cyg_uint32 tbl;
- CYGARC_MFTB (TBL_R, tbl);
- tbr_actual_table[pit_count] = tbl;
- }
-
- verify_value = count_verify_table[pit_count++];
-
-#ifdef DEBUG_PRINTFS
- diag_printf( "ISR_PIT executed %d of 5\n", pit_count );
-#endif
-
- CYG_ASSERT (count == verify_value, "Count wrong!");
-
- // End of test when count is 42. Mask interrupts and print PASS text.
- if (42 <= count || 5 == pit_count) {
- HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
- HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
- HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
-
-#ifdef DEBUG_PRINTFS
- diag_printf( "INFO: Actual counts: %d %d %d %d %d\n",
- count_actual_table[0],
- count_actual_table[1],
- count_actual_table[2],
- count_actual_table[3],
- count_actual_table[4] );
- diag_printf( "INFO: Actuals tbrs: %d %d %d %d %d\n",
- tbr_actual_table[0],
- tbr_actual_table[1],
- tbr_actual_table[2],
- tbr_actual_table[3],
- tbr_actual_table[4] );
-#endif
- if (42 == count && 5 == pit_count)
- CYG_TEST_PASS_FINISH("Intr 0 OK");
- else
- CYG_TEST_FAIL_FINISH("Intr 0 Failed.");
- }
-
- return Cyg_InterruptHANDLED;
-}
+hal_mpc5xx_arbitration_data hal_arbitration_data_tb;
+hal_mpc5xx_arbitration_data hal_arbitration_data_pit;
-// TimeBase A ISR. Should be executing once.
static cyg_uint32 isr_tba(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
- CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
-
- CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!");
+ CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
+
+ CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!");
CYG_ASSERT (ID_TBA == data, "Wrong data!");
- HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
-
- count = count * 3;
+ HAL_INTERRUPT_ACKNOWLEDGE(vector);
+ count = count*3;
-#ifdef DEBUG_PRINTFS
- diag_printf( "ISR_TBA executed\n" );
-#endif
-
- return Cyg_InterruptHANDLED;
+ return CYG_InterruptHANDLED;
}
-// TimeBase B ISR. Should be executing once.
static cyg_uint32 isr_tbb(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
- CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
-
- CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!");
+ CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
+
+ CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!");
CYG_ASSERT (ID_TBB == data, "Wrong data!");
+
+ HAL_INTERRUPT_ACKNOWLEDGE(vector);
+ count = count*8;
- HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
-
- count = count * 8;
-
-#ifdef DEBUG_PRINTFS
- diag_printf( "ISR_TBB executed\n" );
-#endif
-
- return Cyg_InterruptHANDLED;
+ return CYG_InterruptHANDLED;
}
-void intr0_main( void )
+static cyg_uint32
+isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
- CYG_TEST_INIT();
+ cyg_uint32 verify_value;
+
+ CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
+
+ CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!");
+ CYG_ASSERT (ID_PIT == data, "Wrong data!");
+
+ HAL_INTERRUPT_ACKNOWLEDGE(vector);
-#if 0
- // The A.3 revision of the CPU I'm using at the moment generates a
- // machine check exception when writing to IMM_RTCSC. Smells a
- // bit like the "SIU4. Spurious External Bus Transaction Following
- // PLPRCR Write." CPU errata. Have to find out for sure. Run real
- // time clock interrupts on level 0
- {
- // Still to do.
- }
-#endif
-
- // Run periodic timer interrupt on level 1
- {
- cyg_uint16 piscr;
-
- // Attach pit arbiter.
- HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL1,
- &hal_arbitration_isr_pit, ID_PIT, 0);
- HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL1);
-
- // Attach pit isr.
- HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
- ID_PIT, 0);
- HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, 1);
- HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
-
-
- // Set period.
- HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC,
- (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
-
-#ifdef DEBUG_PRINTFS
- diag_printf( "PIT set to %d\n", 2*PIT_PERIOD );
-#endif
- // Enable.
- HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
- piscr |= CYGARC_REG_IMM_PISCR_PTE;
- HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
- }
-
- // Run timebase interrupts on level 2
- {
- cyg_uint16 tbscr;
- cyg_uint32 tbl;
-
- // Attach tb arbiter.
- HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL2,
- &hal_arbitration_isr_tb, ID_TBA, 0);
- HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL2);
-
- // Attach tb isrs.
- HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba,
- ID_TBA, 0);
- HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb,
- ID_TBB, 0);
- HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, 2);
- HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
- HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
+ count++;
- // Set reference A & B registers.
+ count_actual_table[pit_count] = count;
+ {
+ cyg_uint32 tbl;
CYGARC_MFTB (TBL_R, tbl);
- tbl += TB_PERIOD*3;
- HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl);
- tbl += TB_PERIOD*4;
- HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl);
-
-#ifdef DEBUG_PRINTFS
- diag_printf( "TB initial %d, !1 %d !2 %d\n",
- tbl - 7*TB_PERIOD,
- tbl - 4*TB_PERIOD,
- tbl - 0*TB_PERIOD );
-#endif
- // Enable.
- HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
- tbscr |= (CYGARC_REG_IMM_TBSCR_REFA | CYGARC_REG_IMM_TBSCR_REFB |
- CYGARC_REG_IMM_TBSCR_TBE);
- HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
- tbscr |= CYGARC_REG_IMM_TBSCR_REFAE | CYGARC_REG_IMM_TBSCR_REFBE;
- HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
- }
+ tbr_actual_table[pit_count] = tbl;
+ }
- HAL_ENABLE_INTERRUPTS();
+ verify_value = count_verify_table[pit_count++];
+
+ CYG_ASSERT (count == verify_value, "Count wrong!");
+
+ // End of test when count is 42. Mask interrupts and print PASS text.
+ if (42 <= count || 5 == pit_count) {
+ HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
+ HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
+ HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
+
+ if(5 == pit_count)
+ {
+ if(42 != count) CYG_TEST_INFO("TB/PIT ratio does not match");
+ }
+
+ if(5 == pit_count && 42 == count)
+ {
+ CYG_TEST_PASS_FINISH("Intr 0 OK");
+ }
+ else
+ {
+ CYG_TEST_FAIL_FINISH("Intr 0 FAILED");
+ }
+ }
+
+ return CYG_InterruptHANDLED;
+}
+
+static void
+intr0_main( void )
+{
+ int tb_period = TB_PERIOD;
+ cyg_uint32 tbl;
+ cyg_uint16 piscr;
+
+ // Install the PIT Interrupt arbiter
+ hal_arbitration_data_pit.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT;
+ hal_arbitration_data_pit.data = 0;
+ hal_arbitration_data_pit.arbiter = hal_arbitration_isr_pit;
+
+ hal_mpc5xx_install_arbitration_isr(&hal_arbitration_data_pit);
+
+ // attach PIT isr
+ HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit, ID_PIT, 0);
+ HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT);
+
+ // Set period
+ HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC, (2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
+
+ // Enable.
+ HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
+ piscr |= CYGARC_REG_IMM_PISCR_PTE;
+ HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
+
+ // Clear any pending interrupts and enable them
+ HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT);
+ HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
+
+ // Install the Timebase Interrupt Arbiter
+ hal_arbitration_data_tb.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB;
+ hal_arbitration_data_tb.data = 0;
+ hal_arbitration_data_tb.arbiter = hal_arbitration_isr_tb;
+
+ hal_mpc5xx_install_arbitration_isr(&hal_arbitration_data_tb);
+
+ // Attach tb isrs.
+ HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba, ID_TBA, 0);
+ HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb, ID_TBB, 0);
+ HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB);
+
+ // Set reference A & B registers.
+ CYGARC_MFTB (TBL_R, tbl);
+ tbl += tb_period*3;
+ HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl);
+ tbl += tb_period*4;
+ HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl);
+
+ // Clear any pending interrupts and enable them
+ HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_SIU_TB_A);
+ HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_SIU_TB_B);
+ HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
+ HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
- for (;;);
-}
+ HAL_ENABLE_INTERRUPTS();
-externC void
-cyg_start( void )
-{
- intr0_main();
+ for(;;);
}
-#else // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
-
externC void
cyg_start( void )
{
CYG_TEST_INIT();
- CYG_TEST_PASS_FINISH("N/A: CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE disabled");
+ intr0_main();
+ CYG_TEST_PASS_FINISH("HAL Interrupt test");
}
-
-#endif // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
-
-// EOF intr0.c
Index: io/pci/current/src/pci.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/io/pci/current/src/pci.c,v
retrieving revision 1.15
diff -u -5 -p -r1.15 pci.c
--- io/pci/current/src/pci.c 19 Nov 2003 20:39:44 -0000 1.15
+++ io/pci/current/src/pci.c 22 Nov 2003 13:41:21 -0000
@@ -550,15 +550,17 @@ cyg_pci_find_device( cyg_uint16 vendor,
cyg_pcihw_read_config_uint16(bus, devfn,
CYG_PCI_CFG_DEVICE, &d);
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("... PCI vendor = %x, device = %x\n", v, d);
#endif
+ diag_printf("... PCI vendor = %x/%x, device = %x/%x\n", v, vendor, d, device);
if (v != vendor) continue;
// Check that device matches.
if (d == device) {
*devid = new_devid;
+ diag_printf("Found it!\n");
return true;
}
}
return false;
Index: io/watchdog/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/io/watchdog/current/ChangeLog,v
retrieving revision 1.5
diff -u -5 -p -r1.5 ChangeLog
--- io/watchdog/current/ChangeLog 4 Apr 2003 04:28:11 -0000 1.5
+++ io/watchdog/current/ChangeLog 5 Nov 2003 20:43:34 -0000
@@ -1,5 +1,11 @@
+2003-11-05 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
+
+ * src/watchdog.cxx:
+ * include/watchdog.hxx:
+ * include/watchdog.h: New file - add "C" API for watchdog functions.
+
2003-04-03 Thomas Koeller <thomas.koeller@baslerweb.com>
* cdl/watchdog.cdl: Turned 'wallclock' into 'watchdog' in string.
2003-04-02 Jonathan Larmour <jifl@eCosCentric.com>
Index: io/watchdog/current/include/watchdog.h
===================================================================
RCS file: io/watchdog/current/include/watchdog.h
diff -N io/watchdog/current/include/watchdog.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ io/watchdog/current/include/watchdog.h 5 Nov 2003 20:40:43 -0000
@@ -0,0 +1,59 @@
+#ifndef _IO_WATCHDOG_H_
+#define _IO_WATCHDOG_H_
+
+//==========================================================================
+//
+// watchdog.h
+//
+// c-api to the watchdog.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Bob Koninckx
+// Contributors: Bob Koninckx
+// Date: 2003-05-24
+// Purpose: provide a c-api to the watchdog
+//
+//####DESCRIPTIONEND####
+
+#include <cyg/infra/cyg_type.h>
+
+externC void watchdog_start(void);
+externC void watchdog_reset(void);
+externC cyg_uint64 watchdog_get_resolution(void);
+
+#endif // _IO_WATCHDOG_H_
Index: io/watchdog/current/include/watchdog.hxx
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/io/watchdog/current/include/watchdog.hxx,v
retrieving revision 1.3
diff -u -5 -p -r1.3 watchdog.hxx
--- io/watchdog/current/include/watchdog.hxx 23 May 2002 23:06:39 -0000 1.3
+++ io/watchdog/current/include/watchdog.hxx 5 Nov 2003 20:40:43 -0000
@@ -54,11 +54,11 @@
//
//####DESCRIPTIONEND####
//
//==========================================================================
-#include <cyg/kernel/ktypes.h>
+#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_ass.h> // assertion macros
class Cyg_Watchdog_Action;
// -------------------------------------------------------------------------
Index: io/watchdog/current/src/watchdog.cxx
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/io/watchdog/current/src/watchdog.cxx,v
retrieving revision 1.3
diff -u -5 -p -r1.3 watchdog.cxx
--- io/watchdog/current/src/watchdog.cxx 23 May 2002 23:06:39 -0000 1.3
+++ io/watchdog/current/src/watchdog.cxx 5 Nov 2003 20:40:43 -0000
@@ -56,10 +56,11 @@
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/drv_api.h> // for locking
#include <cyg/io/watchdog.hxx> // watchdog API
+#include <cyg/io/watchdog.h> // watchdog c-api
// -------------------------------------------------------------------------
// Statics
// A static pointer to the single system defined watchdog device.
@@ -165,8 +166,29 @@ Cyg_Watchdog::uninstall_action( Cyg_Watc
CYG_REPORT_RETURN();
}
#endif // CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT
+
+// -------------------------------------------------------------------------
+// Implementation of the C-api
+
+externC void
+watchdog_start(void)
+{
+ Cyg_Watchdog::watchdog.start();
+}
+
+externC void
+watchdog_reset(void)
+{
+ Cyg_Watchdog::watchdog.reset();
+}
+
+externC cyg_uint64
+watchdog_get_resolution(void)
+{
+ return Cyg_Watchdog::watchdog.get_resolution();
+}
// -------------------------------------------------------------------------
// EOF io/watchdog/watchdog.cxx