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Adder - fix time base
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at ecos dot sourceware dot org>
- Date: 10 Dec 2003 04:40:23 -0700
- Subject: Adder - fix time base
- Organization: MLB Associates
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/powerpc/adder/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/ChangeLog,v
retrieving revision 1.14
diff -u -5 -p -r1.14 ChangeLog
--- hal/powerpc/adder/current/ChangeLog 8 Dec 2003 14:31:54 -0000 1.14
+++ hal/powerpc/adder/current/ChangeLog 10 Dec 2003 11:39:29 -0000
@@ -1,5 +1,12 @@
+2003-12-10 Gary Thomas <gary@mlbassoc.com>
+
+ * cdl/hal_powerpc_adder.cdl: System clock was using wrong frequency
+ (time base). On this platform, it's configured to use the raw
+ OSCLK which is a constant 10MHz, not the higher speed PLL based
+ clocks.
+
2003-12-08 Gary Thomas <gary@mlbassoc.com>
* cdl/hal_powerpc_adder.cdl:
HAL_PLATFORM_CPU now defined by MPC8xx variant CDL.
Index: hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl,v
retrieving revision 1.10
diff -u -5 -p -r1.10 hal_powerpc_adder.cdl
--- hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 8 Dec 2003 14:31:54 -0000 1.10
+++ hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl 10 Dec 2003 00:59:23 -0000
@@ -86,14 +86,14 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER {
requires { CYGHWR_HAL_POWERPC_MPC8XX == "850" }
default_value 0
implements CYGNUM_HAL_QUICC_SMC2
implements CYGNUM_HAL_QUICC_SCC3
define_proc {
- puts $::cdl_header "#define HAL_PLATFORM_BOARD \"A&M ADDER\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"A&M Adder\""
}
description "
- Select this model for an Adder with the PPC850 processor."
+ Select this model for an Adder with the MPC850 processor."
}
cdl_option CYGHWR_HAL_POWERPC_ADDER_II {
display "Adder-II with 852T"
requires !CYGHWR_HAL_POWERPC_ADDER_I
@@ -103,11 +103,11 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER {
implements CYGNUM_HAL_QUICC_SCC3
define_proc {
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"A&M AdderII\""
}
description "
- Select this model for an Adder with the PPC852T processor."
+ Select this model for an Adder with the MPC852T processor."
}
}
cdl_component CYG_HAL_STARTUP {
display "Startup type"
@@ -155,11 +155,12 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER {
default_value 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
- default_value { ((((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/4)/16)/CYGNUM_HAL_RTC_DENOMINATOR) }
+# Timer clocks are based on OSCLK = 10MHz
+ default_value { (((10*1000000)/4)/CYGNUM_HAL_RTC_DENOMINATOR) }
}
}
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"