This is the mail archive of the
ecos-patches@sources.redhat.com
mailing list for the eCos project.
MOAB - update board support
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at ecos dot sourceware dot org>
- Date: Tue, 24 Aug 2004 07:19:53 -0600
- Subject: MOAB - update board support
- Organization: MLB Associates
For new board, revision 1.1
Also, add missing CDL for FLASH test program
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: devs/eth/ns/dp83816/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/ns/dp83816/current/ChangeLog,v
retrieving revision 1.3
diff -u -5 -p -r1.3 ChangeLog
--- devs/eth/ns/dp83816/current/ChangeLog 14 Oct 2003 13:44:28 -0000 1.3
+++ devs/eth/ns/dp83816/current/ChangeLog 24 Aug 2004 13:06:45 -0000
@@ -1,5 +1,10 @@
+2004-08-24 Gary Thomas <gary@mlbassoc.com>
+
+ * src/if_dp83816.c: Enable start/stop functions (device was always
+ enabled once configured before)
+
2003-10-14 Gary Thomas <gary@mlbassoc.com>
* src/if_dp83816.c (dp83816_poll): Try to better detect condition
where device just stops. This seems to be related to Rx overruns,
but there is no status reported. The best that can be done is
Index: devs/eth/ns/dp83816/current/src/if_dp83816.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/ns/dp83816/current/src/if_dp83816.c,v
retrieving revision 1.5
diff -u -5 -p -r1.5 if_dp83816.c
--- devs/eth/ns/dp83816/current/src/if_dp83816.c 9 Feb 2004 20:23:39 -0000 1.5
+++ devs/eth/ns/dp83816/current/src/if_dp83816.c 15 Aug 2004 12:26:44 -0000
@@ -151,12 +151,12 @@ dp83816_reset(dp83816_priv_data_t *dp)
}
// Setup up acceptance criteria
DP_OUT(dp->base, DP_RFCR, _RFCR_RFEN | _RFCR_AAB | _RFCR_APM);
// Set up interrupts
DP_IN(dp->base, DP_ISR, stat); // Clear any current interrupts
- DP_OUT(dp->base, DP_IMR, 0xFFFFFFFF); // Enable them all!
- DP_OUT(dp->base, DP_IER, 1);
+ DP_OUT(dp->base, DP_IMR, 0x00000000); // Disable them all!
+ DP_OUT(dp->base, DP_IER, 0);
return true;
}
static bool
dp83816_init(struct cyg_netdevtab_entry *tab)
@@ -220,10 +220,12 @@ dp83816_init(struct cyg_netdevtab_entry
static void
dp83816_stop(struct eth_drv_sc *sc)
{
dp83816_priv_data_t *dp = (dp83816_priv_data_t *)sc->driver_private;
+ DP_OUT(dp->base, DP_IMR, 0x00000000); // Disable interrupts
+ DP_OUT(dp->base, DP_IER, 0);
DP_OUT(dp->base, DP_CR, _CR_RXD | _CR_TXD);
}
//
// This function is called to "start up" the interface. It may be called
@@ -234,10 +236,12 @@ dp83816_stop(struct eth_drv_sc *sc)
static void
dp83816_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
{
dp83816_priv_data_t *dp = (dp83816_priv_data_t *)sc->driver_private;
+ DP_OUT(dp->base, DP_IMR, 0xFFFFFFFF); // Enable interrupts
+ DP_OUT(dp->base, DP_IER, 1);
DP_OUT(dp->base, DP_CR, _CR_RXE | _CR_TXE);
}
//
// This routine is called to perform special "control" opertions
Index: devs/eth/powerpc/moab/current/include/moab_eth.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/moab/current/include/moab_eth.inl,v
retrieving revision 1.3
diff -u -5 -p -r1.3 moab_eth.inl
--- devs/eth/powerpc/moab/current/include/moab_eth.inl 2 Oct 2003 20:11:58 -0000 1.3
+++ devs/eth/powerpc/moab/current/include/moab_eth.inl 15 Aug 2004 12:26:44 -0000
@@ -70,11 +70,11 @@ static unsigned char ppc405_eth_txbufs[T
static mal_bd_t ppc405_eth_rxbd[CYGNUM_DEVS_ETH_POWERPC_PPC405_RxNUM] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
static mal_bd_t ppc405_eth_txbd[CYGNUM_DEVS_ETH_POWERPC_PPC405_TxNUM] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
extern char _moab_eth0_ESA[];
static struct ppc405_eth_info ppc405_eth0_info = {
- 0, // Interrupt vector
+ 0, // Interrupt vector
"eth0_esa",
_moab_eth0_ESA,
CYGNUM_DEVS_ETH_POWERPC_PPC405_RxNUM, // Number of Rx buffers
ppc405_eth_rxbufs, // Rx buffer space
ppc405_eth_rxbd, // Rx buffer headers
Index: devs/flash/toshiba/tc58xxx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/toshiba/tc58xxx/current/ChangeLog,v
retrieving revision 1.3
diff -u -5 -p -r1.3 ChangeLog
--- devs/flash/toshiba/tc58xxx/current/ChangeLog 7 Mar 2004 16:44:24 -0000 1.3
+++ devs/flash/toshiba/tc58xxx/current/ChangeLog 24 Aug 2004 13:07:36 -0000
@@ -1,5 +1,10 @@
+2004-08-24 Gary Thomas <gary@mlbassoc.com>
+
+ * include/flash_tc58xxx.inl: Initial implementation of NAND ECC
+ support (used by JFFS2).
+
2004-03-07 Gary Thomas <gary@mlbassoc.com>
* include/flash_tc58xxx.inl: Page addressing was wrong for large (> 32MB) devices.
2004-02-25 Gary Thomas <gary@mlbassoc.com>
Index: devs/flash/toshiba/tc58xxx/current/include/flash_tc58xxx.inl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/flash/toshiba/tc58xxx/current/include/flash_tc58xxx.inl,v
retrieving revision 1.3
diff -u -5 -p -r1.3 flash_tc58xxx.inl
--- devs/flash/toshiba/tc58xxx/current/include/flash_tc58xxx.inl 7 Mar 2004 16:44:25 -0000 1.3
+++ devs/flash/toshiba/tc58xxx/current/include/flash_tc58xxx.inl 15 Aug 2004 12:26:44 -0000
@@ -59,10 +59,11 @@
// FIXME! Someday add support for ECC data & fixups of bad sectors
#include <pkgconf/hal.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_cache.h>
+#include <cyg/infra/diag.h>
#include CYGHWR_MEMORY_LAYOUT_H
#define _FLASH_PRIVATE_
#include <cyg/io/flash.h>
@@ -244,11 +245,10 @@ int
flash_erase_block(void* block, unsigned int size)
{
volatile flash_data_t* ROM;
volatile flash_data_t* b_p = (volatile flash_data_t*) block;
int res = FLASH_ERR_OK;
- int len = 0;
int cnt = 0;
flash_data_t stat;
#if FLASH_DEBUG > 0
diag_printf("%s - block: %x, size: %d\n", __FUNCTION__, block, size);
@@ -270,10 +270,11 @@ flash_erase_block(void* block, unsigned
}
CYGHWR_FLASH_TC58XXX_ALE(0);
CYGHWR_FLASH_TC58XXX_CLE(1);
put_NAND(ROM, FLASH_Start_Erase);
CYGHWR_FLASH_TC58XXX_CLE(0);
+ CYGACC_CALL_IF_DELAY_US(10);
while (!CYGHWR_FLASH_TC58XXX_RDY()) cnt++; // Wait for operation to complete
CYGHWR_FLASH_TC58XXX_CLE(1);
put_NAND(ROM, FLASH_Status);
CYGHWR_FLASH_TC58XXX_CLE(0);
stat = *ROM;
@@ -282,26 +283,226 @@ flash_erase_block(void* block, unsigned
diag_printf(">>\n");
#endif
#if FLASH_DEBUG > 0
diag_printf("block: %x, stat: %x, count = %d\n", b_p, stat, cnt);
#endif
+ if (stat != 0xC0) {
+ diag_printf("Status after erase: %x\n", stat);
+ if ((stat & 0x80) == 0x00) {
+ res = FLASH_ERR_PROTECT;
+ } else {
+ res = FLASH_ERR_ERASE;
+ }
+ }
return res;
}
+//
+// ECC support - adapted from Linux:
+//
+// drivers/mtd/nand_ecc.c
+//
+// Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+// Toshiba America Electronics Components, Inc.
+//
+
+static const unsigned char _nand_ecc_precalc_table[] = {
+ 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
+ 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+ 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+ 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+ 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+ 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+ 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+ 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+ 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+ 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+ 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+ 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+ 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+ 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+ 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+ 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
+};
+
+static void
+_nand_trans_result(unsigned char reg2, unsigned char reg3,
+ unsigned char *ecc0, unsigned char *ecc1)
+{
+ unsigned char a, b, i, tmp1, tmp2;
+
+ /* Initialize variables */
+ a = b = 0x80;
+ tmp1 = tmp2 = 0;
+
+ /* Calculate first ECC byte */
+ for (i = 0; i < 4; i++) {
+ if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
+ tmp1 |= b;
+ b >>= 1;
+ if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
+ tmp1 |= b;
+ b >>= 1;
+ a >>= 1;
+ }
+
+ /* Calculate second ECC byte */
+ b = 0x80;
+ for (i = 0; i < 4; i++) {
+ if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
+ tmp2 |= b;
+ b >>= 1;
+ if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
+ tmp2 |= b;
+ b >>= 1;
+ a >>= 1;
+ }
+
+ /* Store two of the ECC bytes */
+ *ecc0 = tmp1;
+ *ecc1 = tmp2;
+}
+
+//
+// Calculate 3 byte ECC on 256 bytes of data
+//
+static void
+_nand_page_ECC(unsigned char *data, unsigned char *ecc0,
+ unsigned char *ecc1, unsigned char *ecc2)
+{
+ unsigned char idx, reg1, reg2, reg3;
+ int j;
+
+ /* Initialize variables */
+ reg1 = reg2 = reg3 = 0;
+ *ecc0 = *ecc1 = *ecc2 = 0;
+
+ /* Build up column parity */
+ for(j = 0; j < 256; j++) {
+ /* Get CP0 - CP5 from table */
+ idx = _nand_ecc_precalc_table[*data++];
+ reg1 ^= (idx & 0x3f);
+ /* All bit XOR = 1 ? */
+ if (idx & 0x40) {
+ reg3 ^= (unsigned char) j;
+ reg2 ^= ~((unsigned char) j);
+ }
+ }
+
+ /* Create non-inverted ECC code from line parity */
+ _nand_trans_result(reg2, reg3, ecc0, ecc1);
+
+ /* Calculate final ECC code */
+ *ecc0 = ~*ecc0;
+ *ecc1 = ~*ecc1;
+ *ecc2 = ((~reg1) << 2) | 0x03;
+}
+
+//
+// Correct a buffer via ECC (1 bit, 256 byte block)
+// Return: 0 => No error
+// 1 => Corrected
+// 2 => Not corrected, ECC updated
+// -1 => Not correctable
+//
+int
+_nand_correct_data(unsigned char *dat, unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+ unsigned char a, b, c, d1, d2, d3, add, bit, i;
+
+ /* Do error detection */
+ d1 = calc_ecc[0] ^ read_ecc[0];
+ d2 = calc_ecc[1] ^ read_ecc[1];
+ d3 = calc_ecc[2] ^ read_ecc[2];
+
+ if ((d1 | d2 | d3) == 0) {
+ /* No errors */
+ return 0;
+ } else {
+ a = (d1 ^ (d1 >> 1)) & 0x55;
+ b = (d2 ^ (d2 >> 1)) & 0x55;
+ c = (d3 ^ (d3 >> 1)) & 0x54;
+
+ /* Found and will correct single bit error in the data */
+ if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
+ c = 0x80;
+ add = 0;
+ a = 0x80;
+ for (i=0; i<4; i++) {
+ if (d1 & c)
+ add |= a;
+ c >>= 2;
+ a >>= 1;
+ }
+ c = 0x80;
+ for (i=0; i<4; i++) {
+ if (d2 & c)
+ add |= a;
+ c >>= 2;
+ a >>= 1;
+ }
+ bit = 0;
+ b = 0x04;
+ c = 0x80;
+ for (i=0; i<3; i++) {
+ if (d3 & c)
+ bit |= b;
+ c >>= 2;
+ b >>= 1;
+ }
+ b = 0x01;
+ a = dat[add];
+ a ^= (b << bit);
+ dat[add] = a;
+ return 1;
+ } else {
+ i = 0;
+ while (d1) {
+ if (d1 & 0x01)
+ ++i;
+ d1 >>= 1;
+ }
+ while (d2) {
+ if (d2 & 0x01)
+ ++i;
+ d2 >>= 1;
+ }
+ while (d3) {
+ if (d3 & 0x01)
+ ++i;
+ d3 >>= 1;
+ }
+ if (i == 1) {
+ /* ECC Code Error Correction */
+ read_ecc[0] = calc_ecc[0];
+ read_ecc[1] = calc_ecc[1];
+ read_ecc[2] = calc_ecc[2];
+ return 2;
+ } else {
+ /* Uncorrectable Error */
+ return -1;
+ }
+ }
+ }
+
+ /* Should never happen */
+ return -1;
+}
+
+
//----------------------------------------------------------------------------
// Program Buffer
int
flash_program_buf(void* addr, void* data, int len)
{
volatile flash_data_t* ROM;
volatile flash_data_t* addr_ptr = (volatile flash_data_t*) addr;
volatile flash_data_t* data_ptr = (volatile flash_data_t*) data;
int res = FLASH_ERR_OK;
-
- int i;
- int cnt;
+ int i, cnt;
flash_data_t stat;
+ unsigned char oob[16];
ROM = (volatile flash_data_t*) CYGNUM_FLASH_BASE;
#if FLASH_DEBUG > 0
diag_printf("%s - addr: %x, data: %x, len: %d, FLASH: %p/%d\n",
__FUNCTION__, addr, data, len, ROM, sizeof(flash_data_t));
@@ -324,20 +525,27 @@ flash_program_buf(void* addr, void* data
}
CYGHWR_FLASH_TC58XXX_ALE(0);
#if FLASH_DEBUG > 1
diag_printf(">>\n");
#endif
+ // Caculate OOB data for page (ECC)
+ for (i = 0; i < 16; i++) {
+ oob[i] = 0xFF;
+ }
+ // Calculate ECC for page
+ _nand_page_ECC((unsigned char *)&data_ptr[0], &oob[0], &oob[1], &oob[2]);
+ _nand_page_ECC((unsigned char *)&data_ptr[256], &oob[3], &oob[6], &oob[7]);
// Move one page of data to buffer
for (i = 0; i < 512; i++) {
put_NAND(ROM, *data_ptr++);
#if FLASH_DEBUG > 1
if ((i % 16) == 15) diag_printf("\n");
#endif
}
// OOB data
for (i = 0; i < 16; i++) {
- put_NAND(ROM, 0xFF);
+ put_NAND(ROM, oob[i]);
#if FLASH_DEBUG > 1
if ((i % 16) == 15) diag_printf("\n");
#endif
}
#if FLASH_DEBUG > 1
@@ -346,10 +554,11 @@ flash_program_buf(void* addr, void* data
CYGHWR_FLASH_TC58XXX_CLE(1);
put_NAND(ROM, FLASH_Program);
CYGHWR_FLASH_TC58XXX_CLE(0);
CYGACC_CALL_IF_DELAY_US(1); // Actually 200ns
cnt = 0;
+ CYGACC_CALL_IF_DELAY_US(10);
while (!CYGHWR_FLASH_TC58XXX_RDY()) cnt++; // Wait for page data to be ready
CYGHWR_FLASH_TC58XXX_CLE(1);
put_NAND(ROM, FLASH_Status);
CYGHWR_FLASH_TC58XXX_CLE(0);
#if FLASH_DEBUG > 1
@@ -359,26 +568,35 @@ flash_program_buf(void* addr, void* data
CYGHWR_FLASH_TC58XXX_CE(0);
#if FLASH_DEBUG > 0
diag_printf("program at %x, stat: %x, count = %d\n", addr_ptr, stat, cnt);
#endif
addr_ptr += 512; len -= 512;
+ if (stat != 0xC0) {
+ diag_printf("Status after write: %x\n", stat);
+ if ((stat & 0x80) == 0x00) {
+ res = FLASH_ERR_PROTECT;
+ } else {
+ res = FLASH_ERR_PROGRAM;
+ }
+ }
}
return res;
}
//----------------------------------------------------------------------------
// Read data into buffer
int
flash_read_buf(void* addr, void* data, int len)
{
volatile flash_data_t* ROM;
- volatile flash_data_t dummy;
volatile flash_data_t* addr_ptr = (volatile flash_data_t*) addr;
volatile flash_data_t* data_ptr = (volatile flash_data_t*) data;
+ flash_data_t *page;
int res = FLASH_ERR_OK;
- int i;
- int cnt;
+ int i, cnt, offset;
+ flash_data_t stat;
+ unsigned char oob[16], dev_oob[16];
ROM = (volatile flash_data_t*) CYGNUM_FLASH_BASE;
#if FLASH_DEBUG > 1
diag_printf("<< ");
#endif
@@ -402,29 +620,71 @@ flash_read_buf(void* addr, void* data, i
CYGHWR_FLASH_TC58XXX_ALE(0);
#if FLASH_DEBUG > 1
diag_printf(">>\n");
#endif
cnt = 0;
+ CYGACC_CALL_IF_DELAY_US(10);
while (!CYGHWR_FLASH_TC58XXX_RDY()) cnt++; // Wait for page data to be ready
#if FLASH_DEBUG > 0
diag_printf("Read data starting at %p, count = %d\n", data_ptr, cnt);
#endif
+ offset = 0;
+ page = (unsigned char *)data_ptr;
while (len-- > 0) {
*data_ptr++ = *ROM;
- if (((unsigned long)data_ptr & 0x1FF) == 0) {
- // Data page has been read, skip over ECC/OOB data
+ if (++offset == 0x200) {
+ // Data page has been read, fetch ECC/OOB data
for (i = 0; i < 16; i++) {
- dummy = *ROM;
+ dev_oob[i] = *ROM;
+ }
+ // Calculate actual ECC on page
+ _nand_page_ECC(&page[0], &oob[0], &oob[1], &oob[2]);
+ _nand_page_ECC(&page[256], &oob[3], &oob[6], &oob[7]);
+ // Check & repair if possible
+ if ((oob[0] != dev_oob[0]) || (oob[1] != dev_oob[1]) || (oob[2] != dev_oob[2]) ||
+ (oob[3] != dev_oob[3]) || (oob[6] != dev_oob[6]) || (oob[7] != dev_oob[7])) {
+ unsigned char read_ecc[3], calc_ecc[3];
+ int res;
+
+ read_ecc[0] = dev_oob[0]; calc_ecc[0] = oob[0];
+ read_ecc[1] = dev_oob[1]; calc_ecc[1] = oob[1];
+ read_ecc[2] = dev_oob[2]; calc_ecc[2] = oob[2];
+ res = _nand_correct_data(&page[0], read_ecc, calc_ecc);
+ if ((res != 0) && (res != 1)) {
+ diag_printf("ECC failed\n");
+ res = FLASH_ERR_HWR;
+ break;
+ }
+ read_ecc[0] = dev_oob[3]; calc_ecc[0] = oob[3];
+ read_ecc[1] = dev_oob[6]; calc_ecc[1] = oob[6];
+ read_ecc[2] = dev_oob[7]; calc_ecc[2] = oob[7];
+ res = _nand_correct_data(&page[256], read_ecc, calc_ecc);
+ if ((res != 0) && (res != 1)) {
+ diag_printf("ECC failed\n");
+ res = FLASH_ERR_HWR;
+ break;
+ }
}
cnt = 0;
+ CYGACC_CALL_IF_DELAY_US(10);
while (!CYGHWR_FLASH_TC58XXX_RDY()) cnt++; // Wait for page data to be ready
#if FLASH_DEBUG > 0
diag_printf("Read data starting at %p, count = %d\n", data_ptr, cnt);
#endif
+ offset = 0;
+ page = (unsigned char *)data_ptr;
}
}
+ CYGHWR_FLASH_TC58XXX_CLE(1);
+ put_NAND(ROM, FLASH_Status);
+ CYGHWR_FLASH_TC58XXX_CLE(0);
+ stat = *ROM;
CYGHWR_FLASH_TC58XXX_CE(0);
+ if (stat != 0xC0) {
+ diag_printf("Status after read: %x\n", stat);
+ res = FLASH_ERR_HWR;
+ }
return res;
}
#endif // CYGONCE_DEVS_FLASH_TOSHIBA_TC58XXX_INL
Index: hal/powerpc/moab/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/ChangeLog,v
retrieving revision 1.16
diff -u -5 -p -r1.16 ChangeLog
--- hal/powerpc/moab/current/ChangeLog 26 Feb 2004 16:20:50 -0000 1.16
+++ hal/powerpc/moab/current/ChangeLog 24 Aug 2004 13:09:40 -0000
@@ -1,5 +1,14 @@
+2004-08-24 Gary Thomas <gary@mlbassoc.com>
+
+ * src/moab.S:
+ * sa_tests/tty.c:
+ * sa_tests/start.S:
+ * include/pkgconf/mlt_powerpc_moab_romram.h:
+ * cdl/hal_powerpc_moab.cdl: Support for new board revision. Minor
+ layout changes, change in RAM/FLASH sizes.
+
2004-02-26 Gary Thomas <gary@mlbassoc.com>
* misc/redboot_BOOT.ecm:
* cdl/hal_powerpc_moab.cdl: Use HAL_PLATFORM_EXTRA to display operating
mode of RedBoot (BOOT, NAND FLASH or RAM)
Index: hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl,v
retrieving revision 1.7
diff -u -5 -p -r1.7 hal_powerpc_moab.cdl
--- hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl 26 Feb 2004 16:20:50 -0000 1.7
+++ hal/powerpc/moab/current/cdl/hal_powerpc_moab.cdl 17 Aug 2004 12:21:39 -0000
@@ -100,26 +100,36 @@ cdl_package CYGPKG_HAL_POWERPC_MOAB {
run, either from RAM or ROM (flash) memory. ROM based applications
must be self contained, while RAM applications will typically assume
the existence of a debug environment, such as GDB stubs."
}
+ cdl_component CYG_HAL_MOAB_BOARD_REVISION {
+ display "PC revision"
+ flavor data
+ legal_values {"1_0" "1_1"}
+ default_value {"1_1"}
+ description "
+ This option describes the board (PC) revision. Certain changes were
+ made between the various revisions and this allows the kernel to adapt."
+ }
+
cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
display "Development board clock speed (MHz)"
flavor data
- legal_values 250 333
- default_value 250
+ legal_values 250 300 333 400
+ default_value { CYG_HAL_MOAB_BOARD_REVISION == "1_1" ? 400 : 250 }
description "
MOAB Development Boards have various system clock speeds
depending on the processor and oscillator fitted. Select
the clock speed appropriate for your board so that the system
can set the serial baud rate correctly, amongst other things."
}
cdl_option CYGHWR_HAL_POWERPC_MEM_SPEED {
display "Development board memory bus speed (MHz)"
flavor data
- legal_values 66
+ legal_values 66 100 133
default_value 66
description "
MOAB Development Boards have various system clock speeds
depending on the processor and oscillator fitted."
}
Index: hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h,v
retrieving revision 1.1
diff -u -5 -p -r1.1 mlt_powerpc_moab_romram.h
--- hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h 19 Sep 2003 17:11:28 -0000 1.1
+++ hal/powerpc/moab/current/include/pkgconf/mlt_powerpc_moab_romram.h 15 Aug 2004 12:26:44 -0000
@@ -6,14 +6,14 @@
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
#endif
#define CYGMEM_REGION_ram (0)
-#define CYGMEM_REGION_ram_SIZE (0x2000000)
+#define CYGMEM_REGION_ram_SIZE (0x4000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0xfff80000)
#define CYGMEM_REGION_rom_SIZE (0x80000)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
-#define CYGMEM_SECTION_heap1_SIZE (0x2000000 - (size_t) CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x4000000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/powerpc/moab/current/sa_tests/start.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/sa_tests/start.S,v
retrieving revision 1.1
diff -u -5 -p -r1.1 start.S
--- hal/powerpc/moab/current/sa_tests/start.S 19 Sep 2003 17:11:28 -0000 1.1
+++ hal/powerpc/moab/current/sa_tests/start.S 24 Aug 2004 13:09:17 -0000
@@ -1,17 +1,17 @@
//
// Simple test code framework
//
//-----------------------------------------------------------------
-// Copyright (C) 2003, Gary Thomas <gary@mlbassoc.com>
+// Copyright (C) 2003, 2004 Gary Thomas <gary@mlbassoc.com>
//-----------------------------------------------------------------
#include "ppc.inc"
-#define GPIO0 0xEF600700
-#define GPIO0_OR GPIO0+0x000
-#define GPIO0_TCR GPIO0+0x004
+#define GPIO0 (0xEF600700)
+#define GPIO0_OR (GPIO0+0x000)
+#define GPIO0_TCR (GPIO0+0x004)
.text
.globl start
start:
mfdcr r3,1018
@@ -25,17 +25,19 @@ start:
10: dccci 0,r3
addi r3,r3,16
cmpw r3,r4
bne 10b
+#if 0 // Assume that 'boot' environment has set this up
//
// Setup GPIO to drive LEDs
//
lwi r11,GPIO0_OR
li r4,0x80
stw r4,GPIO0_TCR-GPIO0(r11)
stw r4,GPIO0_OR-GPIO0(r11)
+#endif
// Setup and clear a stack used by the C code
lwi sp,stack_base-4
li r3,(stack-stack_base)/4
mtctr r3
Index: hal/powerpc/moab/current/sa_tests/tty.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/sa_tests/tty.c,v
retrieving revision 1.1
diff -u -5 -p -r1.1 tty.c
--- hal/powerpc/moab/current/sa_tests/tty.c 19 Sep 2003 17:11:28 -0000 1.1
+++ hal/powerpc/moab/current/sa_tests/tty.c 24 Aug 2004 13:09:30 -0000
@@ -1,10 +1,10 @@
//
// TTY support code
//
//-----------------------------------------------------------------
-// Copyright (C) 2003, Gary Thomas <gary@mlbassoc.com>
+// Copyright (C) 2003, 2004 Gary Thomas <gary@mlbassoc.com>
//-----------------------------------------------------------------
struct uart {
unsigned char rbr;
#define thr rbr
@@ -79,14 +79,16 @@ tty_init(void)
// Disable and clear FIFOs (need to enable to clear).
uart->fcr = (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2);
uart->fcr = 0;
+#if 0 // Assume that baud rate has been properly set
// Set speed to 38400.
uart->lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1 | SIO_LCR_DLAB;
uart->dll = 0x12;
uart->dlm = 0;
+#endif
// 8-1-no parity.
uart->lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1;
// Enable FIFOs (and clear them).
Index: hal/powerpc/moab/current/src/moab.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/moab/current/src/moab.S,v
retrieving revision 1.3
diff -u -5 -p -r1.3 moab.S
--- hal/powerpc/moab/current/src/moab.S 9 Dec 2003 02:45:36 -0000 1.3
+++ hal/powerpc/moab/current/src/moab.S 15 Aug 2004 12:26:44 -0000
@@ -7,11 +7,11 @@
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2002, 2003 Gary Thomas
+## Copyright (C) 2002, 2003, 2004 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -58,41 +58,64 @@
#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
#------------------------------------------------------------------------------
// No useable LEDs
-#define LED(x)
-
+#define LED(x)
+
+//
+// Various setup values - based on board revision &/or xtal speed
+//
+#if defined(CYG_HAL_MOAB_BOARD_REVISION_1_0)
+#define MOAB_DCR_SDRAM0_RTR 0x05F00000
+#define MOAB_DCR_SDRAM0_B1CR 0x00062001
+#define MOAB_DCR_SDRAM0_B0CR 0x02062001
+#define MOAB_DCR_SDRAM0_CFG 0x80800000
+#elif defined(CYG_HAL_MOAB_BOARD_REVISION_1_1)
+#define MOAB_DCR_SDRAM0_RTR 0x07F00000
+#define MOAB_DCR_SDRAM0_B1CR 0x00084001
+#define MOAB_DCR_SDRAM0_B0CR 0x00000000
+#define MOAB_DCR_SDRAM0_CFG 0x80800000
+#else
+#error "Illegal board revision"
+#endif
+#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250
+#define MOAB_DCR_CPC0_CR0 0x09F8502A
+#define MOAB_DCR_EBC0_B1AP 0x03840000
+#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
+#define MOAB_DCR_CPC0_CR0 0x09F8503A
+#define MOAB_DCR_EBC0_B1AP 0x05840000
+#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 300
+#define MOAB_DCR_CPC0_CR0 0x0FF85034
+#define MOAB_DCR_EBC0_B1AP 0x0A840000
+#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 400
+#define MOAB_DCR_CPC0_CR0 0x0FF8503C
+#define MOAB_DCR_EBC0_B1AP 0x0C840000
+#else
+#error "Illegal CPU speed"
+#endif
#------------------------------------------------------------------------------
FUNC_START( hal_hardware_init )
mflr r30 // Save return address
#ifndef CYG_HAL_STARTUP_RAM
li r3,0x00000000 // Make sure nothing is cacheable
mticcr r3
mtdccr r3
-
// Force data caches to be totally clean
lwi r3,0
lwi r4,0x8000
10: dcbf 0,r3
dccci 0,r3
addi r3,r3,16
cmpw r3,r4
bne 10b
// Basic chip configuration
-#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250
- lwi r3,0x09f8102a
- lwi r3,0x09f8502a
-#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
- lwi r3,0x09f8503a
-#else
-#error "Unsupported board/CPU speed"
-#endif
+ lwi r3,MOAB_DCR_CPC0_CR0
mtdcr DCR_CPC0_CR0,r3
li r3,0x00000000
mtdcr DCR_CPC0_CR1,r3
lwi r3,0x60606000 // Edge conditioning register
@@ -113,11 +136,11 @@ FUNC_START( hal_hardware_init )
stw r3,0(r4)
li r3,DCR_SDRAM0_CFG // See if SDRAM already configured
mtdcr DCR_SDRAM0_CFGADDR,r3
mfdcr r4,DCR_SDRAM0_CFGDATA
- lwi r3,0x80800000
+ lwi r3,MOAB_DCR_SDRAM0_CFG
and r4,r4,r3
cmpw r3,r4
beq sdram_ok
// DRAM controller
@@ -127,20 +150,21 @@ FUNC_START( hal_hardware_init )
mtdcr DCR_SDRAM0_CFGDATA,r4
li r3,DCR_SDRAM0_TR
lwi r4,0x010A800E
mtdcr DCR_SDRAM0_CFGADDR,r3
mtdcr DCR_SDRAM0_CFGDATA,r4
- li r3,DCR_SDRAM0_RTR
- lwi r4,0x05F00000
+ li r3,DCR_SDRAM0_RTR // Refresh timing
+ lwi r4,MOAB_DCR_SDRAM0_RTR
mtdcr DCR_SDRAM0_CFGADDR,r3
mtdcr DCR_SDRAM0_CFGDATA,r4
li r3,DCR_SDRAM0_B1CR // Note: non-ascending addresses because
- lwi r4,0x00062001 // the low 1/2 of memory fails on some boards
+ // the low 1/2 of memory fails on some boards
+ lwi r4,MOAB_DCR_SDRAM0_B1CR
mtdcr DCR_SDRAM0_CFGADDR,r3
mtdcr DCR_SDRAM0_CFGDATA,r4
li r3,DCR_SDRAM0_B0CR
- lwi r4,0x02062001
+ lwi r4,MOAB_DCR_SDRAM0_B0CR
mtdcr DCR_SDRAM0_CFGADDR,r3
mtdcr DCR_SDRAM0_CFGDATA,r4
lwi r4,GPIO_OR // Turn heartbeat LED on
lwi r3,0x00004000
@@ -150,11 +174,11 @@ FUNC_START( hal_hardware_init )
mtctr r3
13: nop
bdnz 13b
li r3,DCR_SDRAM0_CFG // Enable controller
- lwi r4,0x80800000
+ lwi r4,MOAB_DCR_SDRAM0_CFG
mtdcr DCR_SDRAM0_CFGADDR,r3
mtdcr DCR_SDRAM0_CFGDATA,r4
sdram_ok:
// Bus controller
@@ -165,18 +189,11 @@ sdram_ok:
li r3,DCR_EBC0_B0CR
lwi r4,0xFFE38000
mtdcr DCR_EBC0_CFGADDR,r3
mtdcr DCR_EBC0_CFGDATA,r4
li r3,DCR_EBC0_B1AP // MAIN FLASH at 0xCxxxxxxx, R/W
-#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250
- lwi r4,0x03840000 // Cycle time = 50ns
-#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
- lwi r4,0x05840000
-#else
- lwi r4,0x0C840000
-#error "Unsupported board/CPU speed"
-#endif
+ lwi r4,MOAB_DCR_EBC0_B1AP
mtdcr DCR_EBC0_CFGADDR,r3
mtdcr DCR_EBC0_CFGDATA,r4
li r3,DCR_EBC0_B1CR
lwi r4,0xC0018000 // 1MB, 8bits [actually only 1 byte!]
mtdcr DCR_EBC0_CFGADDR,r3
@@ -197,11 +214,11 @@ sdram_ok:
#endif // ROM or ROMRAM startup
lwi r3,0x80000001 // DRAM can be cached - instructions only
iccci 0,r3
mticcr r3
- li r3,0x00000000
+ lwi r3,0x00000000
mtdccr r3
#ifdef CYG_HAL_STARTUP_ROMRAM
// Copy image from ROM to RAM
mr r6,r30
Index: io/flash/current/cdl/io_flash.cdl
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/io/flash/current/cdl/io_flash.cdl,v
retrieving revision 1.17
diff -u -5 -p -r1.17 io_flash.cdl
--- io/flash/current/cdl/io_flash.cdl 20 Jun 2004 12:20:53 -0000 1.17
+++ io/flash/current/cdl/io_flash.cdl 24 Aug 2004 13:09:51 -0000
@@ -7,11 +7,11 @@
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2003 Gary Thomas
+## Copyright (C) 2003, 2004 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
@@ -191,8 +191,68 @@ cdl_package CYGPKG_IO_FLASH {
display "Name of FIS entry"
flavor data
default_value { "\"jffs2\"" }
}
}
+ }
+ }
+
+ cdl_component CYGPKG_IO_FLASH_OPTIONS {
+ display "Flash device driver build options"
+ flavor none
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+
+ cdl_option CYGPKG_IO_FLASH_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the flash device drivers. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_IO_FLASH_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the flash device drivers. These flags are removed from
+ the set of global flags if present."
+ }
+
+ cdl_component CYGPKG_IO_FLASH_TESTS {
+ display "Flash device driver tests"
+ flavor data
+ no_define
+ calculated { "tests/flash1" }
+ description "
+ This option specifies the set of tests for the flash device drivers."
+
+ cdl_option CYGNUM_IO_FLASH_TEST_OFFSET {
+ display "Start offset from flash base"
+ flavor data
+ default_value 0x100000
+ description "
+ This gives the offset from the base of flash where tests
+ can be run. It is important to set this correctly, as an
+ incorrect value could allow the tests to write over critical
+ portions of the FLASH device and possibly render the target
+ board totally non-functional."
+ }
+ cdl_option CYGNUM_IO_FLASH_TEST_LENGTH {
+ display "Length"
+ flavor data
+ default_value 0x100000
+ description "
+ This gives the length of the region of flash used for testing."
+ }
}
}
}
Index: hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm
===================================================================
RCS file: hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm
diff -N hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/moab/current/misc/moab1.1_redboot_BOOT.ecm 15 Aug 2004 12:26:44 -0000
@@ -0,0 +1,205 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware moab ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_POWERPC current ;
+ package -hardware CYGPKG_HAL_POWERPC_PPC40x current ;
+ package -hardware CYGPKG_HAL_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_FLASH_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ;
+ package -hardware CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_PPC405 current ;
+ package -hardware CYGPKG_DEVS_ETH_NS_DP83816 current ;
+ package -hardware CYGPKG_DEVS_ETH_PHY current ;
+ package -hardware CYGPKG_IO_PCI current ;
+ package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ;
+ package -hardware CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB current ;
+ package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ;
+ package -hardware CYGPKG_IO_SERIAL_POWERPC_PPC405 current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_NS_DNS current ;
+ package CYGPKG_IO_ETH_DRIVERS current ;
+ package CYGPKG_IO_WALLCLOCK current ;
+ package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_IO_ETH_DRIVERS_NUM_PKT {
+ user_value 32
+};
+
+cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
+ user_value 0
+};
+
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ inferred_value WRITETHRU
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_HAL_POWERPC_ENABLE_MMU {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS {
+ user_value 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYG_HAL_MOAB_BOARD_REVISION {
+ user_value 1_1
+};
+
+cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
+ user_value 400
+};
+
+cdl_option CYGHWR_HAL_POWERPC_MEM_SPEED {
+ user_value 133
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ inferred_value 2
+};
+
+cdl_option CYGNUM_REDBOOT_NETWORKING_MAX_PKTBUF {
+ user_value 8
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_STARTUP {
+ user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ user_value 0x00080000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ inferred_value 2048
+};
+
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ inferred_value EEPROM
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ inferred_value 64
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ inferred_value 256
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_REDBOOT_MODE {
+ user_value BOOT
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_IO_FLASH_CHATTER {
+ user_value 0
+};
+
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ inferred_value 0
+};
+
+cdl_component CYGSEM_DEVS_FLASH_POWERPC_MOAB_MAIN {
+ user_value 1
+};
+
+
Index: hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm
===================================================================
RCS file: hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm
diff -N hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/moab/current/misc/moab1.1_redboot_RAMF.ecm 15 Aug 2004 12:26:44 -0000
@@ -0,0 +1,169 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware moab ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_POWERPC current ;
+ package -hardware CYGPKG_HAL_POWERPC_PPC40x current ;
+ package -hardware CYGPKG_HAL_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_FLASH_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ;
+ package -hardware CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_PPC405 current ;
+ package -hardware CYGPKG_DEVS_ETH_NS_DP83816 current ;
+ package -hardware CYGPKG_DEVS_ETH_PHY current ;
+ package -hardware CYGPKG_IO_PCI current ;
+ package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ;
+ package -hardware CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB current ;
+ package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ;
+ package -hardware CYGPKG_IO_SERIAL_POWERPC_PPC405 current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_NS_DNS current ;
+ package CYGPKG_IO_FLASH current ;
+ package CYGPKG_IO_ETH_DRIVERS current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ inferred_value WRITETHRU
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_HAL_POWERPC_ENABLE_MMU {
+ user_value 0
+ inferred_value 0
+};
+
+cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
+ user_value 400
+};
+
+cdl_option CYGHWR_HAL_POWERPC_MEM_SPEED {
+ user_value 133
+};
+
+cdl_component CYGNUM_HAL_EEPROM_SIZE {
+ inferred_value 2048
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ inferred_value 2
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
+};
+
+cdl_option CYGOPT_REDBOOT_FIS {
+ user_value 0
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ user_value 0x00080000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ inferred_value 2048
+};
+
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ inferred_value EEPROM
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ inferred_value 64
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ inferred_value 256
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+cdl_component CYGSEM_DEVS_FLASH_POWERPC_MOAB_BOOT {
+ user_value 1
+};
+
+cdl_component CYGSEM_DEVS_FLASH_POWERPC_MOAB_MAIN {
+ user_value 0
+};
+
+
Index: hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm
===================================================================
RCS file: hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm
diff -N hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/powerpc/moab/current/misc/moab1.1_redboot_ROMRAM.ecm 15 Aug 2004 12:26:44 -0000
@@ -0,0 +1,197 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware moab ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_POWERPC current ;
+ package -hardware CYGPKG_HAL_POWERPC_PPC40x current ;
+ package -hardware CYGPKG_HAL_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_FLASH_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT49XXXX current ;
+ package -hardware CYGPKG_DEVS_FLASH_TOSHIBA_TC58XXX current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_MOAB current ;
+ package -hardware CYGPKG_DEVS_ETH_POWERPC_PPC405 current ;
+ package -hardware CYGPKG_DEVS_ETH_NS_DP83816 current ;
+ package -hardware CYGPKG_DEVS_ETH_PHY current ;
+ package -hardware CYGPKG_IO_PCI current ;
+ package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ;
+ package -hardware CYGPKG_DEVICES_WALLCLOCK_POWERPC_MOAB current ;
+ package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ;
+ package -hardware CYGPKG_IO_SERIAL_POWERPC_PPC405 current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_NS_DNS current ;
+ package CYGPKG_IO_ETH_DRIVERS current ;
+ package CYGPKG_IO_WALLCLOCK current ;
+ package CYGPKG_IO_FLASH current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_IO_ETH_DRIVERS_NUM_PKT {
+ user_value 32
+};
+
+cdl_option CYGSEM_IO_ETH_DRIVERS_WARN {
+ user_value 0
+};
+
+cdl_option CYGHWR_DEVS_ETH_PHY_DP83847 {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_DCACHE_STARTUP_MODE {
+ inferred_value WRITETHRU
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_POWERPC_RESET_USES_JUMP {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_HAL_POWERPC_ENABLE_MMU {
+ inferred_value 0
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYG_HAL_MOAB_BOARD_REVISION {
+ user_value 1_1
+};
+
+cdl_option CYGHWR_HAL_POWERPC_CPU_SPEED {
+ user_value 400
+};
+
+cdl_option CYGHWR_HAL_POWERPC_MEM_SPEED {
+ user_value 133
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MAX_MEM_SEGMENTS {
+ inferred_value 2
+};
+
+cdl_option CYGNUM_REDBOOT_NETWORKING_MAX_PKTBUF {
+ user_value 8
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_STARTUP {
+ user_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ user_value 0x00080000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_SIZE {
+ inferred_value 2048
+};
+
+cdl_option CYGHWR_REDBOOT_FLASH_CONFIG_MEDIA {
+ inferred_value EEPROM
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_STRING_SIZE {
+ inferred_value 64
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ inferred_value 256
+};
+
+cdl_option CYGSEM_REDBOOT_FLASH_CONFIG_READONLY_FALLBACK {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_IO_FLASH_CHATTER {
+ user_value 0
+};
+
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ inferred_value 0
+};
+
+cdl_component CYGSEM_DEVS_FLASH_POWERPC_MOAB_MAIN {
+ user_value 1
+};
+
+