Index: var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v
retrieving revision 1.23
diff -u -5 -p -r1.23 ChangeLog
--- var/current/ChangeLog	5 Oct 2004 08:36:35 -0000	1.23
+++ var/current/ChangeLog	6 Oct 2004 07:03:27 -0000
@@ -1,5 +1,9 @@
+2004-10-06  Andrea Michelotti <amichelotti@atmel.com>
+	* include/var_io.h:protected PDC/SPI DMA registers from redefinition.
+	
+	
 2004-10-05  Savin Zlobec <savin@elatec.si>
 
 	* include/var_io.h: Added definitions for AT91M55800A SPI and PIO
 	pins.
 
Index: var/current/include/var_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v
retrieving revision 1.10
diff -u -5 -p -r1.10 var_io.h
--- var/current/include/var_io.h	5 Oct 2004 08:36:38 -0000	1.10
+++ var/current/include/var_io.h	6 Oct 2004 07:03:33 -0000
@@ -742,14 +742,24 @@
 #define AT91_SPI_SR_ENDTX      0x00000020        // End of Transmitter Transfer
 #define AT91_SPI_SR_SPIENS     0x00010000        // SPI Enable Status
 #define AT91_SPI_IER           0x14              // Interrupt Enable Register
 #define AT91_SPI_IDR           0x18              // Interrupt Disable Register
 #define AT91_SPI_IMR           0x1C              // Interrupt Mask Register
+// DMA registers are PDC registers
+// can be different from target to target
+#ifndef AT91_SPI_RPR
 #define AT91_SPI_RPR           0x20              // Receive Pointer Register
+#endif
+#ifndef AT91_SPI_RCR
 #define AT91_SPI_RCR           0x24              // Receive Counter Register
+#endif
+#ifndef AT91_SPI_TPR
 #define AT91_SPI_TPR           0x28              // Transmit Pointer Register
+#endif
+#ifndef AT91_SPI_TCR
 #define AT91_SPI_TCR           0x2C              // Transmit Counter Register
+#endif
 #define AT91_SPI_CSR0          0x30              // Chip Select Register 0
 #define AT91_SPI_CSR1          0x34              // Chip Select Register 1
 #define AT91_SPI_CSR2          0x38              // Chip Select Register 2
 #define AT91_SPI_CSR3          0x3C              // Chip Select Register 3
 #define AT91_SPI_CSR_CPOL      0x00000001        // Clock Polarity
Index: jtst/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/jtst/current/ChangeLog,v
retrieving revision 1.2
diff -u -5 -p -r1.2 ChangeLog
--- jtst/current/ChangeLog	5 Oct 2004 12:51:18 -0000	1.2
+++ jtst/current/ChangeLog	6 Oct 2004 07:03:33 -0000
@@ -1,5 +1,9 @@
+2004-10-6  Andrea Michelotti  <amichelotti@atmel.com>
+
+	* include/plf_io.h: removed SPI definitions.
+
 2004-10-4  Andrea Michelotti  <amichelotti@atmel.com>
 
 	* include/hal_platform_setup.h: added generation of three
 	different clocks for watchdog.
 	
Index: jtst/current/include/plf_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/jtst/current/include/plf_io.h,v
retrieving revision 1.1
diff -u -5 -p -r1.1 plf_io.h
--- jtst/current/include/plf_io.h	25 Sep 2004 09:46:19 -0000	1.1
+++ jtst/current/include/plf_io.h	6 Oct 2004 07:03:33 -0000
@@ -96,56 +96,10 @@
 
 #define AT91_PDC_PTCR_TXDIS  0x200
 #define AT91_PDC_PTCR_RXDIS  0x2
 
 
-// SPI interface
-#define AT91_SPI_CR     0x0  // control register
-#define AT91_SPI_CR_DIS 0x2  // disable SP
-#define AT91_SPI_CR_EN  0x1  // enable SPI
-#define AT91_SPI_CR_RST 0x80 // SW reset SPI
-#define AT91_SPI_MR     0x4  // mode register
-#define AT91_SPI_RDR    0x8  // receive data register
-#define AT91_SPI_TDR    0x8  // trasmit data register
-#define AT91_SPI_SR     0x10 // status register
-#define AT91_SPI_IER    0x14 // interrupt register
-#define AT91_SPI_IDR    0x18 // interrupt disable register
-#define AT91_SPI_IMR    0x1C // interrupt mask register
-#define AT91_SPI_CSR0   0x30 // chip select 0
-#define AT91_SPI_CSR1   0x34 // chip select 1
-#define AT91_SPI_CSR2   0x38 // chip select 2
-#define AT91_SPI_CSR3   0x3C // chip select 3
-// interrupts mask
-#define AT91_SPI_INT_RDRF   0x1
-#define AT91_SPI_INT_TDRE   0x2
-#define AT91_SPI_INT_MODF   0x4
-#define AT91_SPI_INT_OVRE   0x8
-#define AT91_SPI_INT_ENDRX  0x10
-#define AT91_SPI_INT_ENDTX  0x20
-#define AT91_SPI_INT_RXBUFF 0x40
-#define AT91_SPI_INT_TXBUFF 0x80
-
-//
-#define AT91_SPI_BIT_WIDTH_8  0x0
-#define AT91_SPI_BIT_WIDTH_9  0x1
-#define AT91_SPI_BIT_WIDTH_10 0x2
-#define AT91_SPI_BIT_WIDTH_11 0x3
-#define AT91_SPI_BIT_WIDTH_12 0x4
-#define AT91_SPI_BIT_WIDTH_13 0x5
-#define AT91_SPI_BIT_WIDTH_14 0x6
-#define AT91_SPI_BIT_WIDTH_15 0x7
-#define AT91_SPI_BIT_WIDTH_16 0x8
-
-#define AT91_SPI_DATA_CHANGE_HILO 0
-#define AT91_SPI_DATA_CHANGE_LOHI 1
-
-
-#define AT91_SPI_CLK_PHASE_HI  0
-#define AT91_SPI_CLK_PHASE_LOW 1
-
-
-
 // CLOCK divider interface
 
 #define AT91_CLKGEN_CPTMAX0    0x0 //counter 0
 #define AT91_CLKGEN_CPTMAX1    0x4 //counter 1
 #define AT91_CLKGEN_CPTMAX2    0x8 //..
