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Philips LPC2xxx variant port


Hello,

LPC2XXX variant tested with MCB2100 Keil board.Basic support so far (RedBoot, hal_diag,
ROM startup) no flash.

It is not based on the LPC2104 port which is in bugzilla pending assignment.(found out
about that after I started porting)

I'd appreciate comments/testing.
MCB2100 platform port, wd and serial drivers follow in upcoming patches.

thanks
Jani

--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/ChangeLog
@@ -0,0 +1,46 @@
+2004-09-12  Jani Monoses <jani@iv.ro>
+
+	* src/hal_diag.c: 
+	* src/lpc2xxx_misc.c: 
+	* include/plf_stub.h: 
+	* include/var_io.h: 
+	* include/var_arch.h: 
+	* include/hal_var_ints.h: 
+	* include/hal_diag.h: 
+	* include/hal_cache.h: 
+	* cdl/hal_arm_lpc2xxx.cdl: New port - based on AT91 variant.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl
@@ -0,0 +1,225 @@
+# ====================================================================
+#
+#      hal_arm_lpc.cdl
+#
+#      Philips LPC2XXX HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Contributors:   gthomas, tkoeller, tdrury, nickg
+# Date:           2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ARM_LPC2XXX {
+    display       "Philips LPC2XXX variant HAL"
+    parent        CYGPKG_HAL_ARM
+    define_header hal_arm_lpc2xxx.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The LPC2XXX HAL package provides the support needed to run
+        eCos on Philips LPC2XXX based targets."
+
+    compile       hal_diag.c lpc2xxx_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+    implements    CYGINT_HAL_ARM_ARCH_ARM7
+    implements    CYGINT_HAL_ARM_THUMB_ARCH
+
+    # Let the architectural HAL see this variant's files
+    define_proc {
+        puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+        puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_ARCH_H"
+    }
+
+    cdl_option CYGHWR_HAL_ARM_LPC2XXX {
+        display        "LPC2XXX variant used"
+        flavor         data
+        default_value  {"LPC2129"}
+        legal_values   {"LPC2104" "LPC2105" "LPC2106" 
+			"LPC2114" "LPC2119" "LPC2124" "LPC2129" "LPC2132" "LPC2138" "LPC2194"
+			"LPC2212" "LPC2214" "LPC2290" "LPC2292" "LPC2294"}
+        description    "The LPC2XXX microcontroller family has several variants,
+                        the main differences being the amount of on-chip RAM,
+	                flash and peripherals. This option allows the
+                        platform HALs to select the specific microcontroller
+                        being used."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value ((CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED) / CYGNUM_HAL_RTC_DENOMINATOR)
+        }
+    }
+    
+    # Real-time clock/counter specifics
+    cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+        display       "CPU clock speed"
+        flavor        data
+        default_value {60000000}
+    }
+
+ 
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+    
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+
+        }
+    }
+
+}
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/hal_cache.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):  jani 
+// Contributors:
+// Date:        2004-09-08
+// Purpose:     Cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+//              cache control operations.
+// Usage:
+//              #include <cyg/hal/hal_cache.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/hal_diag.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas, tkoeller
+// Date:        2001-07-12
+// Purpose:     HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage:       #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+//-----------------------------------------------------------------------------
+// LED
+externC void hal_diag_led(int mask);
+
+externC void hal_lpc2xxx_set_leds(int mask);
+
+//-----------------------------------------------------------------------------
+// delay
+
+externC void hal_delay_us(cyg_int32 usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n);
+
+//-----------------------------------------------------------------------------
+// reset
+
+extern void hal_lpc2xxx_reset_cpu(void);
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/hal_var_ints.h
@@ -0,0 +1,108 @@
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+//      hal_var_ints.h
+//
+//      HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jani 
+// Contributors: 
+// Date:         2004-09-12
+// Purpose:      Define Interrupt support
+// Description:  The interrupt details for the LPC2XXX are defined here.
+// Usage:
+//		 #include <pkgconf/system.h>
+//		 #include CYGBLD_HAL_VARIANT_H
+//               #include CYGBLD_HAL_VAR_INTS_H
+//
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+
+#define CYGNUM_HAL_INTERRUPT_WD      0
+#define CYGNUM_HAL_INTERRUPT_SOFT    1
+#define CYGNUM_HAL_INTERRUPT_DCC_RX  2
+#define CYGNUM_HAL_INTERRUPT_DCC_TX  3
+#define CYGNUM_HAL_INTERRUPT_TIMER0  4
+#define CYGNUM_HAL_INTERRUPT_TIMER1  5
+#define CYGNUM_HAL_INTERRUPT_UART0   6
+#define CYGNUM_HAL_INTERRUPT_UART1   7
+#define CYGNUM_HAL_INTERRUPT_PWM0    8
+#define CYGNUM_HAL_INTERRUPT_I2C     9
+#define CYGNUM_HAL_INTERRUPT_SPI0    10
+#define CYGNUM_HAL_INTERRUPT_SPI1    11
+#define CYGNUM_HAL_INTERRUPT_PLL     12
+#define CYGNUM_HAL_INTERRUPT_RTCDEV  13	//actual RTC device not the eCos 'real time clock' interrupt. The latter is on TIMER0.
+#define CYGNUM_HAL_INTERRUPT_EINT0   14
+#define CYGNUM_HAL_INTERRUPT_EINT1   15
+#define CYGNUM_HAL_INTERRUPT_EINT2   16
+#define CYGNUM_HAL_INTERRUPT_EINT3   17
+
+#define CYGNUM_HAL_INTERRUPT_AD      18 
+
+#define CYGNUM_HAL_INTERRUPT_CAN     19
+
+#define CYGNUM_HAL_INTERRUPT_CAN1_TX    20 
+#define CYGNUM_HAL_INTERRUPT_CAN2_TX    21 
+#define CYGNUM_HAL_INTERRUPT_CAN3_TX    22
+#define CYGNUM_HAL_INTERRUPT_CAN4_TX    23
+
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX    26
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX    27
+#define CYGNUM_HAL_INTERRUPT_CAN3_RX    28
+#define CYGNUM_HAL_INTERRUPT_CAN4_RX    29
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX           (31)
+
+#define CYGNUM_HAL_ISR_COUNT            (CYGNUM_HAL_ISR_MAX+1)
+
+//The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_TIMER0
+
+__externC void hal_lpc_watchdog_reset(void);
+#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0
+
+#endif // CYGONCE_HAL_VAR_INTS_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/plf_stub.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas
+// Date:        2001-07-12
+// Purpose:     Platform HAL stub support for LPC2XXX based boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/arm_stub.h>           // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/var_arch.h
@@ -0,0 +1,78 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      LPC2XXX variant architecture overrides
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Jonathan Larmour <jifl@eCosCentric.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting the copyright
+// holders.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: Daniel Neri
+// Date:         2003-06-24
+// Purpose:      LPC2XXX variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. These implementations halt the system core clock.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+
+
+#define HAL_IDLE_THREAD_ACTION(_count_)                       \
+CYG_MACRO_START                                               \
+/*HAL_WRITE_UINT32(LPC_SCB + LPC_SCB_PCON, LPC_SCB_PCON_IDL); */  \
+CYG_MACRO_END
+
+
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/include/var_io.h
@@ -0,0 +1,286 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jani
+// Contributors:
+// Date:        2004-09-08
+// Purpose:     LPC2XXX variant specific registers
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/hal/plf_io.h>
+
+//AHB and VPB peripheral devices' base addresses
+
+#define LPC_PERIPHERAL_SIZE	0x00004000
+#define LPC_DEVICE(base, n) (base + n * LPC_PERIPHERAL_SIZE)
+
+#define LPC_VPB_BASE	0xE0000000
+#define LPC_VPB_DEVICE(n)	LPC_DEVICE(LPC_VPB_BASE, n)
+#define LPC_AHB_BASE	0xFFE00000
+#define LPC_AHB_DEVICE(n)	LPC_DEVICE(LPC_AHB_BASE, n)
+
+#define LPC_WD		LPC_VPB_DEVICE(0)
+#define LPC_TIMER0	LPC_VPB_DEVICE(1)
+#define LPC_TIMER1	LPC_VPB_DEVICE(2)
+#define LPC_UART0	LPC_VPB_DEVICE(3)
+#define LPC_UART1	LPC_VPB_DEVICE(4)
+#define LPC_PWM0	LPC_VPB_DEVICE(5)
+#define LPC_UNUSED	LPC_VPB_DEVICE(6)
+#define LPC_I2C		LPC_VPB_DEVICE(7)
+#define LPC_SPI0	LPC_VPB_DEVICE(8)
+#define LPC_RTC		LPC_VPB_DEVICE(9)
+#define LPC_GPIO	LPC_VPB_DEVICE(10)
+#define LPC_PCB		LPC_VPB_DEVICE(11)
+#define LPC_SPI1	LPC_VPB_DEVICE(12)
+#define LPC_AD		LPC_VPB_DEVICE(13)
+//...
+#define LPC_SCB		LPC_VPB_DEVICE(127)
+
+
+#define LPC_EMC		LPC_AHB_DEVICE(0)
+
+//Device register offsets
+
+//VPB devices
+
+//Pin Control Block
+#define LPC_PCB_PINSEL0 (LPC_PCB + 0x00)
+#define LPC_PCB_PINSEL1 (LPC_PCB + 0x04)
+#define LPC_PCB_PINSEL2 (LPC_PCB + 0x14)
+
+//GPIO
+
+#define LPC_GPIO0	(LPC_GPIO + 0x00)
+#define LPC_GPIO1	(LPC_GPIO + 0x10)
+#define LPC_GPIO2	(LPC_GPIO + 0x20)
+#define LPC_GPIO3	(LPC_GPIO + 0x30)
+
+#define LPC_GPIO_IOPIN	0x00
+#define LPC_GPIO_IOSET	0x04
+#define LPC_GPIO_IODIR	0x08
+#define LPC_GPIO_IOCLR	0x0C
+
+//Watchdog
+#define LPC_WD_MOD	0x00
+	#define LPC_WD_MOD_WDEN		(1<<0)
+	#define LPC_WD_MOD_WDRESET	(1<<1)
+	#define LPC_WD_MOD_WDTOF	(1<<2)
+	#define LPC_WD_MOD_WDINT	(1<<3)
+#define LPC_WD_TC	0x04
+#define LPC_WD_FEED	0x08
+#define LPC_WD_TV	0x0C
+
+//Timer
+#define LPC_TIMER_IR	0x00 
+	#define LPC_TIMER_IR_MR0	0x01
+	#define LPC_TIMER_IR_MR1	0x02
+	#define LPC_TIMER_IR_MR2	0x04
+	#define LPC_TIMER_IR_MR3	0x08
+	#define LPC_TIMER_IR_CR0	0x10
+	#define LPC_TIMER_IR_CR1	0x20
+	#define LPC_TIMER_IR_CR2	0x40
+	#define LPC_TIMER_IR_CR3	0x80
+#define LPC_TIMER_TCR	0x04
+	#define LPC_TIMER_TCR_ENABLE	0x01
+	#define LPC_TIMER_TCR_RESET	0x02
+
+#define LPC_TIMER_TC	0x08 
+#define LPC_TIMER_PR	0x0C
+#define LPC_TIMER_PC	0x10 
+#define LPC_TIMER_MCR	0x14			//control the actions triggered by a match of TC with 
+						//any of the four match registers
+	#define LPC_TIMER_MCR_INT0  (1<<0)
+	#define LPC_TIMER_MCR_RST0  (1<<1)
+	#define LPC_TIMER_MCR_STOP0 (1<<2)
+	#define LPC_TIMER_MCR_INT1  (1<<3)
+	#define LPC_TIMER_MCR_RST1  (1<<4)
+	#define LPC_TIMER_MCR_STOP1 (1<<5)
+	#define LPC_TIMER_MCR_INT2  (1<<6)
+	#define LPC_TIMER_MCR_RST2  (1<<7)
+	#define LPC_TIMER_MCR_STOP2 (1<<8)
+	#define LPC_TIMER_MCR_INT3  (1<<9)
+	#define LPC_TIMER_MCR_RST3  (1<<10)
+	#define LPC_TIMER_MCR_STOP3 (1<<11)
+
+#define LPC_TIMER_MR0	0x18 
+#define LPC_TIMER_MR1	0x1C 
+#define LPC_TIMER_MR2	0x20 
+#define LPC_TIMER_MR3	0x24 
+#define LPC_TIMER_CCR	0x28 
+#define LPC_TIMER_CR0	0x2C 
+#define LPC_TIMER_CR1	0x30 
+#define LPC_TIMER_CR2	0x34 
+#define LPC_TIMER_CR3	0x38 
+#define LPC_TIMER_EMR	0x3C 
+
+//16x5x compatible UART
+#define LPC_UART_RBR	0x00
+#define LPC_UART_THR	0x00
+#define LPC_UART_DLL	0x00
+#define LPC_UART_DLM	0x04
+#define LPC_UART_IER	0x04
+	#define LPC_UART_IER_RBR    0x00
+	#define LPC_UART_IER_THRE   0x01
+	#define LPC_UART_IER_RX_LS  0x02
+
+#define LPC_UART_IIR	0x08
+#define LPC_UART_FCR	0x08
+	#define LPC_UART_FCR_ENABLE 0x01
+	#define LPC_UART_FCR_RXRST  0x02
+	#define LPC_UART_FCR_TXRST  0x04
+#define LPC_UART_LCR		0x0C
+	#define LPC_UART_LCR_LENGTH_5	(0<<0)
+	#define LPC_UART_LCR_LENGTH_6	(1<<0)
+	#define LPC_UART_LCR_LENGTH_7	(2<<0)
+	#define LPC_UART_LCR_LENGTH_8	(3<<0)
+
+	#define LPC_UART_LCR_STOP_1	(0<<2)
+	#define LPC_UART_LCR_STOP_2	(1<<2)
+
+	#define LPC_UART_LCR_PARITY_NONE	(0<<3)
+	#define LPC_UART_LCR_PARITY_ODD		(1<<3)
+	#define LPC_UART_LCR_PARITY_EVEN	(3<<3)
+	#define LPC_UART_LCR_PARITY_1		(5<<3)
+	#define LPC_UART_LCR_PARITY_0		(7<<3)
+
+	#define LPC_UART_LCR_DLAB_EN	(1 << 7)
+
+#define LPC_UART_MCR	0x10
+
+#define LPC_UART_LSR	0x14
+	#define LPC_UART_LSR_RDR	(1<<0)
+	#define LPC_UART_LSR_OE		(1<<1)
+	#define LPC_UART_LSR_PE		(1<<2)
+	#define LPC_UART_LSR_FE		(1<<3)
+	#define LPC_UART_LSR_BI		(1<<4)
+	#define LPC_UART_LSR_THRE	(1<<5)
+	#define LPC_UART_LSR_TEMP	(1<<6)
+	#define LPC_UART_LSR_RXFE	(1<<7)
+
+#define LPC_UART_MSR	0x08
+#define LPC_UART_SRC	0x1C
+
+//I2C
+#define LPC_I2C_CONSET	0x00
+#define LPC_I2C_STAT	0x04
+#define LPC_I2C_DAT	0x08
+#define LPC_I2C_ADR	0x0C
+#define LPC_I2C_SCLH	0x10
+#define LPC_I2C_SCLL	0x14
+#define LPC_I2C_CONCLR	0x18
+
+//SPI
+#define LPC_SPI_SPCR	0x00
+#define LPC_SPI_SPSR	0x04
+#define LPC_SPI_SPDR	0x08
+#define LPC_SPI_SPCCR	0x0C
+#define LPC_SPI_SPINT	0x1C
+#define LPC_SPI_SPCR	0x00
+#define LPC_SPI_SPCR	0x00
+
+//CAN
+//ADC
+
+//System control block
+
+#define LPC_SCB_MAMCR	0x00
+#define LPC_SCB_MAMTIM	0x04
+
+#define LPC_SCB_MEMMAP	0x40
+	#define LPC_SCB_MEMMAP_BOOT 	0x00
+	#define LPC_SCB_MEMMAP_FLASH	0x01
+	#define LPC_SCB_MEMMAP_RAM	0x02
+	#define LPC_SCB_MEMMAP_EXT	0x03
+
+#define LPC_SCB_PLLCON	0x80
+#define LPC_SCB_PLLCFG	0x84
+#define LPC_SCB_PLLSTAT	0x88
+#define LPC_SCB_PLLFEED	0x8C
+
+#define LPC_SCB_PCON	0xC0
+	#define LPC_SCB_PCON_IDL	(1<<0)
+	#define LPC_SCB_PCON_PD		(1<<1)
+#define LPC_SCB_PCONP	0xC4
+
+#define LPC_SCB_VPBDIV	0x100
+
+#define LPC_SCB_EXTINT	0x140
+#define LPC_SCB_EXTWAKE	0x144
+#define LPC_SCB_EXTMODE	0x148
+#define LPC_SCB_EXTPOL	0x14C
+
+//AHB devices
+
+//External memory controller
+#define LPC_EMC_BCFG0	0x00
+#define LPC_EMC_BCFG1	0x04
+#define LPC_EMC_BCFG2	0x08
+#define LPC_EMC_BCFG3	0x0C
+
+//Vectored interrupt controller at the upper 4K of the 4G address space
+
+#define LPC_VIC		0xFFFFF000
+#define LPC_VIC_IRQSTATUS	0x00
+#define LPC_VIC_FIQSTATUS	0x04
+#define LPC_VIC_RAWINT		0x08
+#define LPC_VIC_INTSELECT	0x0C
+#define LPC_VIC_INTEN		0x10
+#define LPC_VIC_INTENCLR	0x14
+#define LPC_VIC_SOFTINT		0x18
+#define LPC_VIC_SOFTINTCLR	0x1C
+#define LPC_VIC_PROTECTION	0x20
+#define LPC_VIC_VECTADDR	0x30
+#define LPC_VIC_DEFVECTADDR	0x34
+#define LPC_VIC_VECTADDR0	0x100
+#define LPC_VIC_VECTCNTL0	0x200
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/src/hal_diag.c
@@ -0,0 +1,341 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas
+// Date:        2001-07-12
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h>             // USART registers
+
+//-----------------------------------------------------------------------------
+typedef struct {
+    cyg_uint8* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+    int baud_rate;
+} channel_data_t;
+
+//-----------------------------------------------------------------------------
+//Baud rate depends on the peripheral clock which is the core clock
+//divided by 1, 2 or 4 as reflected by the VPBDIV register
+extern cyg_uint32 lpc_pclk,lpc_cclk;
+int
+cyg_var_baud_generator(int baud)
+{
+    return lpc_pclk/(baud*16);
+}
+
+static void
+cyg_hal_plf_serial_init_channel(void* __ch_data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8* base = chan->base;
+    cyg_uint16 divider = lpc_pclk/(chan->baud_rate*16);
+    //Set baudrate
+    HAL_WRITE_UINT32(base+LPC_UART_LCR, LPC_UART_LCR_DLAB_EN);
+    HAL_WRITE_UINT32(base+LPC_UART_DLM, divider >> 8);
+    HAL_WRITE_UINT32(base+LPC_UART_DLL, divider & 0xFF);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT32(base+LPC_UART_LCR, LPC_UART_LCR_LENGTH_8 |
+                         LPC_UART_LCR_PARITY_NONE | LPC_UART_LCR_STOP_1);
+
+    // Reset and enable FIFO
+    HAL_WRITE_UINT32(base+LPC_UART_FCR, LPC_UART_FCR_ENABLE |
+		    LPC_UART_FCR_RXRST | LPC_UART_FCR_TXRST);
+}
+
+void
+cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    cyg_uint8 stat;
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT32(base+LPC_UART_LSR, stat);
+    } while ((stat & LPC_UART_LSR_THRE) == 0);
+
+    HAL_WRITE_UINT32(base+LPC_UART_THR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8* base = chan->base;
+    cyg_uint8 stat;
+
+    HAL_READ_UINT32(base+LPC_UART_LSR, stat);
+    if ((stat & LPC_UART_LSR_RDR) == 0)
+        return false;
+
+    HAL_READ_UINT32(base+LPC_UART_RBR, *ch);
+
+    return true;
+}
+
+cyg_uint8
+cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+static void
+cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+        
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int
+cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
+    int ret = 0;
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        cyg_hal_plf_serial_init_channel(chan);
+        ret = 0;
+        break;
+    case __COMMCTL_IRQ_ENABLE:
+        irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base+LPC_UART_IER, LPC_UART_IER_RBR);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base+LPC_UART_IER, 0);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+    default:
+        break;
+    }
+
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    int res = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_uint8 c;
+    cyg_uint8 stat;
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+    HAL_READ_UINT32(chan->base+LPC_UART_LSR, stat);
+    if ( (stat & LPC_UART_LSR_RDR) != 0 ) {
+
+        HAL_READ_UINT32(chan->base+LPC_UART_RBR, c);
+        if( cyg_hal_is_break( &c , 1 ) )
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static channel_data_t lpc2xxx_ser_channels[2] = {
+    { (cyg_uint8*)LPC_UART0, 1000, CYGNUM_HAL_INTERRUPT_UART0, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+    { (cyg_uint8*)LPC_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}
+};
+
+static void
+cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur;
+
+    cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    // Init channels
+    cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[0]);
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+    cyg_hal_plf_serial_init_channel(&lpc2xxx_ser_channels[1]);
+#endif
+
+    // Setup procs in the vector table
+
+    // Set channel 0
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[0]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
+    // Set channel 1
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+    CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc2xxx_ser_channels[1]);
+    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+#endif
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+	
+    if (initialized)
+        return;
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+
+void
+hal_diag_led(int mask)
+{
+    hal_lpc2xxx_set_leds(mask);
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
--- /dev/null
+++ /home/jani/work/ecoswork/cvs/,,what-changed.ecos--official--2.1--patch-30--jani@iv.ro--ecos/new-files-archive/./packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
@@ -0,0 +1,302 @@
+/*==========================================================================
+//
+//      lpc_misc.c
+//
+//      HAL misc variant support code for Philips LPC2XXX
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, jskov, nickg, tkoeller
+// Date:         2001-07-12
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // necessary?
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h>             // calling interface
+#include <cyg/hal/hal_misc.h>           // helper functions
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+#include <cyg/hal/drv_api.h>            // HAL ISR support
+#endif
+#include <cyg/hal/var_io.h>             // platform registers
+
+cyg_uint32 lpc_cclk;	//CPU clock frequency
+cyg_uint32 lpc_pclk;	//peripheral devices clock speed (equal to, half, or quarter of CPU clock)
+
+// -------------------------------------------------------------------------
+// Clock support
+// Use TIMER0
+static cyg_uint32 _period;
+
+void hal_clock_initialize(cyg_uint32 period)
+{
+    CYG_ADDRESS timer = LPC_TIMER0;
+
+    period = period/(lpc_cclk/lpc_pclk);
+
+    // Disable and reset counter
+    HAL_WRITE_UINT32(timer+LPC_TIMER_TCR, 2);
+    
+    //set prescale register to 0
+    HAL_WRITE_UINT32(timer+LPC_TIMER_PR, 0);
+
+    // Set up match register 
+    HAL_WRITE_UINT32(timer+LPC_TIMER_MR0, period);
+    
+    //Reset and generate interrupt on match
+    HAL_WRITE_UINT32(timer+LPC_TIMER_MCR, LPC_TIMER_MCR_INT0 | LPC_TIMER_MCR_RST0);
+
+    // Enable counter
+    HAL_WRITE_UINT32(timer+LPC_TIMER_TCR, 1);
+}
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+    CYG_ADDRESS timer = LPC_TIMER0;
+
+    HAL_WRITE_UINT32(timer+LPC_TIMER_IR, LPC_TIMER_IR_MR0);  // Clear interrupt
+
+    if (period != _period) {
+        hal_clock_initialize(period);
+    }
+    _period = period;
+
+}
+
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+    CYG_ADDRESS timer = LPC_TIMER0;
+    cyg_uint32 val;
+
+    HAL_READ_UINT32(timer+LPC_TIMER_TC, val);
+    *pvalue = val;
+}
+
+// -------------------------------------------------------------------------
+//
+// Delay for some number of micro-seconds
+// use TIMER1
+//
+void hal_delay_us(cyg_int32 usecs)
+{
+    CYG_ADDRESS timer = LPC_TIMER1;
+    cyg_uint32 stat;
+    cyg_uint64 ticks;
+
+    // Calculate how many timer ticks the required number of
+    // microseconds equate to. We do this calculation in 64 bit
+    // arithmetic to avoid overflow.
+    ticks = (((cyg_uint64)usecs) * ((cyg_uint64)lpc_pclk))/1000000LL;
+    
+    // Disable and reset counter
+    HAL_WRITE_UINT32(timer+LPC_TIMER_TCR, 2);
+    
+    //Stop on match
+    HAL_WRITE_UINT32(timer+LPC_TIMER_MR0, ticks);
+    HAL_WRITE_UINT32(timer+LPC_TIMER_MCR, LPC_TIMER_MCR_STOP0 | LPC_TIMER_MCR_RST0);
+
+    //set prescale register to 0
+    HAL_WRITE_UINT32(timer+LPC_TIMER_PR, 0);			
+
+    // Enable counter
+    HAL_WRITE_UINT32(timer+LPC_TIMER_TCR, 1);
+
+    // Wait for the match
+    do {
+        HAL_READ_UINT32(timer+LPC_TIMER_TC, stat);
+    } while (stat < ticks);
+}
+
+// -------------------------------------------------------------------------
+// Hardware init
+
+
+
+//Return value of VPBDIV register. According to errata doc
+//we need to read twice consecutively to get correct value
+//So mark as volatile so gcc does not optimize the second read away
+cyg_uint32 lpc_get_vpbdiv(void)
+{   
+    volatile cyg_uint32 div;	
+    HAL_READ_UINT32(LPC_SCB + LPC_SCB_VPBDIV, div);
+    HAL_READ_UINT32(LPC_SCB + LPC_SCB_VPBDIV, div);
+
+    return div;
+}
+
+//Set the two bits in VPBDIV which control peripheral clock division
+//div must be 1,2 or 4
+void lpc_set_vpbdiv(int div)
+{   
+    cyg_uint8 orig = lpc_get_vpbdiv();
+    
+    //update VPBDIV register
+    HAL_WRITE_UINT32(LPC_SCB + LPC_SCB_VPBDIV, (div % 4) | (orig & 0xFC));
+    
+    lpc_pclk = lpc_cclk/div;
+}
+
+void hal_hardware_init(void)
+{
+    lpc_cclk = CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED;
+    lpc_set_vpbdiv(4);
+    // Set up eCos/ROM interfaces
+    hal_if_init();
+
+}
+
+// -------------------------------------------------------------------------
+// This routine is called to respond to a hardware interrupt (IRQ).  It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+    cyg_uint32 irq_num,irq_stat;
+    // Find out which interrupt caused the IRQ
+    // picks the lowest if there are more.
+    // FIXME:try to make use of the VIC for better latency.
+    //       That will probably need changes to vectors.S and other int-related code
+    HAL_READ_UINT32(LPC_VIC+LPC_VIC_IRQSTATUS, irq_stat);
+    for (irq_num = 0; irq_num < 32; irq_num++)
+	    if (irq_stat & (1<<irq_num)) break;
+    // No valid interrrupt source, treat as spurious interrupt    
+    if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX)
+      irq_num = CYGNUM_HAL_INTERRUPT_NONE;
+    
+    return irq_num;
+}
+
+// -------------------------------------------------------------------------
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+    HAL_WRITE_UINT32(LPC_VIC+LPC_VIC_INTENCLR, 1<<vector);
+}
+
+void hal_interrupt_unmask(int vector)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+    HAL_WRITE_UINT32(LPC_VIC+LPC_VIC_INTEN, 1<<vector);
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+    HAL_WRITE_UINT32(LPC_VIC+LPC_VIC_VECTADDR, 0);  
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+    cyg_uint32 mode;
+    cyg_uint32 pol;
+    //only external interrupts are configurable	
+    CYG_ASSERT(vector <= CYGNUM_HAL_INTERRUPT_EINT3 &&
+               vector >= CYGNUM_HAL_INTERRUPT_EINT0 , "Invalid vector");
+    //Errata sheet says VPBDIV is corrupted when accessing EXTPOL or EXTMOD
+    //Must be written as 0 and at the end restored to original value
+    
+    HAL_WRITE_UINT32(LPC_SCB + LPC_SCB_VPBDIV, 0);
+    
+    HAL_READ_UINT32(LPC_SCB+LPC_SCB_EXTMODE, mode);
+    HAL_READ_UINT32(LPC_SCB+LPC_SCB_EXTPOL, pol);
+    
+    //map int vector to corresponding bit (0..3)
+    vector = 1 << (vector - CYGNUM_HAL_INTERRUPT_EINT0);
+    
+    //level or edge
+    if (level) {
+	mode &= ~vector;   
+    } else {
+	mode |= vector;   
+    }
+    
+    //high/low or falling/rising
+    if (up) {
+	pol |= vector;   
+    } else {
+	pol &= ~vector;   
+    }
+    
+    HAL_WRITE_UINT32(LPC_SCB+LPC_SCB_EXTMODE, mode);
+    HAL_WRITE_UINT32(LPC_SCB+LPC_SCB_EXTPOL, pol);
+    
+    //we know this was the original value
+    lpc_set_vpbdiv(lpc_cclk/lpc_pclk);
+    
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+    CYG_ASSERT(level >= 0 && level <= 15, "Invalid level");
+
+}
+
+// Use the watchdog to generate a reset
+void hal_lpc_watchdog_reset(void)
+{
+    HAL_WRITE_UINT32(LPC_WD + LPC_WD_TC, 0xFF);
+    HAL_WRITE_UINT32(LPC_WD + LPC_WD_MOD, LPC_WD_MOD_WDEN | LPC_WD_MOD_WDRESET);
+    HAL_WRITE_UINT32(LPC_WD + LPC_WD_FEED, 0xAA);	//feed WD with the two magic values
+    HAL_WRITE_UINT32(LPC_WD + LPC_WD_FEED, 0x55);
+    
+    while(1);
+}
+
+//--------------------------------------------------------------------------
+// EOF lpc_misc.c


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