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SH4 SCIF driver patch
- From: Hajime Ishitani <pigmon_at_mail_dot_snd_dot_co_dot_jp at snd dot co dot jp>
- To: ecos-patches at sources dot redhat dot com
- Date: Thu, 12 May 2005 17:31:13 +0900
- Subject: SH4 SCIF driver patch
Hello
I'm using SH4 (SH7751R).
I made a patch to be able to use a SCIF driver from SH4.
I revised register access method.
Index: ecos/packages/devs/serial/sh/scif/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/sh/scif/current/ChangeLog,v
retrieving revision 1.9
diff -u -r1.9 ChangeLog
--- ecos/packages/devs/serial/sh/scif/current/ChangeLog 18 Mar 2003
18:18:38 -0000 1.9
+++ ecos/packages/devs/serial/sh/scif/current/ChangeLog 12 May 2005
07:52:23 -0000
@@ -1,3 +1,8 @@
+2005-05-02 Hajime Ishitani <pigmon@mail.snd.co.jp>
+
+ * src/sh_scif_serial.c :
+ support SH4 register access
+
2003-03-18 Gary Thomas <gary@mlbassoc.com>
* src/sh_scif_serial.c (sh_scif_set_config):
Index: ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c,v
retrieving revision 1.8
diff -u -r1.8 sh_scif_serial.c
--- ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c 18
Mar 2003 18:18:38 -0000 1.8
+++ ecos/packages/devs/serial/sh/scif/current/src/sh_scif_serial.c 12
May 2005 07:52:23 -0000
@@ -96,6 +96,17 @@
# define SCIF_SCFRDR 0x0a // receive data register
# define SCIF_SCFCR 0x0c // FIFO control
# define SCIF_SCFDR 0x0e // FIFO data count register
+#elif defined(CYGPKG_HAL_SH_SH4)
+// The SCIF controller register layout on the SH4
+// The controller base is defined in the board specification file.
+# define SCIF_SCSMR 0x00 // serial mode register
+# define SCIF_SCBRR 0x04 // bit rate register
+# define SCIF_SCSCR 0x08 // serial control register
+# define SCIF_SCFTDR 0x0C // transmit data register
+# define SCIF_SCSSR 0x10 // serial status register
+# define SCIF_SCFRDR 0x14 // receive data register
+# define SCIF_SCFCR 0x18 // FIFO control
+# define SCIF_SCFDR 0x1C // FIFO data count register
#else
# error "Unsupported variant"
#endif
@@ -254,12 +265,22 @@
return false;
// Disable SCI interrupts while changing hardware
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(base+SCIF_SCSCR, _scr);
HAL_WRITE_UINT8(base+SCIF_SCSCR, 0);
+#else
+ HAL_READ_UINT16(base+SCIF_SCSCR, _scr);
+ HAL_WRITE_UINT16(base+SCIF_SCSCR, 0);
+#endif
// Reset FIFO.
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCFCR,
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCFCR,
+
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
+#endif
#ifdef CYGINT_IO_SERIAL_SH_SCIF_ASYNC_RXTX
sh_chan->async_rxtx_mode = false;
@@ -288,13 +309,21 @@
HAL_WRITE_UINT8(base+SCIF_SCIMR, 0);
#endif
#endif
- }
+ }
+
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCSMR, _smr);
-
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCSMR, _smr);
+#endif
// Set baud rate.
_smr &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
_smr |= baud_divisor >> 8;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCSMR, _smr);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCSMR, _smr);
+#endif
HAL_WRITE_UINT8(base+SCIF_SCBRR, baud_divisor & 0xff);
// FIXME: Should delay 1/<baud> second here.
@@ -322,11 +351,23 @@
// and actual transmission stop, it may be necessary to reduce the
// trigger level further.
#ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCFCR,
+
CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8);
+#endif
#else
HAL_WRITE_UINT8(base+SCIF_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_14|CYGARC_REG_SCIF_SCFCR_TTRG_8);
+#if !defined(CYGPKG_HAL_SH_SH4)
+ HAL_WRITE_UINT8(base+SCIF_SCFCR,
+
CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCFCR,
+
CYGARC_REG_SCIF_SCFCR_RTRG_8|CYGARC_REG_SCIF_SCFCR_TTRG_8);
+#endif
#endif
if (init) {
@@ -345,7 +386,11 @@
_scr |= CYGARC_REG_SCIF_SCSCR_RIE; // enable rx interrupts
}
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCSCR, _scr);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCSCR, _scr);
+#endif
if (new_config != &chan->config) {
chan->config = *new_config;
@@ -537,12 +582,20 @@
// RX interrupt. When disabled, FIFO will fill up and
// clear RTS.
cyg_uint8 _scscr;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(base+SCIF_SCSCR, _scscr);
+#else
+ HAL_READ_UINT16(base+SCIF_SCSCR, _scscr);
+#endif
if (*f) // we should throttle
_scscr &= ~CYGARC_REG_SCIF_SCSCR_RIE;
else // we should no longer throttle
_scscr |= CYGARC_REG_SCIF_SCSCR_RIE;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCSCR, _scscr);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCSCR, _scscr);
+#endif
}
#ifdef CYGHWR_SH_SCIF_FLOW_DSRDTR
if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX ) {
@@ -562,12 +615,20 @@
cyg_addrword_t base = ser_chan->ctrl_base;
cyg_uint8 *f = (cyg_uint8 *)xbuf;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(base+SCIF_SCFCR, _scfcr);
+#else
+ HAL_READ_UINT16(base+SCIF_SCFCR, _scfcr);
+#endif
if (*f) // enable RTS/CTS flow control
_scfcr |= CYGARC_REG_SCIF_SCFCR_MCE;
else // disable RTS/CTS flow control
_scfcr &= ~CYGARC_REG_SCIF_SCFCR_MCE;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(base+SCIF_SCFCR, _scfcr);
+#else
+ HAL_WRITE_UINT16(base+SCIF_SCFCR, _scfcr);
+#endif
}
#ifndef CYGHWR_SH_SCIF_FLOW_DSRDTR
// Clear DSR/DTR flag as it's not supported.
@@ -630,9 +691,15 @@
| CYGARC_REG_CHCR_IE | CYGARC_REG_CHCR_DE);
// Enable serial interrupts
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, scr);
scr |= CYGARC_REG_SCIF_SCSCR_TIE;
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, scr);
+ scr |= CYGARC_REG_SCIF_SCSCR_TIE;
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, scr);
+#endif
}
return res;
@@ -690,9 +757,15 @@
cyg_uint32 _cr;
// mask serial interrupt
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _cr);
_cr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit interrupt
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _cr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _cr);
+ _cr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit interrupt
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _cr);
+#endif
// mask DMA interrupt and disable engine
HAL_READ_UINT32(sh_chan->dma_xmt_base+CYGARC_REG_CHCR, _cr);
@@ -753,7 +826,11 @@
// middle of this would result in a bad CR state.
cyg_drv_isr_lock();
{
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
_scr |= CYGARC_REG_SCIF_SCSCR_TIE; // Enable xmit
interrupt
#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA
if (sh_chan->irda_mode) {
@@ -773,7 +850,11 @@
_scr &= ~CYGARC_REG_SCIF_SCSCR_RE;
}
#endif
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
sh_chan->tx_enabled = true;
}
cyg_drv_isr_unlock();
@@ -812,7 +893,11 @@
// result in a bad CR state.
cyg_drv_isr_lock();
{
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
_scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // Disable xmit
interrupt
#ifdef CYGINT_IO_SERIAL_SH_SCIF_IRDA
if (sh_chan->irda_mode) {
@@ -841,7 +926,11 @@
_scr &= ~CYGARC_REG_SCIF_SCSCR_TE;
}
#endif
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
}
cyg_drv_isr_unlock();
@@ -862,9 +951,15 @@
sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv;
cyg_uint8 _scr;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
_scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // mask out tx interrupts
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+ _scr &= ~CYGARC_REG_SCIF_SCSCR_TIE; // mask out tx interrupts
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
return CYG_ISR_CALL_DSR; // Cause DSR to be run
}
@@ -925,9 +1020,15 @@
if (sh_chan->tx_enabled) {
cyg_uint8 _scr;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
_scr |= CYGARC_REG_SCIF_SCSCR_TIE; // unmask tx interrupts
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+ _scr |= CYGARC_REG_SCIF_SCSCR_TIE; // unmask tx interrupts
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
}
}
@@ -939,9 +1040,15 @@
sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv;
cyg_uint8 _scr;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
_scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+ _scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
return CYG_ISR_CALL_DSR; // Cause DSR to be run
}
@@ -998,9 +1105,15 @@
HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR,
CYGARC_REG_SCIF_SCSSR_CLEARMASK &
~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR));
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
_scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+ _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
}
// Serial I/O - low level error interrupt handler (ISR)
@@ -1011,9 +1124,15 @@
sh_scif_info *sh_chan = (sh_scif_info *)chan->dev_priv;
cyg_uint8 _scr;
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
_scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+ _scr &= ~CYGARC_REG_SCIF_SCSCR_RIE; // mask rx interrupts
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
return CYG_ISR_CALL_DSR; // Cause DSR to be run
}
@@ -1070,9 +1189,15 @@
}
HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSSR, _ssr_mask);
+#if !defined(CYGPKG_HAL_SH_SH4)
HAL_READ_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
_scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts
HAL_WRITE_UINT8(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#else
+ HAL_READ_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+ _scr |= CYGARC_REG_SCIF_SCSCR_RIE; // unmask rx interrupts
+ HAL_WRITE_UINT16(sh_chan->ctrl_base+SCIF_SCSCR, _scr);
+#endif
}
#endif // ifdef CYGDAT_IO_SERIAL_SH_SCIF_INL
--
Hajime Ishitani
.