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Generic 8250 serial diagnostics.
- From: David Vrabel <dvrabel at arcom dot com>
- To: eCos Patches <ecos-patches at ecos dot sourceware dot org>
- Date: Mon, 19 Dec 2005 15:40:16 +0000
- Subject: Generic 8250 serial diagnostics.
Hi,
The patches adds generic 8250/16x50 serial diagnostics routines to
hal/common. It's been tested with standard PC UARTs, IXP4xx internal
UARTs, and external UARTs on a PXA270 board. It likely works for many
other processor/UART combinations.
I think this is preferable to the current practice of copying all the
routines whenever a new platform is implemented.
UART quirks (e.g., the UUE bit on the internal UARTs of the IXP4xx) are
handled by a set of UART_FEATURE_XXX bits which are provided on a
per-port basis. Additional UART quirks can be added as required.
David Vrabel
--
David Vrabel, Design Engineer
Arcom, Clifton Road Tel: +44 (0)1223 411200 ext. 3233
Cambridge CB1 7EA, UK Web: http://www.arcom.com/
%status
pending
%patch
Index: ecos-working/packages/hal/common/current/ChangeLog
===================================================================
--- ecos-working.orig/packages/hal/common/current/ChangeLog 2005-12-19 14:57:35.000000000 +0000
+++ ecos-working/packages/hal/common/current/ChangeLog 2005-12-19 14:57:37.000000000 +0000
@@ -1,3 +1,12 @@
+2005-12-19 David Vrabel <dvrabel@arcom.com>
+
+ * cdl/common.cdl: New interface CYGINT_HAL_COMMON_8250_SERIAL_DIAG
+ to enable the building of the generic 8250 serial diagnostics
+ routines.
+
+ * include/hal_serial_8250_diag.h, src/hal_serial_8250_diag.c: New
+ generic 8250 serial diagnostics routines.
+
2005-06-27 Andrew Lunn <andrew.lunn@ascom.ch>
* include/hal_tables.h (CYG_HAL_TABLE_{QUALIFIED_}ENTRY): added
Index: ecos-working/packages/hal/common/current/cdl/common.cdl
===================================================================
--- ecos-working.orig/packages/hal/common/current/cdl/common.cdl 2005-12-19 14:57:35.000000000 +0000
+++ ecos-working/packages/hal/common/current/cdl/common.cdl 2005-12-19 14:57:37.000000000 +0000
@@ -150,3 +150,14 @@
}
}
+cdl_interface CYGINT_HAL_COMMON_8250_SERIAL_DIAG {
+ display "Use the generic 8250 serial diagnostics routines"
+}
+
+cdl_option CYGBLD_HAL_COMMON_8250_SERIAL_DIAG {
+ display "Build generic 8250 serial diagnostics routines"
+ active_if CYGINT_HAL_COMMON_8250_SERIAL_DIAG
+ calculated 1
+
+ compile hal_serial_8250_diag.c
+}
Index: ecos-working/packages/hal/common/current/include/hal_serial_8250_diag.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ ecos-working/packages/hal/common/current/include/hal_serial_8250_diag.h 2005-12-19 14:57:37.000000000 +0000
@@ -0,0 +1,69 @@
+#ifndef CYGONCE_HAL_8250_SERIAL_DIAG_H
+#define CYGONCE_HAL_8250_SERIAL_DIAG_H
+/*=============================================================================
+//
+// hal_8250_serial_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines for 8250/16x50 UARTs
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+//
+// Copyright (C) 2005 eCosCentric Ltd.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): David Vrabel <dvrabel@arcom.com>
+// Date: 2005-09-15
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+/*
+ * UART features
+ */
+#define UART_FEATURE_HAVE_UUE 0x1 /* Have UART Unit Enable bit in IER */
+
+typedef struct {
+ unsigned freq; /* frequeny of UART clock in Hz */
+ unsigned base; /* MMIO address or I/O port */
+ int regshift; /* shift to register offset */
+ int isr_vector;
+ unsigned uart_features;
+ int baud_rate;
+ cyg_bool valid;
+ cyg_int32 msec_timeout;
+} serial_8250_channel_data_t;
+
+externC void cyg_hal_serial_8250_diag_init(serial_8250_channel_data_t *channels, int num);
+
+#endif //CYGONCE_HAL_8250_SERIAL_DIAG_H
Index: ecos-working/packages/hal/common/current/src/hal_serial_8250_diag.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ ecos-working/packages/hal/common/current/src/hal_serial_8250_diag.c 2005-12-19 14:58:03.000000000 +0000
@@ -0,0 +1,386 @@
+//=============================================================================
+//
+// hal_serial_8250_diag.c
+//
+// HAL diagnostic output code for 8250/16x50 UARTs
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+//
+// Copyright (C) 2005 eCosCentric Ltd.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): David Vrabel <dvrabel@arcom.com>
+// Date: 2005-09-15
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_if.h> // interface API
+#include <cyg/hal/hal_misc.h>
+
+#include <cyg/hal/hal_serial_8250_diag.h>
+
+
+/* 8250/16x50 UART registers */
+#define UART_RBR 0x00 // Receive Buffer Register
+
+#define UART_THR 0x00 // Transmit Holding Register
+
+#define UART_IER 0x01 // Interrupt Enable Register
+# define UART_IER_RCV 0x01
+# define UART_IER_XMT 0x02
+# define UART_IER_LS 0x04
+# define UART_IER_MS 0x08
+# define UART_IER_UUE 0x40 // UART Unit Enable bit
+
+#define UART_IIR 0x02 // Interrupt Identification Register
+
+#define UART_FCR 0x02 // FIFO Control Register
+
+#define UART_LCR 0x03 // Line Control Register
+# define UART_LCR_WLS0 0x01 // word length select bit 0
+# define UART_LCR_WLS1 0x02 // word length select bit 1
+# define UART_LCR_STB 0x04 // number of stop bits
+# define UART_LCR_PEN 0x08 // parity enable
+# define UART_LCR_EPS 0x10 // even parity select
+# define UART_LCR_SP 0x20 // stick parity
+# define UART_LCR_SB 0x40 // set break
+# define UART_LCR_DLAB 0x80 // divisor latch access bit
+
+#define UART_MCR 0x04 // Modem Control Register
+# define UART_MCR_DTR 0x01
+# define UART_MCR_RTS 0x02
+# define UART_MCR_INT 0x08 // Enable interrupts
+
+#define UART_LSR 0x05 // Line Status Register
+# define UART_LSR_DR 0x01 // data ready
+# define UART_LSR_OE 0x02 // overrun error
+# define UART_LSR_PE 0x04 // parity error
+# define UART_LSR_FE 0x08 // framing error
+# define UART_LSR_BI 0x10 // break interrupt
+# define UART_LSR_THRE 0x20 // transmitter holding register empty
+# define UART_LSR_TEMT 0x40 // transmitter register empty
+# define UART_LSR_ERR 0x80 // any error condition
+
+#define UART_MSR 0x06 // Modem Status Register
+# define UART_MSR_DCTS 0x01 // delta clear to send
+# define UART_MSR_DDSR 0x02 // delta data set ready
+# define UART_MSR_TERI 0x04 // trailing edge ring indicator
+# define UART_MSR_DDCD 0x08 // delta data carrier detect
+# define UART_MSR_CTS 0x10 // clear to send
+# define UART_MSR_DSR 0x20 // data set ready
+# define UART_MSR_RI 0x40 // ring indicator
+# define UART_MSR_DCD 0x80 // data carrier detect
+
+#define UART_DLL 0x00 // Divisor Latch LSB (if DLAB = 1)
+#define UART_DLM 0x01 // Divisor Latch MSB (if DLAB = 1)
+
+
+static void uart_write(serial_8250_channel_data_t *chan, int reg, cyg_uint8 data)
+{
+ HAL_WRITE_UINT8(chan->base + (reg << chan->regshift), data);
+}
+
+static cyg_uint8 uart_read(serial_8250_channel_data_t *chan, int reg)
+{
+ cyg_uint8 data;
+ HAL_READ_UINT8(chan->base + (reg << chan->regshift), data);
+ return data;
+}
+
+static void set_baud(serial_8250_channel_data_t *chan)
+{
+ unsigned divisor;
+ cyg_uint32 lcr;
+
+ divisor = (chan->freq + 8*chan->baud_rate) / (16*chan->baud_rate);
+
+ lcr = uart_read(chan, UART_LCR);
+ uart_write(chan, UART_LCR, lcr | UART_LCR_DLAB);
+ uart_write(chan, UART_DLL, divisor & 0xff);
+ uart_write(chan, UART_DLM, (divisor >> 8) & 0xff);
+ uart_write(chan, UART_LCR, lcr);
+}
+
+static void init_channel(serial_8250_channel_data_t *chan)
+{
+ cyg_uint8 ier, lsr;
+
+ ier = 0;
+ if (chan->uart_features & UART_FEATURE_HAVE_UUE)
+ ier |= UART_IER_UUE;
+ uart_write(chan, UART_IER, ier);
+ uart_write(chan, UART_MCR, 0);
+
+ set_baud(chan);
+
+ // 8-1-no parity.
+ uart_write(chan, UART_LCR, UART_LCR_WLS0 | UART_LCR_WLS1);
+
+ // Test whether the channel is valid or not. If the status
+ // register reads back all ones, its a fair bet that it is not
+ // actually there!
+ lsr = uart_read(chan, UART_LSR);
+ chan->valid = (lsr != 0xFF);
+
+ uart_write(chan, UART_FCR, 0x07); // Enable & clear FIFO
+}
+
+static void cyg_hal_serial_8250_diag_putc(void *__ch_data, char c)
+{
+ serial_8250_channel_data_t *chan = (serial_8250_channel_data_t *)__ch_data;
+ cyg_uint8 lsr;
+
+ if (!chan->valid)
+ return;
+
+ CYGARC_HAL_SAVE_GP();
+ do {
+ lsr = uart_read(chan, UART_LSR);
+ } while ((lsr & UART_LSR_THRE) == 0);
+
+ uart_write(chan, UART_THR, c);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_serial_8250_diag_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+ serial_8250_channel_data_t *chan = (serial_8250_channel_data_t *)__ch_data;
+ cyg_uint8 lsr;
+
+ if (!chan->valid)
+ return false;
+
+ lsr = uart_read(chan, UART_LSR);
+ if ((lsr & UART_LSR_DR) == 0)
+ return false;
+
+ *ch = uart_read(chan, UART_RBR);
+
+ return true;
+}
+
+static cyg_uint8 cyg_hal_serial_8250_diag_getc(void* __ch_data)
+{
+ serial_8250_channel_data_t *chan = (serial_8250_channel_data_t *)__ch_data;
+ cyg_uint8 ch;
+
+ if (!chan->valid)
+ return '\n';
+
+ CYGARC_HAL_SAVE_GP();
+
+ while (!cyg_hal_serial_8250_diag_getc_nonblock(__ch_data, &ch));
+
+ CYGARC_HAL_RESTORE_GP();
+
+ return ch;
+}
+
+static void cyg_hal_serial_8250_diag_write(void* __ch_data, const cyg_uint8* __buf,
+ cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_serial_8250_diag_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_serial_8250_diag_read(void* __ch_data, cyg_uint8 *__buf, cyg_uint32 __len)
+{
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_serial_8250_diag_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_serial_8250_diag_getc_timeout(void* __ch_data, cyg_uint8 *ch)
+{
+ serial_8250_channel_data_t *chan = (serial_8250_channel_data_t *)__ch_data;
+ int delay_count;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10; // delay in 0.1 ms steps
+
+ for(;;) {
+ res = cyg_hal_serial_8250_diag_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
+
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+
+static int cyg_hal_serial_8250_diag_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+ serial_8250_channel_data_t *chan = (serial_8250_channel_data_t *)__ch_data;
+ static int irq_state = 0;
+ int ret = 0;
+ cyg_uint8 ier;
+ cyg_uint32 b;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ /* FIXME: Should check that the baud rate is valid? */
+ set_baud(chan);
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ ier = UART_IER_RCV;
+ if (chan->uart_features & UART_FEATURE_HAVE_UUE)
+ ier |= UART_IER_UUE;
+ uart_write(chan, UART_IER, ier);
+ uart_write(chan, UART_MCR, UART_MCR_INT | UART_MCR_DTR | UART_MCR_RTS);
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ ier = 0;
+ if (chan->uart_features & UART_FEATURE_HAVE_UUE)
+ ier |= UART_IER_UUE;
+ uart_write(chan, UART_IER, ier);
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+ default:
+ break;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
+}
+
+static int cyg_hal_serial_8250_diag_isr(void *__ch_data, int *__ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+ serial_8250_channel_data_t *chan = (serial_8250_channel_data_t *)__ch_data;
+ int res = 0;
+ char c;
+ cyg_uint8 lsr;
+
+ CYGARC_HAL_SAVE_GP();
+
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+ *__ctrlc = 0;
+ lsr = uart_read(chan, UART_LSR);
+ if ( (lsr & UART_LSR_DR) != 0 ) {
+ c = uart_read(chan, UART_RBR);
+ if (cyg_hal_is_break(&c , 1))
+ *__ctrlc = 1;
+ }
+
+ res = CYG_ISR_HANDLED;
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+}
+
+void cyg_hal_serial_8250_diag_init(serial_8250_channel_data_t *channels, int num)
+{
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+
+ for (i = 0; i < num; i++) {
+ if (channels[i].baud_rate == 0)
+ channels[i].baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
+
+ HAL_INTERRUPT_MASK(channels[i].isr_vector);
+
+ init_channel(&channels[i]);
+
+ // Setup procs in the vector table
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_serial_8250_diag_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_serial_8250_diag_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_serial_8250_diag_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_serial_8250_diag_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_serial_8250_diag_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_serial_8250_diag_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_serial_8250_diag_getc_timeout);
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_serial_8250_diag.c