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Re: [ECOS] Re: ISR not causing an DSR in some rare conditions
Jay Foster <email@example.com> writes:
> Attached is a patch for the first problem described below. This is
> essentially Sergei Organov's suggested change put into patch form.
The original suggestion had:
sub sp,sp,#(ARMREG_SIZE - armreg_lr - 4) // skip svc_sp, svc_lr, vector, cpsr, and pc
and your patch has:
sub sp,sp,#(ARMREG_SIZE - armreg_pc) // skip svc_sp, svc_lr, vector, cpsr, and pc
While they are exactly the same from the point of view of assembler, for
humans the first variant emphasized that lr will be put at armreg_lr
offset in the context structure. The fact that 'armreg_pc' happens to be
equal to 'armreg_lr - 4' does not mean one should use it instead.
Could you please preserve the former variant in your patch.