Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/ChangeLog,v
retrieving revision 1.174
diff -u -w -B -r1.174 ChangeLog
--- ChangeLog	16 Oct 2006 14:36:14 -0000	1.174
+++ ChangeLog	9 Nov 2006 18:31:20 -0000
@@ -1,3 +1,8 @@
+2006-11-09  Gratian Crisan  <gratian.crisan@ni.com>
+
+	* ecos.db: Add PHYTEC Phycore LPC229x target and PHYCORE LPC229x 
+	SMSC LAN91C111 ethernet driver
+	
 2006-10-16  Jonathan Larmour  <jifl@eCosCentric.com>
 
 	* ecos.db: Comment out CYGPKG_DEVS_ETH_ARM_AT91 for now - it's still
Index: ecos.db
===================================================================
RCS file: /cvs/ecos/ecos/packages/ecos.db,v
retrieving revision 1.160
diff -u -w -B -r1.160 ecos.db
--- ecos.db	16 Oct 2006 14:36:14 -0000	1.160
+++ ecos.db	9 Nov 2006 18:31:22 -0000
@@ -1641,6 +1641,15 @@
         description     "Ethernet driver for Intel PRO/100+ boards on ARM INTEGRATOR."
 }
 
+package CYGPKG_DEVS_ETH_ARM_PHYCORE_LPC229x {
+      alias           { "Ethernet driver for PHYCORE LPC229x SMSC LAN91C111 board" devs_eth_arm_phycore_lpc229x }
+      hardware
+      directory       devs/eth/arm/phycore_lpc229x
+      script          phycore_lpc229x_eth_drivers.cdl
+      description     "This package contains the ethernet driver for SMSC LAN91C111 
+		      ethernet chip on Phytec PHYCORE LPC229x development board."
+}
+
 package CYGPKG_DEVS_ETH_POWERPC_QUICC {
 	alias 		{ "QUICC ethernet driver" quicc_eth_driver }
 	hardware
@@ -2679,6 +2688,16 @@
 	LPC-MT evaluation board from Olimex."
 }
 
+package CYGPKG_HAL_ARM_LPC2XXX_PHYCORE {
+        alias           { "phyCORE-ARM7/LPC229x evaluation board" arm_lpc229x_phycore }
+        directory       hal/arm/lpc2xxx/phycore
+        script          hal_arm_lpc2xxx_phycore.cdl
+        hardware
+        description "
+        The PHYCORE HAL package provides the support needed to run eCos 
+	on an PHYTEC phyCORE-ARM7/LPC229x eval board."
+}
+
 package CYGPKG_HAL_ARM_MAC7100 {
 	alias		{ "Freescale MAC7100 variant HAL" hal_arm_mac7100 arm_mac7100_hal }
 	directory	hal/arm/mac7100/var
@@ -4473,6 +4492,20 @@
         LPC-P2106 evaluation board from Olimex."
 }
 
+target lpc229x_phycore {
+        alias { "phyCORE-ARM7 LPC229x eval board HAL" lpc_phycore }
+        packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_LPC2XXX
+                   CYGPKG_HAL_ARM_LPC2XXX_PHYCORE 
+                   CYGPKG_IO_SERIAL_GENERIC_16X5X
+                   CYGPKG_IO_SERIAL_ARM_LPC2XXX
+                   CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+        }
+        description "
+        The PHYCORE HAL package provides the support needed to run eCos 
+	on an PHYTEC phyCORE-ARM7/LPC229x eval board."
+}
+
 target lpcmt {
 	alias { "Olimex evaluation board LPC-LPCMT" lpcmt }
 	packages { CYGPKG_HAL_ARM
Index: devs/eth/arm/phycore_lpc229x/current/ChangeLog
===================================================================
RCS file: devs/eth/arm/phycore_lpc229x/current/ChangeLog
diff -N devs/eth/arm/phycore_lpc229x/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/arm/phycore_lpc229x/current/ChangeLog	9 Nov 2006 18:31:23 -0000
@@ -0,0 +1,37 @@
+2006-11-08  Gratian Crisan <gratian.crisan@ni.com>
+	* include/devs_eth_phycore_lpc229x.inl:
+	* cdl/phycore_lpc229x_eth_drivers.cdl:
+	* Initial version for LAN91CXX ethernet controller on the PHYTEC 
+	Phycore-LPC229x board.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 National Instruments Corporation. 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: devs/eth/arm/phycore_lpc229x/current/cdl/phycore_lpc229x_eth_drivers.cdl
===================================================================
RCS file: devs/eth/arm/phycore_lpc229x/current/cdl/phycore_lpc229x_eth_drivers.cdl
diff -N devs/eth/arm/phycore_lpc229x/current/cdl/phycore_lpc229x_eth_drivers.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/arm/phycore_lpc229x/current/cdl/phycore_lpc229x_eth_drivers.cdl	9 Nov 2006 18:31:23 -0000
@@ -0,0 +1,91 @@
+# ====================================================================
+#
+#      phycore_lpc229x_eth_drivers.cdl
+#
+#      Support for LAN91CXX ethernet controller on the PHYTEC 
+#	   Phycore-LPC229x board.
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2006 National Instruments Corporation. 
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Gratian Crisan
+# Contributors:
+# Date:           2006-11-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_ARM_PHYCORE_LPC229x {
+
+    display       "PHYCORE SMSC LAN91C111 ethernet driver"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_HAL_ARM_LPC2XXX_PHYCORE
+
+    include_dir   cyg/io
+		
+    # 32-bit mode, with EEPROM
+    implements    CYGHWR_NET_DRIVERS
+    implements    CYGHWR_NET_DRIVER_ETH0
+    implements    CYGINT_DEVS_ETH_SMSC_LAN91CXX_REQUIRED
+    
+    requires      CYGPKG_DEVS_ETH_SMSC_LAN91CXX
+    description   "Ethernet driver for PHYCORE LPC229x SMSC LAN91C111 boards."
+	
+    define_proc {
+        puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_SMSC_LAN91CXX_INL <cyg/io/devs_eth_phycore_lpc229x.inl>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_SMSC_LAN91CXX_CFG <pkgconf/devs_eth_arm_phycore_lpc229x.h>"
+        puts $::cdl_system_header "/*****  ethernet driver proc output end  *****/"
+    }
+    
+    # Arguably this should do in the generic package
+    # but then there is a logic loop so you can never enable it.
+
+    cdl_interface CYGINT_DEVS_ETH_SMSC_LAN91CXX_REQUIRED {
+        display   "SMSC LAN91CXX driver required"
+    }
+
+    cdl_option CYGDAT_DEVS_ETH_ARM_PHYCORE_LPC229x_NAME {
+        display       "Device name for the ethernet driver"
+        flavor        data
+        default_value {"\"eth0\""}
+        description   "
+            This option sets the name of the ethernet device for the
+            ethernet port."
+    }
+}
+
+# EOF phycore_lpc229x_eth_drivers.cdl
Index: devs/eth/arm/phycore_lpc229x/current/include/devs_eth_phycore_lpc229x.inl
===================================================================
RCS file: devs/eth/arm/phycore_lpc229x/current/include/devs_eth_phycore_lpc229x.inl
diff -N devs/eth/arm/phycore_lpc229x/current/include/devs_eth_phycore_lpc229x.inl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ devs/eth/arm/phycore_lpc229x/current/include/devs_eth_phycore_lpc229x.inl	9 Nov 2006 18:31:23 -0000
@@ -0,0 +1,84 @@
+//==========================================================================
+//
+//	devs_eth_phycore_lpc229x.inl
+//
+//	PHYCORE LPC229x ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 National Instruments Corporation. 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):	Gratian Crisan
+// Contributors: 
+// Date:        2006-11-08 
+// Purpose:      
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/devs_eth_arm_phycore_lpc229x.h>
+#include <cyg/hal/hal_intr.h>  
+#include <cyg/hal/hal_platform_ints.h>        
+#include <cyg/hal/plf_io.h>
+
+#define LAN91CXX_IS_LAN91C111	1
+
+static lan91cxx_priv_data lan91cxx_eth0_priv_data = { 
+	provide_esa : NULL,				// read MAC from associated EEPROM
+	hardwired_esa : 0,
+	base : (unsigned short *) CYGARC_HAL_LPC2XXX_PHYCORE_ETH_BASE,
+	interrupt :  CYGARC_HAL_LPC2XXX_PHYCORE_ETH_IRQ
+};
+
+ETH_DRV_SC(lan91cxx_sc,
+	&lan91cxx_eth0_priv_data,			// Driver specific data
+	CYGDAT_DEVS_ETH_ARM_PHYCORE_LPC229x_NAME,	// Name for device
+	lan91cxx_start,
+	lan91cxx_stop,
+	lan91cxx_control,
+	lan91cxx_can_send,
+	lan91cxx_send,
+	lan91cxx_recv,
+	lan91cxx_deliver,
+	lan91cxx_poll,
+	lan91cxx_int_vector
+);
+
+NETDEVTAB_ENTRY(lan91cxx_netdev, 
+	"lan91cxx_" CYGDAT_DEVS_ETH_ARM_PHYCORE_LPC229x_NAME,
+	smsc_lan91cxx_init,
+	&lan91cxx_sc);
+
+//EOF devs_eth_phycore_lpc229x.inl
+
+
Index: devs/eth/smsc/lan91cxx/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/smsc/lan91cxx/current/ChangeLog,v
retrieving revision 1.22
diff -u -w -B -r1.22 ChangeLog
--- devs/eth/smsc/lan91cxx/current/ChangeLog	20 Jul 2006 19:14:31 -0000	1.22
+++ devs/eth/smsc/lan91cxx/current/ChangeLog	9 Nov 2006 18:31:25 -0000
@@ -1,3 +1,15 @@
+2006-11-09  Gratian Crisan  <gratian.crisan@ni.com>
+
+	* cdl/smsc_lan91cxx_eth_drivers.cdl:
+	* src/if_lan91cxx.c:
+	Added options for disabling auto-negotiation and manually selecting
+	the ethernet speed and duplex mode
+	Added workaround for PHYTEC Phycore LPC229x development board. This
+	board has a bug that won't allow you to select the level for the EINT0 
+	interrupt connected to the ethernet chip. This workaround will use the 
+	capture input instead of EINT0.
+	
+	
 2005-06-27  Stefan Sommerfeld <sommerfeld@mikrom.com>
  
 	* src/if_lan91cxx.c: Changed some debug messages to output right
Index: devs/eth/smsc/lan91cxx/current/cdl/smsc_lan91cxx_eth_drivers.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/smsc/lan91cxx/current/cdl/smsc_lan91cxx_eth_drivers.cdl,v
retrieving revision 1.8
diff -u -w -B -r1.8 smsc_lan91cxx_eth_drivers.cdl
--- devs/eth/smsc/lan91cxx/current/cdl/smsc_lan91cxx_eth_drivers.cdl	20 Jul 2006 19:14:31 -0000	1.8
+++ devs/eth/smsc/lan91cxx/current/cdl/smsc_lan91cxx_eth_drivers.cdl	9 Nov 2006 18:31:25 -0000
@@ -109,6 +109,52 @@
             configured in PCMCIA mode."
     }
 
+    cdl_option CYGNUM_DEVS_ETH_SMSC_LAN91CXX_USE_AUTO_NEGOTIATION {
+        display		"use auto-negotiation"
+        flavor		data
+        legal_values	0 to 1
+        default_value	1
+        description 	"
+            The device driver uses auto-negotiation to determine
+            the speed and duplex mode to use. If these is 1 the
+            speed and duplex parameters are ignored."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_SMSC_LAN91CXX_SPEED {
+        display		"selects the ethernet speed"
+        flavor		data
+        legal_values	10 100
+        default_value	100
+        description	"
+            Selects between 10 or 100 MBit speeds. This parameter
+            is ignored if auto-negotiation is enabled."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_SMSC_LAN91CXX_DUPLEX {
+        display		"selects the link duplex state"
+        flavor		data
+        legal_values	0 to 1
+        default_value	1
+        description	"
+            When Auto Negotiation is disabled this entry can be used
+            to manually select the link duplex state. Writting a '1'
+            to this field selects full duplex while a '0' selects half
+            duplex. When auto-negotiation is enabled writing this
+            field has no effect."
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_SMSC_LAN91CXX_PHYCORE_EINT0_BUG {
+        display		"work around the EINT0 bug on LPC229x"
+        flavor		data
+        calculated	{CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA == 1}
+        active_if	CYGPKG_HAL_ARM_LPC2XXX_PHYCORE
+        description 	"
+            The LPC229x on the PHYCORE development board has a
+            bug that won't allow you to select the level for the
+            EINT0 interrupt connected to the ethernet chip. This
+            workaround will use the capture input instead of EINT0."
+    }
+
     cdl_component CYGPKG_DEVS_ETH_SMSC_LAN91CXX_OPTIONS {
         display "LAN91CXX ethernet driver build options"
         flavor  none
Index: devs/eth/smsc/lan91cxx/current/src/if_lan91cxx.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/smsc/lan91cxx/current/src/if_lan91cxx.c,v
retrieving revision 1.20
diff -u -w -B -r1.20 if_lan91cxx.c
--- devs/eth/smsc/lan91cxx/current/src/if_lan91cxx.c	20 Jul 2006 19:14:31 -0000	1.20
+++ devs/eth/smsc/lan91cxx/current/src/if_lan91cxx.c	9 Nov 2006 18:31:26 -0000
@@ -216,7 +216,9 @@
     struct eth_drv_sc *sc = (struct eth_drv_sc *)data;
     struct lan91cxx_priv_data *cpd =
         (struct lan91cxx_priv_data *)sc->driver_private;
-
+#ifdef CYGNUM_DEVS_ETH_SMSC_LAN91CXX_PHYCORE_EINT0_BUG_1
+    cyg_uint32 ir;
+#endif // CYGNUM_DEVS_ETH_SMSC_LAN91CXX_PHYCORE_EINT0_BUG_1
 //    DEBUG_FUNCTION();
 
     INCR_STAT( interrupts );
@@ -224,8 +226,36 @@
     cyg_drv_interrupt_mask(cpd->interrupt);
     cyg_drv_interrupt_acknowledge(cpd->interrupt);
 
+#ifdef CYGNUM_DEVS_ETH_SMSC_LAN91CXX_PHYCORE_EINT0_BUG_1
+    // stop timer and reset
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxTCR, 
+		     CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_RESET);
+
+    // read interrupt flags 
+    HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxIR, ir);
+#ifdef CYGARC_HAL_LPC2XXX_PHYCORE_CAPTURE
+    if (!(ir & CYGARC_HAL_LPC2XXX_REG_TxIR_CR2)) {
+        // other capture or MR0, call target function
+        CYGARC_HAL_LPC2XXX_PHYCORE_CAPTURE(ir);
+    }
+#endif // CYGARC_HAL_LPC2XXX_PHYCORE_CAPTURE
+
+    // re-arm interrupt
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxIR, ir);
+    // start timer
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxTCR, 
+		     CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_ENABLE);
+
+    if (!(ir & CYGARC_HAL_LPC2XXX_REG_TxIR_CR2)) {
+        cyg_drv_interrupt_unmask(cpd->interrupt);
+        return CYG_ISR_HANDLED;
+    } else {
     return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
 }
+#else
+    return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
+#endif //CYGNUM_DEVS_ETH_SMSC_LAN91CXX_PHYCORE_EINT0_BUG_1
+}
 #endif
 
 // The deliver function (ex-DSR)  handles the ethernet [logical] processing
@@ -477,6 +507,8 @@
 {
     cyg_uint16 intr;
 #ifdef LAN91CXX_IS_LAN91C111
+    cyg_uint16 phy_flags;
+    cyg_uint16 mac_flags;
     int delay;
 #endif
 #ifdef CYGPKG_NET
@@ -488,13 +520,11 @@
     // 91C111 Errata. Internal PHY comes up disabled. Must enable here.
     lan91cxx_write_phy(sc, 0, LAN91CXX_PHY_CTRL, LAN91CXX_PHY_CTRL_RST);
     CYGACC_CALL_IF_DELAY_US(500000);
+
+    if (CYGNUM_DEVS_ETH_SMSC_LAN91CXX_USE_AUTO_NEGOTIATION) {
     lan91cxx_write_phy(sc, 0, LAN91CXX_PHY_CTRL, LAN91CXX_PHY_CTRL_ANEG_EN |
 		                                 LAN91CXX_PHY_CTRL_SPEED);
 
-#ifdef LAN91CXX_FORCE_10MHZ
-    lan91cxx_write_phy( sc, 0, LAN91CXX_PHY_AUTO_AD, 0x0061);
-#endif
-
     // Start auto-negotiation
     put_reg(sc, LAN91CXX_RPCR,
 	    LAN91CXX_RPCR_LEDA_RX | LAN91CXX_RPCR_LEDB_LINK | LAN91CXX_RPCR_ANEG);
@@ -509,9 +539,21 @@
     }
 #if DEBUG & 1
     if (delay <= 0)
-	    diag_printf("auto-negotiation failed.\n");
-#endif
+            db_printf("auto-negotiation failed.\n");
 #endif
+    } else {
+        phy_flags = 0;
+        mac_flags = LAN91CXX_RPCR_LEDA_RX | LAN91CXX_RPCR_LEDB_LINK;
+
+        phy_flags |= (CYGNUM_DEVS_ETH_SMSC_LAN91CXX_SPEED == 100) ? LAN91CXX_PHY_CTRL_SPEED : 0;
+	phy_flags |= (CYGNUM_DEVS_ETH_SMSC_LAN91CXX_DUPLEX) ? LAN91CXX_PHY_CTRL_DPLX : 0;
+        lan91cxx_write_phy(sc, 0, LAN91CXX_PHY_CTRL, phy_flags);
+	
+	mac_flags |= (CYGNUM_DEVS_ETH_SMSC_LAN91CXX_SPEED == 100) ? LAN91CXX_RPCR_SPEED : 0;
+        mac_flags |= (CYGNUM_DEVS_ETH_SMSC_LAN91CXX_DUPLEX) ? LAN91CXX_RPCR_DPLX : 0;
+        put_reg(sc, LAN91CXX_RPCR, mac_flags);
+    }
+#endif //LAN91CXX_IS_LAN91C111
 
     put_reg(sc, LAN91CXX_MMU_COMMAND, LAN91CXX_MMU_reset_mmu);
 
Index: hal/arm/lpc2xxx/phycore/current/ChangeLog
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/ChangeLog
diff -N hal/arm/lpc2xxx/phycore/current/ChangeLog
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/ChangeLog	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,44 @@
+2006-11-09  Gratian Crisan <gratian.crisan@ni.com>
+
+	* src/phycore_misc.c:
+	* cdl/hal_arm_lpc2xxx_phycore.cdl:
+	* include/hal_platform_ints.h
+	* include/hal_platform_setup.h
+	* include/plf_io.h
+	* include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.h
+	* include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.ldi
+	* include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.h
+	* include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.ldi	
+	New HAL platform added to support the PHYTEC phyCORE-ARM7/LPC229x board
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 National Instruments Corporation. 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
Index: hal/arm/lpc2xxx/phycore/current/cdl/hal_arm_lpc2xxx_phycore.cdl
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/cdl/hal_arm_lpc2xxx_phycore.cdl
diff -N hal/arm/lpc2xxx/phycore/current/cdl/hal_arm_lpc2xxx_phycore.cdl
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/cdl/hal_arm_lpc2xxx_phycore.cdl	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,286 @@
+# ====================================================================
+#
+#      hal_arm_lpc2xxx_phycore.cdl
+#
+#      phyCORE-ARM7/LPC229x HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+## Copyright (C) 2004 eCosCentric Limited
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Gratian Crisan
+# Contributors:   jani, gthomas, tkoeller, nickg
+# Date:           2006-11-09
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ARM_LPC2XXX_PHYCORE {
+    display       "phyCORE-ARM7/LPC229x eval board HAL"
+    parent        CYGPKG_HAL_ARM_LPC2XXX
+    define_header hal_arm_lpc2xxx_phycore.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The PHYCORE HAL package provides the support needed to run eCos 
+	on an PHYTEC phyCORE-ARM7/LPC229x eval board."
+
+    compile       phycore_misc.c
+
+    requires      { CYGHWR_HAL_ARM_LPC2XXX == "LPC2292" || CYGHWR_HAL_ARM_LPC2XXX == "LPC2294" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_arm_lpc2xxx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_lpc2xxx_phycore.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"ARM7TDMI-S\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"PHYTEC phyCORE/LPC229x\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+    
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"ROM"}
+        legal_values  {"ROM" "RAM"}
+	no_define
+	define -file system.h CYG_HAL_STARTUP
+        description   "
+            Choose ROM or RAM startup type."
+    }
+    
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   2
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The PHYCORE board has two serial ports."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            The PHYCORE board has two serial ports."
+     }
+     
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port."
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+         display       "GDB serial port baud rate"
+         flavor        data
+         legal_values  9600 19200 38400 57600 115200
+         default_value 38400
+         description   "
+            This option controls the baud rate used for the GDB connection."
+     }
+     
+    # Real-time clock/counter specifics
+    cdl_option CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ {
+        display       "CPU clock speed"
+        flavor        data
+        default_value {10000000}
+    }
+
+    cdl_option CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL {
+        display       "CPU clock speed"
+        flavor        data
+        default_value {6}
+    }
+ 
+    cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+        display       "CPU clock speed"
+        flavor        data
+        calculated { CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL * CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ }
+    }
+   
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+    
+            make -priority 325 {
+                <PREFIX>/bin/redboot.hex : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O ihex $< $@
+            }
+
+        }
+    }
+
+    cdl_option CYGNUM_HAL_ARM_LPC2XXX_WITH_SMSC_LAN91CXX {
+	display		"True if Phycore with SMSC LAN91CXX driver present"
+	flavor		data
+	calculated	{CYGINT_DEVS_ETH_SMSC_LAN91CXX_REQUIRED}
+	description 	"
+		This option is true if this is a build tree for PHYCORE
+		development board with SMSC LAN91CXX ethernet driver enabled."
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+	    calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_lpc2xxx_phycore_ram":
+                                                  "arm_lpc2xxx_phycore_rom"}
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+	        calculated { (CYG_HAL_STARTUP == "RAM") ? 
+                         "<pkgconf/mlt_arm_lpc2xxx_phycore_ram.ldi>": 
+                         "<pkgconf/mlt_arm_lpc2xxx_phycore_rom.ldi>"} 
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+	        calculated { (CYG_HAL_STARTUP == "RAM") ? 
+                     "<pkgconf/mlt_arm_lpc2xxx_phycore_ram.h>":
+	                 "<pkgconf/mlt_arm_lpc2xxx_phycore_rom.h>"}
+        }
+    }
+
+}
Index: hal/arm/lpc2xxx/phycore/current/include/hal_platform_ints.h
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/hal_platform_ints.h
diff -N hal/arm/lpc2xxx/phycore/current/include/hal_platform_ints.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/hal_platform_ints.h	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//=============================================================================
+//
+//      hal_platform_ints.h
+//
+//      PHYCORE LPC229x interrupts
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 National Instruments Corporation. 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):  Gratian Crisan
+// Contributors:
+// Date:        2006-11-09
+// Purpose:     PHYTEC phyCORE LPC229x board specific interrupts
+// Description:
+// Usage:       #include <cyg/hal/hal_platform_ints.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#define CYGNUM_HAL_INTERRUPT_WDT                0
+#define CYGNUM_HAL_INTERRUPT_SW                 1
+#define CYGNUM_HAL_INTERRUPT_ICE_RX             2
+#define CYGNUM_HAL_INTERRUPT_ICE_TX             3
+#define CYGNUM_HAL_INTERRUPT_TIMER0             4
+#define CYGNUM_HAL_INTERRUPT_TIMER1             5
+#define CYGNUM_HAL_INTERRUPT_UART0              6
+#define CYGNUM_HAL_INTERRUPT_UART1              7
+#define CYGNUM_HAL_INTERRUPT_PWM0               8
+#define CYGNUM_HAL_INTERRUPT_I2C                9
+#define CYGNUM_HAL_INTERRUPT_SPI0               10
+#define CYGNUM_HAL_INTERRUPT_SPI1               11
+#define CYGNUM_HAL_INTERRUPT_PLL                12
+#define CYGNUM_HAL_INTERRUPT_WALLCLOCK          13
+#define CYGNUM_HAL_INTERRUPT_EINT0              14
+#define CYGNUM_HAL_INTERRUPT_EINT1              15
+#define CYGNUM_HAL_INTERRUPT_EINT2              16
+#define CYGNUM_HAL_INTERRUPT_EINT3              17
+#define CYGNUM_HAL_INTERRUPT_AD                 18
+#define CYGNUM_HAL_INTERRUPT_CAN_FILTER         19
+#define CYGNUM_HAL_INTERRUPT_CAN1_TX            20
+#define CYGNUM_HAL_INTERRUPT_CAN2_TX            21
+#define CYGNUM_HAL_INTERRUPT_CAN3_TX            22
+#define CYGNUM_HAL_INTERRUPT_CAN4_TX            23
+/* 24-25 reserved */
+#define CYGNUM_HAL_INTERRUPT_CAN1_RX            26
+#define CYGNUM_HAL_INTERRUPT_CAN2_RX            27
+#define CYGNUM_HAL_INTERRUPT_CAN3_RX            28
+#define CYGNUM_HAL_INTERRUPT_CAN4_RX            29
+/* 30-31 reserved */
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
Index: hal/arm/lpc2xxx/phycore/current/include/hal_platform_setup.h
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/hal_platform_setup.h
diff -N hal/arm/lpc2xxx/phycore/current/include/hal_platform_setup.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/hal_platform_setup.h	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,232 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+/*=============================================================================
+//
+//      hal_platform_setup.h
+//
+//      Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+// Copyright (C) 2004 eCosCentric Limited 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Gratian Crisan
+// Contributors: jani
+// Date:        2006-11-09
+// Purpose:     LPC229X/PHYCORE platform specific support routines
+// Description:
+// Usage:       #include <cyg/hal/hal_platform_setup.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <cyg/hal/var_io.h>
+
+//===========================================================================*/
+
+#define LINES (0xFE<<16)
+#define LINE  (1<<16)
+.macro  _line_init
+// set to GPIO
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
+        ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
+        bic r1, r1, #8
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
+// set to output
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
+        ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1DIR]
+        orr r1,r1,#LINE
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1DIR]
+// turn ON
+        ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1PIN]
+        bic r1,r1,#LINES
+        orr r1,r1,#LINE
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1PIN]
+.endm
+
+.macro  _led_init
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
+        ldr r1,=(1<<8)                                  // GPIO0 pins 8 is LED output
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0DIR]
+.endm
+
+.macro _led x
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
+        ldr r1,=(1<<8)
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0CLR]
+        ldr r1,=((\x & 1)<<8)
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0SET]
+.endm
+#define CYGHWR_LED_MACRO _led \x 
+	
+.macro _pll_init					/// PLL intitialization
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
+
+        mov r2,#0xAA
+        mov r3,#0x55
+
+        mov r1,#(0x20 | (CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL - 1))
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]	// load the PLL configuration register	
+
+        mov r1,#1						
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]	// enable PLL
+
+        str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]	// perform validation sequence 0XAA followed by 0x55
+        str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
+
+1:
+        ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLSTAT]	// wait for it to lock
+        ands r1,r1,#(1<<10)
+        beq 1b
+	
+        mov r1,#3			                // connect PLL
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
+
+        str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]	// perform validation sequence 0XAA followed by 0x55
+        str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]	
+.endm
+	
+.macro _mem_init
+        mov r0,#0					// copy first 64 bytes of flash to RAM
+        mov r1,#0x40000000
+        mov r2,#0x40
+1:
+        ldr r3,[r0,#4]!
+        str r3,[r1,#4]!
+        cmps r0,r2
+        bne 1b
+
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
+        mov r1,#2
+        // interrupt vector table is mapped to FLASH(1) or RAM(2)	
+        str r1, [r0,#CYGARC_HAL_LPC2XXX_REG_MEMMAP]	
+        mov r1,#4					// 4 processor clocks fetch cycle
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMTIM]	// flash timings
+        mov r1,#2
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMCR]	// enable full MAM
+.endm
+
+// set-up external memory
+/**
+ * Bank Configuration Registers 0-3 (BCFG0-3)
+ *      [0..3]          IDCY: Min. number of idle Cycles <0-15>
+ *      [4]             Reserved     
+ *      [5..9]          WST1: Wait States 1 <0-31>
+ *      [10]            RBLE: Read Byte Lane Enable
+ *      [11..15]        WST2: Wait States 2 <0-31>
+ *      [16..23]        Reserved
+ *      [26]            WP: Write Protect
+ *      [27]            BM: Burst ROM
+ *      [28..29]        MW: Memory Width  <0=8-bit,1=16-bit,2=32-bit,3=Reserved>
+ *      [30..31]        Reserved
+ */
+#define CYGARC_HAL_LPC229x_REG_BCFG0_VAL	0x200038E3
+#define CYGARC_HAL_LPC229x_REG_BCFG1_VAL	0x20003CE3
+#define CYGARC_HAL_LPC229x_REG_BCFG2_VAL	0x20003CE3
+#define CYGARC_HAL_LPC229x_REG_BCFG3_VAL	0x2000FFEF
+#define CYGARC_HAL_LPC229x_EXT_BUS_PINS		0x0E6149E4  /* CS0..3, OE, WE, BLS0..3, 
+								D0..31, A2..23, JTAG Pins */
+.macro _ext_bus_init
+        // enable external parallel bus signals
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
+        ldr r1,=CYGARC_HAL_LPC229x_EXT_BUS_PINS
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]	
+
+        // set-up external memory wait states
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG0
+        ldr r1,=CYGARC_HAL_LPC229x_REG_BCFG0_VAL
+        str r1, [r0]
+
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1
+        ldr r1,=CYGARC_HAL_LPC229x_REG_BCFG1_VAL
+        str r1, [r0]
+
+        // set-up ethernet chip bus
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG2
+        ldr r1,=CYGARC_HAL_LPC229x_REG_BCFG2_VAL
+        str r1, [r0]
+.endm
+		
+.macro _gpio_init
+        // enable  RX and TX on UART0 and UART1
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE	
+        ldr r1,=0x00050005
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL0]
+.endm
+
+.macro  _block
+        ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
+        ldr r1,=(1<<8)
+        str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0CLR]
+2:
+        nop
+        b 2
+.endm
+#define PLATFORM_BLOCK _block 
+//===========================================================================*/
+                        
+#if defined(CYG_HAL_STARTUP_ROM)
+.macro  _setup
+        _line_init
+        _led_init
+        _led 1
+        _pll_init
+
+        _ext_bus_init
+        _mem_init
+
+        _gpio_init
+.endm
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#else
+.macro  _setup
+        _line_init
+        _led_init
+        _led 1
+        _pll_init
+
+        _ext_bus_init
+
+        _gpio_init
+.endm        
+#endif
+
+#define PLATFORM_SETUP1 _setup
+
+//-----------------------------------------------------------------------------
+// end of hal_platform_setup.h
+#endif // CYGONCE_HAL_PLATFORM_SETUP_H
Index: hal/arm/lpc2xxx/phycore/current/include/plf_io.h
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/plf_io.h
diff -N hal/arm/lpc2xxx/phycore/current/include/plf_io.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/plf_io.h	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,68 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      phyCore LPC229x board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2006 National Instruments Corporation. 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):  Gratian Crisan
+// Contributors: 
+// Date:        2006-11-09
+// Purpose:     PHYTEC phyCORE LPC229x board specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/hal/hal_platform_ints.h>
+
+#define CYGARC_HAL_LPC2XXX_PHYCORE_LED0		(1<<8)		/* P0.8 */
+
+#define CYGARC_HAL_LPC2XXX_PHYCORE_ETH_BASE	0x82000300	/* CS2 + OFFSET(0x300) */
+/**
+ * The SMSC LAN91C111 ethernet chip is connected to CYGNUM_HAL_INTERRUPT_EINT0
+ * but EINT0 is buggy on LPC2294 and we cannot set the interrupt mode to high.
+ * We use the CAP0.2 interrupt instead.
+ */
+#define CYGARC_HAL_LPC2XXX_PHYCORE_ETH_IRQ	CYGNUM_HAL_INTERRUPT_TIMER0
+
+#define CYGARC_HAL_LPC2XXX_PHYCORE_CAPTURE	cyg_hal_lpc2xxx_phycore_capture
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
Index: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.h
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.h
diff -N hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.h	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,21 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x40000000)
+#define CYGMEM_REGION_sram_SIZE (0x00004000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W
+#define CYGMEM_REGION_ram (0x81000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1))
+
Index: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.ldi
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.ldi
diff -N hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_ram.ldi	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,28 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram : ORIGIN = 0x40000000, LENGTH = 0x4000
+    ram  : ORIGIN = 0x81000000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, 0x81006000, LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN(0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.h
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.h
diff -N hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.h	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,23 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_sram (0x40000000)
+#define CYGMEM_REGION_sram_SIZE (0x00004000)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_ram (0x81000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x00000000)
+#define CYGMEM_REGION_rom_SIZE (0x00040000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.ldi
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.ldi
diff -N hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.ldi
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/include/pkgconf/mlt_arm_lpc2xxx_phycore_rom.ldi	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,29 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    sram : ORIGIN = 0x40000000, LENGTH = 0x4000
+    ram  : ORIGIN = 0x81000000, LENGTH = 0x100000
+    rom  : ORIGIN = 0x00000000, LENGTH = 0x40000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (rom, 0x00000000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixed_vectors (sram, 0x40000400, LMA_EQ_VMA)
+    SECTION_data (ram, 0x81000000, FOLLOWING(.gcc_except_table))
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
Index: hal/arm/lpc2xxx/phycore/current/src/phycore_misc.c
===================================================================
RCS file: hal/arm/lpc2xxx/phycore/current/src/phycore_misc.c
diff -N hal/arm/lpc2xxx/phycore/current/src/phycore_misc.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ hal/arm/lpc2xxx/phycore/current/src/phycore_misc.c	9 Nov 2006 18:31:33 -0000
@@ -0,0 +1,277 @@
+/*==========================================================================
+//
+//      phycore_misc.c
+//
+//      HAL misc board support code for PHYTEC phyCore LPC229x
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+// Copyright (C) 2004 eCosCentric Limited 
+// Copyright (C) 2006 National Instruments Corporation. 
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Gratian Crisan 
+// Contributors: jani
+// Date:         2006-11-09
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_arm_lpc2xxx_phycore.h>
+#include <cyg/hal/hal_io.h>             // IO macros
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/plf_io.h>
+#include <cyg/hal/drv_api.h>
+
+typedef struct lpc229x_capture {
+	cyg_interrupt intr;
+   cyg_handle_t intr_handle;
+	cyg_uint32 ch0;
+	cyg_uint32 ch1;
+	cyg_uint32 ch2;
+	cyg_uint32 ch3;
+	cyg_uint32 overflow;
+} lpc229x_capture;
+lpc229x_capture phycore_capture;
+
+extern void cyg_hal_plf_serial_init(void);
+
+/**
+ * @brief Reads the capture registers or MR0 in case of overflow
+ *
+ * @param ir - timer interrupt register
+ *
+ * WARNING: this function runs inside the timer interrupt. Keep it short
+ */
+void cyg_hal_lpc2xxx_phycore_capture(cyg_uint32 ir)
+    __attribute__ ((section (".2ram.cyg_hal_lpc2xxx_phycore_capture")));
+    void cyg_hal_lpc2xxx_phycore_capture(cyg_uint32 ir)
+{
+    cyg_uint32 base = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+
+    if ( ir & CYGARC_HAL_LPC2XXX_REG_TxIR_CR0 ) {
+        HAL_READ_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxCR0, phycore_capture.ch0);
+    } else if ( ir & CYGARC_HAL_LPC2XXX_REG_TxIR_CR1 ) {
+        HAL_READ_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxCR1, phycore_capture.ch1);
+    } else if ( ir & CYGARC_HAL_LPC2XXX_REG_TxIR_CR2 ) {
+        HAL_READ_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxCR2, phycore_capture.ch2);
+    } else if ( ir & CYGARC_HAL_LPC2XXX_REG_TxIR_CR3 ) {
+        HAL_READ_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxCR3, phycore_capture.ch3);
+    } else if ( ir & CYGARC_HAL_LPC2XXX_REG_TxIR_MR0 ) {
+        phycore_capture.ch0 = 0;
+        phycore_capture.ch1 = 0;
+        phycore_capture.ch2 = 0;
+        phycore_capture.ch3 = 0;
+        phycore_capture.overflow++;
+    }
+}
+
+cyg_int32 cyg_hal_lpc2xxx_phycore_get_capture(cyg_uint8 ch, cyg_uint32 *val, cyg_uint32 *ovr)
+{
+    switch(ch) {
+        case 0:
+            *val = phycore_capture.ch0;
+            break;
+        case 1:
+            *val = phycore_capture.ch1;
+            break;
+        case 2:
+            *val = phycore_capture.ch2;
+            break;
+        case 3:
+            *val = phycore_capture.ch3;
+            break;
+        default:
+            return (-1);
+    }
+
+    *ovr = phycore_capture.overflow;
+    phycore_capture.overflow = 0;
+    return(0);
+}
+
+/**
+ * If SMSC LAN91CXX ethernet driver is not enabled we use the local ISR
+ * for capture. Otherwise cyg_hal_lpc2xxx_phycore_capture is called from
+ * ethernet driver.
+ */
+static cyg_uint32 phycore_capture_isr(cyg_vector_t vector, cyg_addrword_t data) 
+    __attribute__ ((section (".2ram.phycore_capture_isr")));
+    static cyg_uint32 phycore_capture_isr(cyg_vector_t vector, cyg_addrword_t data)
+{
+    cyg_uint32 ir;
+
+    cyg_drv_interrupt_mask(vector);
+
+    // stop timer and reset
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxTCR, 
+                     CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_RESET);
+
+    // read interrupt flags 
+    HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxIR, ir);
+
+    cyg_hal_lpc2xxx_phycore_capture(ir);
+
+    // re-arm interrupt
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE+ CYGARC_HAL_LPC2XXX_REG_TxIR, ir);
+
+    // start timer
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE + CYGARC_HAL_LPC2XXX_REG_TxTCR, 
+                     CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_ENABLE);
+
+    cyg_drv_interrupt_acknowledge(vector);
+    cyg_drv_interrupt_unmask(vector);
+    return CYG_ISR_HANDLED;
+}
+
+// Low bit of mask determines the on/off status of the LED. 0 means ON
+// and 1 is OFF!
+void hal_lpc2xxx_set_leds(int mask)
+{
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_IO_BASE + 
+                     CYGARC_HAL_LPC2XXX_REG_IO0SET, CYGARC_HAL_LPC2XXX_PHYCORE_LED0);
+    if (mask & 1)	
+        HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_IO_BASE + 
+                         CYGARC_HAL_LPC2XXX_REG_IO0CLR, CYGARC_HAL_LPC2XXX_PHYCORE_LED0);
+}
+
+void cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+	
+    if (initialized)
+        return;
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+
+cyg_uint32 cyg_hal_plf_get_pclock(void)
+{
+    cyg_uint32 div;
+    cyg_uint32 mul;
+    cyg_uint32 pll;
+
+    /* read current clock divider */
+    div = lpc_get_vpbdiv();
+    switch(div & 0x03) {
+        case 1:
+            div = 1;
+            break;
+        case 2:
+            div = 2;
+            break;
+        default:
+        case 0:
+            div = 4;
+            break;
+    }
+
+    /* read the current PLL value an mask out the clock multiplier value */
+    HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + CYGARC_HAL_LPC2XXX_REG_PLLSTAT, pll);
+    mul = (pll & 0x0F) + 1;
+
+    /* compute peripherial bus clock */	 
+    return ((mul * CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ) / div);
+}
+
+void cyg_hal_plf_hardware_init(void)
+{
+    CYG_ADDRESS base = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+    cyg_uint32 prescale = 0;
+    cyg_uint32 pclck = cyg_hal_plf_get_pclock();
+    cyg_uint32 reg = 0;
+
+    // stop timer and reset
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxTCR, CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_RESET);
+
+#ifdef CYGNUM_HAL_ARM_LPC2XXX_WITH_SMSC_LAN91CXX_1
+    // enable EINT0 pin and set it to CAP 0.2
+    HAL_READ_UINT32(CYGARC_HAL_LPC2XXX_REG_PIN_BASE + CYGARC_HAL_LPC2XXX_REG_PINSEL1, reg);
+    reg |= 0x03;
+    HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_PIN_BASE + CYGARC_HAL_LPC2XXX_REG_PINSEL1, reg);
+
+    // enable interrupt on capture and MR0 (overflow)
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxIR, 
+                     CYGARC_HAL_LPC2XXX_REG_TxIR_CR2 |
+                     CYGARC_HAL_LPC2XXX_REG_TxIR_MR0);
+
+    // enable channel: capture on rising edge and generate interrupt (Ethernet)
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxCCR, 
+                     CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2_RISE | 
+                     CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2);
+#else
+    // enable interrupt on  MR0 (overflow) the capture inptus will be enabled by user library
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxIR,
+                     CYGARC_HAL_LPC2XXX_REG_TxIR_MR0);
+
+    // set up interrupt handling
+    cyg_drv_interrupt_create( CYGNUM_HAL_INTERRUPT_TIMER0,		// vector
+                              0,					// queuing priority
+                              0,				   	// data pointer
+                              phycore_capture_isr,			// ISR
+                              NULL,				      	// DSR
+                              &(phycore_capture.intr_handle),
+                              &(phycore_capture.intr)
+        );
+    cyg_drv_interrupt_attach(phycore_capture.intr_handle);
+#endif // CYGNUM_HAL_ARM_LPC2XXX_WITH_SMSC_LAN91CXX_1
+
+    // compute prescale value so we will get a 1 MHz input clock for capture
+    prescale = pclck/1000000L;
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxPR, prescale);
+
+    // set MR0 to detect an overflow
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxMR0, 0xFFFFFFFF);
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxMCR, CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_INT);
+
+    // enable timer
+    HAL_WRITE_UINT32(base + CYGARC_HAL_LPC2XXX_REG_TxTCR, CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_ENABLE);
+#ifndef CYGNUM_HAL_ARM_LPC2XXX_WITH_SMSC_LAN91CXX_1
+    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER0);
+#endif
+}
+//--------------------------------------------------------------------------
+// EOF phycore_misc.c
Index: hal/arm/lpc2xxx/var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/lpc2xxx/var/current/ChangeLog,v
retrieving revision 1.4
diff -u -w -B -r1.4 ChangeLog
--- hal/arm/lpc2xxx/var/current/ChangeLog	8 May 2006 17:51:03 -0000	1.4
+++ hal/arm/lpc2xxx/var/current/ChangeLog	9 Nov 2006 18:31:33 -0000
@@ -1,3 +1,13 @@
+2006-11-09  Gratian Crisan  <gratian.crisan@ni.com>
+
+	* src/lpc2xxx_misc.c:
+	* include/hal_var_ints.h: 
+	Made RTC use CYGNUM_HAL_INTERRUPT_TIMER1 for PHYTEC Phycore 
+	LPC229x board. This board has a hardware bug that forces us 
+	to use TIMER0 for the ethernet chip.
+	* include/var_io.h: Added definitions for ADC start flags
+	
+	
 2006-05-08  Andy Jackson <andy@grapevinetech.co.uk>
  
 	* src/lpc2xxx_misc.c: Fixed issue with VPBDIV initialisation on
Index: hal/arm/lpc2xxx/var/current/include/hal_var_ints.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/lpc2xxx/var/current/include/hal_var_ints.h,v
retrieving revision 1.2
diff -u -w -B -r1.2 hal_var_ints.h
--- hal/arm/lpc2xxx/var/current/include/hal_var_ints.h	7 May 2006 18:36:18 -0000	1.2
+++ hal/arm/lpc2xxx/var/current/include/hal_var_ints.h	9 Nov 2006 18:31:33 -0000
@@ -96,8 +96,11 @@
 #define CYGNUM_HAL_ISR_COUNT         (CYGNUM_HAL_ISR_MAX+1)
 
 //The vector used by the Real time clock
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+#define CYGNUM_HAL_INTERRUPT_RTC     CYGNUM_HAL_INTERRUPT_TIMER1
+#else
 #define CYGNUM_HAL_INTERRUPT_RTC     CYGNUM_HAL_INTERRUPT_TIMER0
-
+#endif
 // Other entries here moved to variant specific include file
 // This is included here to avoid breaking anything
 #include <cyg/hal/lpc2xxx_misc.h>
Index: hal/arm/lpc2xxx/var/current/include/var_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/lpc2xxx/var/current/include/var_io.h,v
retrieving revision 1.2
diff -u -w -B -r1.2 var_io.h
--- hal/arm/lpc2xxx/var/current/include/var_io.h	7 May 2006 18:36:18 -0000	1.2
+++ hal/arm/lpc2xxx/var/current/include/var_io.h	9 Nov 2006 18:31:35 -0000
@@ -426,6 +426,8 @@
 #define CYGARC_HAL_LPC2XXX_REG_ADCR                     0x0000
 #define CYGARC_HAL_LPC2XXX_REG_ADCR_BURST               (1<<16)
 #define CYGARC_HAL_LPC2XXX_REG_ADCR_PDN                 (1<<21)
+#define CYGARC_HAL_LPC2XXX_REG_ADCR_NO_START            (0<<24)
+#define CYGARC_HAL_LPC2XXX_REG_ADCR_START_NOW           (1<<24)
 #define CYGARC_HAL_LPC2XXX_REG_ADCR_EDGE                (1<<27)
 #define CYGARC_HAL_LPC2XXX_REG_ADDR                     0x0004
 #define CYGARC_HAL_LPC2XXX_REG_ADDR_OVERRUN             (1<<30)
Index: hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c,v
retrieving revision 1.4
diff -u -w -B -r1.4 lpc2xxx_misc.c
--- hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c	8 May 2006 17:51:03 -0000	1.4
+++ hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c	9 Nov 2006 18:31:35 -0000
@@ -95,17 +95,22 @@
 
 // -------------------------------------------------------------------------
 // eCos clock support
-// Use TIMER0
+// Use TIMER0 or TIMER1 for buggy Phycore LPC229x
 static cyg_uint32 _period;
 
 void hal_clock_initialize(cyg_uint32 period)
 {
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+    CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE;
+#else
     CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+#endif //CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
 
+    _period = period;
     period = period/(lpc_cclk/lpc_pclk);
 
     // Disable and reset counter
-    HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 2);
+    HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_RESET);
     
     // set prescale register to 0
     HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxPR, 0);
@@ -119,26 +124,32 @@
                      CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET);
 
     // Enable counter
-    HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, 1);
+    HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTCR, CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_ENABLE);
 }
 
 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
 {
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+    CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE;
+#else
     CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
-
-    HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxIR, 
-                     CYGARC_HAL_LPC2XXX_REG_TxIR_MR0);  // Clear interrupt
+#endif //CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
 
     if (period != _period) {
         hal_clock_initialize(period);
     }
-    _period = period;
 
+    HAL_WRITE_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxIR, 
+                     CYGARC_HAL_LPC2XXX_REG_TxIR_MR0);  // Clear interrupt
 }
 
 void hal_clock_read(cyg_uint32 *pvalue)
 {
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+    CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE;
+#else
     CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE;
+#endif //CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
     cyg_uint32 val;
 
     HAL_READ_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTC, val);
@@ -155,7 +166,11 @@
     CYG_ADDRESS timer = CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE;
     cyg_uint32 stat;
     cyg_uint64 ticks;
+    cyg_uint32 ints;
 
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+    HAL_DISABLE_INTERRUPTS(ints);
+#endif
     // Calculate how many timer ticks the required number of
     // microseconds equate to. We do this calculation in 64 bit
     // arithmetic to avoid overflow.
@@ -180,6 +195,11 @@
     do {
         HAL_READ_UINT32(timer+CYGARC_HAL_LPC2XXX_REG_TxTC, stat);
     } while (stat < ticks);
+
+#if CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA
+    hal_clock_initialize(_period);
+    HAL_RESTORE_INTERRUPTS(ints);
+#endif
 }
 
 // -------------------------------------------------------------------------
 