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Re: Fixed some bugs in hal_io.h
- From: David Fernandez <dfernandez at cct dot co dot uk>
- To: ecos-patches at ecos dot sourceware dot org
- Date: Tue, 02 Jan 2007 13:30:17 +0000
- Subject: Re: Fixed some bugs in hal_io.h
- Organization: Concurrent Technologies, Plc
- References: <458754BB.1070406@eCosCentric.com> <1167731561.2878.24.camel@software.cct.co.uk>
- Reply-to: dfernandez at cct dot co dot uk
There you are the last patch revised.
Regarding the r-value compatibility problem, I've put an option to allow
that "extended" behaviour, set to 0 by default.
Have fun.
Index: hal/i386/arch/current/ChangeLog
===================================================================
RCS file: /home/cvs/cvsroot/dfernandez/Projects/ecos/packages/hal/i386/arch/current/ChangeLog,v
retrieving revision 1.1.1.1
diff -p -u -5 -r1.1.1.1 ChangeLog
--- hal/i386/arch/current/ChangeLog 2006/06/26 10:53:35 1.1.1.1
+++ hal/i386/arch/current/ChangeLog 2007/01/02 13:22:12
@@ -1,5 +1,16 @@
+2007-01-02 David Fernandez <dfernandez@cct.co.uk>
+
+ * cdl/hal_i386.cdl: Modified to add new option CYGSEM_HAL_IO_READ_RVALUES
+ * include/hal_io.h: Modified to optionally allow I/O reads to work as
+ rvalues.
+
+2006-12-18 David Fernandez <dfernandez@cct.co.uk>
+
+ * include/hal_io.h: Modified to fix bugs regarding STRING macros.
+ Slight reformat.
+
2005-09-19 David Vrabel <dvrabel@arcom.com>
* src/redboot_linux_exec.c: No need to include pcmb_serial.h.
2005-07-18 David Vrabel <dvrabel@arcom.com>
Index: hal/i386/arch/current/cdl/hal_i386.cdl
===================================================================
RCS file: /home/cvs/cvsroot/dfernandez/Projects/ecos/packages/hal/i386/arch/current/cdl/hal_i386.cdl,v
retrieving revision 1.1.1.1
diff -p -u -5 -r1.1.1.1 hal_i386.cdl
--- hal/i386/arch/current/cdl/hal_i386.cdl 2006/06/26 10:53:35 1.1.1.1
+++ hal/i386/arch/current/cdl/hal_i386.cdl 2007/01/02 13:22:12
@@ -74,97 +74,115 @@ cdl_package CYGPKG_HAL_I386 {
@rm vectors.tmp
}
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/i386.ld
- $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+ $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(filter-out -fno-rtti -Woverloaded-virtual,$(CFLAGS)) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail -n +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
cdl_component CYGPKG_HAL_SMP_SUPPORT {
- display "SMP support"
- default_value 0
- requires { CYGHWR_HAL_I386_FPU_SWITCH_LAZY == 0 }
+ display "SMP support"
+ default_value 0
+ requires { CYGHWR_HAL_I386_FPU_SWITCH_LAZY == 0 }
+ requires { CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK == 1 }
- cdl_option CYGPKG_HAL_SMP_CPU_MAX {
- display "Max number of CPUs supported"
- flavor data
- default_value 2
- }
+ cdl_option CYGPKG_HAL_SMP_CPU_MAX {
+ display "Max number of CPUs supported"
+ flavor data
+ default_value 2
+ }
}
cdl_component CYGHWR_HAL_I386_FPU {
- display "Enable I386 FPU support"
- default_value 1
- description "This component enables support for the
- I386 floating point unit."
-
- cdl_option CYGHWR_HAL_I386_FPU_SWITCH_LAZY {
- display "Use lazy FPU state switching"
- flavor bool
- default_value 1
-
- description "
- This option enables lazy FPU state switching.
- The default behaviour for eCos is to save and
- restore FPU state on every thread switch, interrupt
- and exception. While simple and deterministic, this
- approach can be expensive if the FPU is not used by
- all threads. The alternative, enabled by this option,
- is to use hardware features that allow the FPU state
- of a thread to be left in the FPU after it has been
- descheduled, and to allow the state to be switched to
- a new thread only if it actually uses the FPU. Where
- only one or two threads use the FPU this can avoid a
- lot of unnecessary state switching."
- }
+ display "Enable I386 FPU support"
+ default_value 1
+ description "
+ This component enables support for the I386 floating point unit.
+ "
+
+ cdl_option CYGHWR_HAL_I386_FPU_SWITCH_LAZY {
+ display "Use lazy FPU state switching"
+ flavor bool
+ default_value 1
+
+ description "
+ This option enables lazy FPU state switching.
+ The default behaviour for eCos is to save and
+ restore FPU state on every thread switch, interrupt
+ and exception. While simple and deterministic, this
+ approach can be expensive if the FPU is not used by
+ all threads. The alternative, enabled by this option,
+ is to use hardware features that allow the FPU state
+ of a thread to be left in the FPU after it has been
+ descheduled, and to allow the state to be switched to
+ a new thread only if it actually uses the FPU. Where
+ only one or two threads use the FPU this can avoid a
+ lot of unnecessary state switching.
+ "
+ }
}
cdl_component CYGHWR_HAL_I386_PENTIUM {
- display "Enable Pentium class CPU features"
- default_value 0
- description "This component enables support for various
- features of Pentium class CPUs."
-
- cdl_option CYGHWR_HAL_I386_PENTIUM_SSE {
- display "Save/Restore SSE registers on context switch"
- flavor bool
- default_value 0
-
- description "
- This option enables SSE state switching. The default
- behaviour for eCos is to ignore the SSE registers.
- Enabling this option adds SSE state information to
- every thread context."
- }
-
- cdl_option CYGHWR_HAL_I386_PENTIUM_GDB_REGS {
- display "Support extra Pentium registers in GDB stub"
- flavor bool
- default_value 0
-
- description "
- This option enables support for extra Pentium registers
- in the GDB stub. These are registers such as CR0-CR4, and
- all MSRs. Not all GDBs support these registers, so the
- default behaviour for eCos is to not include them in the
- GDB stub support code."
- }
+ display "Enable Pentium class CPU features"
+ default_value 0
+ description "This component enables support for various
+ features of Pentium class CPUs.
+ "
+
+ cdl_option CYGHWR_HAL_I386_PENTIUM_SSE {
+ display "Save/Restore SSE registers on context switch"
+ flavor bool
+ default_value 0
+
+ description "
+ This option enables SSE state switching. The default
+ behaviour for eCos is to ignore the SSE registers.
+ Enabling this option adds SSE state information to
+ every thread context.
+ "
+ }
+
+ cdl_option CYGHWR_HAL_I386_PENTIUM_GDB_REGS {
+ display "Support extra Pentium registers in GDB stub"
+ flavor bool
+ default_value 0
+
+ description "
+ This option enables support for extra Pentium registers
+ in the GDB stub. These are registers such as CR0-CR4, and
+ all MSRs. Not all GDBs support these registers, so the
+ default behaviour for eCos is to not include them in the
+ GDB stub support code.
+ "
+ }
}
cdl_option CYGBLD_LINKER_SCRIPT {
- display "Linker script"
- flavor data
- no_define
- calculated { "src/i386.ld" }
+ display "Linker script"
+ flavor data
+ no_define
+ calculated { "src/i386.ld" }
}
+ cdl_option CYGSEM_HAL_IO_READ_RVALUES {
+ display "Define HAL_READ_UINTx macros as r-values"
+ description "
+ Unless this option is active, the I/O read macros will be
+ void typed procedures. Otherwise, they may be used as values in
+ a expression.
+ "
+
+ flavor bool
+ default_value 0
+ }
+
cdl_interface CYGINT_HAL_I386_MEM_REAL_REGION_TOP {
- display "Implementations of hal_i386_mem_real_region_top()"
+ display "Implementations of hal_i386_mem_real_region_top()"
}
cdl_component CYGPKG_REDBOOT_I386_LINUX_EXEC {
display "Provide the exec command in RedBoot"
flavor none
@@ -174,14 +192,16 @@ cdl_package CYGPKG_HAL_I386 {
from RedBoot. The component is enabled/disabled from
RedBoots CDL."
compile -library=libextras.a redboot_linux_exec.c
cdl_option CYGHWR_REDBOOT_I386_TRAMPOLINE_ADDRESS {
- display "Address for the trampoline code"
- flavor data
- default_value 0x7C000
- description "This is the address to where the trampoline code is
- copied. The trampoline copies the image to its
- final location and jumps to its entry point."
+ display "Address for the trampoline code"
+ flavor data
+ default_value 0x7C000
+ description "
+ This is the address to where the trampoline code is
+ copied. The trampoline copies the image to its
+ final location and jumps to its entry point.
+ "
}
}
}
Index: hal/i386/arch/current/include/hal_io.h
===================================================================
RCS file: /home/cvs/cvsroot/dfernandez/Projects/ecos/packages/hal/i386/arch/current/include/hal_io.h,v
retrieving revision 1.1.1.1
diff -p -u -5 -r1.1.1.1 hal_io.h
--- hal/i386/arch/current/include/hal_io.h 2006/06/26 10:53:35 1.1.1.1
+++ hal/i386/arch/current/include/hal_io.h 2007/01/02 13:22:12
@@ -67,33 +67,46 @@
// IO Register address.
// This type is for recording the address of an IO register.
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
+
//-----------------------------------------------------------------------------
// BYTE Register access.
// Individual and vectorized access to 8 bit registers.
+#ifdef CYGSEM_HAL_IO_READ_RVALUES
+#define HAL_READ_UINT8( _register_, _value_ ) \
+({ \
+ asm volatile( \
+ " xor %%eax,%%eax \n" \
+ " inb %%dx, %%al \n" \
+ : "=a" (_value_) \
+ : "d" (_register_) \
+ ); \
+ (_value_); \
+})
+#else // ! CYGSEM_HAL_IO_READ_RVALUES
#define HAL_READ_UINT8( _register_, _value_ ) \
+CYG_MACRO_START \
+ asm volatile( \
+ " xor %%eax,%%eax \n" \
+ " inb %%dx, %%al \n" \
+ : "=a" (_value_) \
+ : "d" (_register_) \
+ ); \
+CYG_MACRO_END
+#endif // ! CYGSEM_HAL_IO_READ_RVALUES
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
-{ \
- asm volatile ( "xor %%eax,%%eax ;" \
- "inb %%dx, %%al" \
- : "=a" (_value_) \
- : "d"(_register_) \
- ); \
-} \
-CYG_MACRO_END
-
-#define HAL_WRITE_UINT8( _register_, _value_ ) \
-CYG_MACRO_START \
-{ \
- asm volatile ( "outb %%al,%%dx" \
- : \
- : "a" (_value_), "d"(_register_) \
- ); \
-} \
+ asm volatile( \
+ " outb %%al,%%dx \n" \
+ : \
+ : "a" (_value_), \
+ "d" (_register_) \
+ ); \
CYG_MACRO_END
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
! Not supported MACRO ! \
@@ -102,103 +115,142 @@ CYG_MACRO_END
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
! Not supported MACRO ! \
CYG_MACRO_END
-#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_) \
-CYG_MACRO_START \
- asm volatile ( "insb" \
- : \
- : "c" (_count_), "d"(_register_), "D"(_buf_) \
- ); \
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_BYTE m[_count_]; } *mp; \
+ asm volatile( \
+ " rep insb \n" \
+ : "=m" (*(mp) (_buf_)) \
+ : "c" (_count_), \
+ "d" (_register_), \
+ "D" (_buf_) \
+ ); \
CYG_MACRO_END
-#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_) \
-CYG_MACRO_START \
- asm volatile ( "outsb" \
- : \
- : "c" (_count_), "d"(_register_), "S"(_buf_) \
- ); \
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_BYTE m[_count_]; } *mp; \
+ asm volatile( \
+ " rep outsb \n" \
+ : \
+ : "c" (_count_), \
+ "d" (_register_), \
+ "S" (_buf_), \
+ "m" (*(mp) (_buf_)) \
+ ); \
CYG_MACRO_END
//-----------------------------------------------------------------------------
// 16 bit access.
// Individual and vectorized access to 16 bit registers.
+#ifdef CYGSEM_HAL_IO_READ_RVALUES
+#define HAL_READ_UINT16( _register_, _value_ ) \
+({ \
+ asm volatile( \
+ " xor %%eax,%%eax \n" \
+ " inw %%dx, %%ax \n" \
+ : "=a" (_value_) \
+ : "d" (_register_) \
+ ); \
+ (_value_); \
+})
+#else // ! CYGSEM_HAL_IO_READ_RVALUES
#define HAL_READ_UINT16( _register_, _value_ ) \
+CYG_MACRO_START \
+ asm volatile( \
+ " xor %%eax,%%eax \n" \
+ " inw %%dx, %%ax \n" \
+ : "=a" (_value_) \
+ : "d" (_register_) \
+ ); \
+CYG_MACRO_END
+#endif // ! CYGSEM_HAL_IO_READ_RVALUES
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
-{ \
- asm volatile ( "xor %%eax,%%eax ;" \
- "inw %%dx, %%ax" \
- : "=a" (_value_) \
- : "d"(_register_) \
- ); \
-} \
-CYG_MACRO_END
-
-#define HAL_WRITE_UINT16( _register_, _value_ ) \
-CYG_MACRO_START \
-{ \
- asm volatile ( "outw %%ax,%%dx" \
- : \
- : "a" (_value_), "d"(_register_) \
- ); \
-} \
+ asm volatile( \
+ " outw %%ax,%%dx \n" \
+ : \
+ : "a" (_value_), \
+ "d" (_register_) \
+ ); \
CYG_MACRO_END
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
! Not supported MACRO ! \
CYG_MACRO_END
-
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
! Not supported MACRO ! \
CYG_MACRO_END
-
-#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
- CYG_MACRO_START \
- asm volatile ( "insw" \
- : \
- : "c" (_count_), "d"(_register_), "D"(_buf_) \
- ); \
- CYG_MACRO_END
-#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \
- CYG_MACRO_START \
- asm volatile ( "outsw" \
- : \
- : "c" (_count_), "d"(_register_), "S"(_buf_) \
- ); \
- CYG_MACRO_END
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_UINT16 m[_count_]; } *mp; \
+ asm volatile( \
+ " rep insw \n" \
+ : "=m" (*(mp) (_buf_)) \
+ : "c" (_count_), \
+ "d" (_register_), \
+ "D" (_buf_) \
+ ); \
+CYG_MACRO_END
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_ ) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_UINT16 m[_count_]; } *mp; \
+ asm volatile( \
+ " rep outsw \n" \
+ : \
+ : "c" (_count_), \
+ "d" (_register_), \
+ "S" (_buf_), \
+ "m" (*(mp) (_buf_)) \
+ ); \
+CYG_MACRO_END
//-----------------------------------------------------------------------------
// 32 bit access.
// Individual and vectorized access to 32 bit registers.
+#ifdef CYGSEM_HAL_IO_READ_RVALUES
+#define HAL_READ_UINT32( _register_, _value_ ) \
+({ \
+ asm volatile( \
+ " inl %%dx, %%eax \n" \
+ : "=a" (_value_) \
+ : "d" (_register_) \
+ ); \
+ (_value_); \
+})
+#else // ! CYGSEM_HAL_IO_READ_RVALUES
#define HAL_READ_UINT32( _register_, _value_ ) \
+CYG_MACRO_START \
+ asm volatile( \
+ " inl %%dx, %%eax \n" \
+ : "=a" (_value_) \
+ : "d" (_register_) \
+ ); \
+CYG_MACRO_END
+#endif // ! CYGSEM_HAL_IO_READ_RVALUES
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
-{ \
- asm volatile ( "inl %%dx, %%eax" \
- : "=a" (_value_) \
- : "d"(_register_) \
- ); \
-} \
-CYG_MACRO_END
-
-#define HAL_WRITE_UINT32( _register_, _value_ ) \
-CYG_MACRO_START \
-{ \
- asm volatile ( "outl %%eax,%%dx" \
- : \
- : "a" (_value_), "d"(_register_) \
- ); \
-} \
+ asm volatile( \
+ " outl %%eax,%%dx \n" \
+ : \
+ : "a" (_value_), \
+ "d" (_register_) \
+ ); \
CYG_MACRO_END
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
! Not supported MACRO ! \
@@ -207,38 +259,97 @@ CYG_MACRO_END
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
! Not supported MACRO ! \
CYG_MACRO_END
-#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \
- CYG_MACRO_START \
- asm volatile ( "insl" \
- : \
- : "c" (_count_), "d"(_register_), "D"(_buf_) \
- ); \
- CYG_MACRO_END
+#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_UINT32 m[_count_]; } *mp; \
+ asm volatile( \
+ " rep insl \n" \
+ : "=m" (*(mp) (_buf_)) \
+ : "c" (_count_), \
+ "d" (_register_), \
+ "D" (_buf_) \
+ ); \
+CYG_MACRO_END
-#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_) \
- CYG_MACRO_START \
- asm volatile ( "outsl" \
- : \
- : "c" (_count_), "d"(_register_), "S"(_buf_) \
- ); \
- CYG_MACRO_END
+#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_ ) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_UINT32 m[_count_]; } *mp; \
+ asm volatile( \
+ " outsl \n" \
+ : \
+ : "c" (_count_), \
+ "d" (_register_), \
+ "S" (_buf_), \
+ "m" (*(mp) (_buf)) \
+ ); \
+CYG_MACRO_END
//-----------------------------------------------------------------------------
-
// Macros for acessing shared memory structures
-#define HAL_READMEM_UINT8( _reg_, _val_ ) ((_val_) = *((volatile CYG_BYTE *)(_reg_)))
-#define HAL_WRITEMEM_UINT8( _reg_, _val_ ) (*((volatile CYG_BYTE *)(_reg_)) = (_val_))
+#define HAL_READMEM_UINT8( _reg_, _val_ ) \
+ ((_val_) = *((volatile CYG_BYTE *)(_reg_)))
+#define HAL_WRITEMEM_UINT8( _reg_, _val_ ) \
+ (*((volatile CYG_BYTE *)(_reg_)) = (_val_))
+
+#define HAL_READMEM_UINT16( _reg_, _val_ ) \
+ ((_val_) = *((volatile CYG_WORD16 *)(_reg_)))
+#define HAL_WRITEMEM_UINT16( _reg_, _val_ ) \
+ (*((volatile CYG_WORD16 *)(_reg_)) = (_val_))
+
+#define HAL_READMEM_UINT32( _reg_, _val_ ) \
+ ((_val_) = *((volatile CYG_WORD32 *)(_reg_)))
+#define HAL_WRITEMEM_UINT32( _reg_, _val_ ) \
+ (*((volatile CYG_WORD32 *)(_reg_)) = (_val_))
+
+#define HAL_STRCOPY_UINT32( _va1_, _va2_, _count_) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_BYTE m[_count_]; \
+ } *mp; \
+ asm volatile( \
+ " rep movsl \n" \
+ : \
+ : "=m" (*(mp) (_va2_)) \
+ : "c" (_count_), \
+ "S" (_va1_), \
+ "D" (_va2_), \
+ "m" (*(mp) (_va1_)) \
+ ); \
+CYG_MACRO_END
+
+#define HAL_STRCOPY_UINT16( _va1_, _va2_, _count_) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_UINT16 m[_count_];\
+ } *mp; \
+ asm volatile( \
+ " rep movsw \n" \
+ : \
+ : "=m" (*(mp) (_va2_)) \
+ : "c" (_count_), \
+ "S" (_va1_), \
+ "D" (_va2_), \
+ "m" (*(mp) (_va1_)) \
+ ); \
+CYG_MACRO_END
-#define HAL_READMEM_UINT16( _reg_, _val_ ) ((_val_) = *((volatile CYG_WORD16 *)(_reg_)))
-#define HAL_WRITEMEM_UINT16( _reg_, _val_ ) (*((volatile CYG_WORD16 *)(_reg_)) = (_val_))
+#define HAL_STRCOPY_UINT8( _va1_, _va2_, _count_ ) \
+CYG_MACRO_START \
+ typedef volatile struct { CYG_UINT32 m[_count_];\
+ } *mp; \
+ asm volatile( \
+ " rep movsb \n" \
+ : "=m" (*(mp) (_va2_)) \
+ : "c" (_count_), \
+ "S" (_va1_), \
+ "D" (_va2_), \
+ "m" (*(mp) (_va1_)) \
+ ); \
+CYG_MACRO_END
-#define HAL_READMEM_UINT32( _reg_, _val_ ) ((_val_) = *((volatile CYG_WORD32 *)(_reg_)))
-#define HAL_WRITEMEM_UINT32( _reg_, _val_ ) (*((volatile CYG_WORD32 *)(_reg_)) = (_val_))
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_IO_H
// End of hal_io.h