Re: AT91 EMAC

["John Eigelaar" <jeigelaar at mweb dot co dot za>]

> Hi John
> 
> Could you explain the background to doing a reset at the end of
> hal_plf_eth_init(). I would like to understand this a bit more. It
> seems to be causing my JTAG debugger a problem.
> 
>       Thanks
>         Andrew

The DM9161A Phy latches the state of several pins on startup. These
determine the operating mode of the phy. Because of the AT91 GPIO starting
as inputs with pull-ups enabled by default all these pins are read as high
on phy startup. This causes the phy to be in MII mode with the MII
interface isolated from the processor. The most important pins though is
the TEST input of the phy and the POWERDOWN input which causes the phy to
be in test mode as well as powered down mode.

The pins thus needs to be setup and the phy reset through the NRST output
for it to be in proper operational mode.

The more elegant sollution to this is to do a soft reset of the PHY via
the serial management inetrface and the setup all the neccessary functions.

I am not sure though whether this will clear the testmode properly though.

The latter sollution however means the duplication of the PHY read/write
register code in the driver.

John Eigelaar