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Re: [ECOS] AT91SAM7S RTC speed


Thanks for the patch. I've included the fix for the RTC and SPI
calculation, plus the typo's in var_io.h

             Andrew
Index: hal/arm/at91/at91sam7s/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v
retrieving revision 1.19
diff -u -r1.19 ChangeLog
--- hal/arm/at91/at91sam7s/current/ChangeLog	4 Sep 2008 06:10:22 -0000	1.19
+++ hal/arm/at91/at91sam7s/current/ChangeLog	19 Oct 2008 14:49:14 -0000
@@ -1,3 +1,9 @@
+2008-10-19  Igor B. Poretsky <poretsky@mlbox.ru>
+	    Andrew Lunn  <andrew.lunn@ascom.ch>
+
+	* cdl/hal_arm_at91sam7s.cdl: Fix calculation of RTC period. The TC
+	uses a different divider as the PIT.
+
 2008-09-04  John Eigelaar  <jeigelaar@mweb.co.za>
 
 	* cdl/hal_arm_at91sam7s.cdl: Set MOR OSCCOUNT and PLL Count to
Index: hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v
retrieving revision 1.11
diff -u -r1.11 hal_arm_at91sam7s.cdl
--- hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl	4 Sep 2008 06:10:22 -0000	1.11
+++ hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl	19 Oct 2008 14:49:15 -0000
@@ -168,9 +168,14 @@
             display       "Real-time clock period"
             flavor        data
             legal_values  1 to 0xffff 
-            calculated    ((CYGNUM_HAL_RTC_NUMERATOR * CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/16) / CYGNUM_HAL_RTC_DENOMINATOR / 1000000000)
-            description   "
-                CYGNUM_HAL_RTC_PERIOD : (CYGNUM_HAL_RTC_NUMERATOR * CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/16) / CYGNUM_HAL_RTC_DENOMINATOR / 1000000000 "
+            calculated    { (CYGNUM_HAL_RTC_NUMERATOR * 
+                             CYGNUM_HAL_ARM_AT91_CLOCK_SPEED /
+                             (CYGBLD_HAL_ARM_AT91_TIMER_TC ? 32 : 16) / 
+                             CYGNUM_HAL_RTC_DENOMINATOR / 
+                             1000000000
+                            )
+                          }
+            description   "Value to program into the RTC clock generator."
         }
     }
     
Index: hal/arm/at91/var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v
retrieving revision 1.42
diff -u -r1.42 ChangeLog
--- hal/arm/at91/var/current/ChangeLog	4 Sep 2008 05:50:54 -0000	1.42
+++ hal/arm/at91/var/current/ChangeLog	19 Oct 2008 14:49:15 -0000
@@ -1,3 +1,7 @@
+2008-10-19  Igor B. Poretsky <poretsky@mlbox.ru>
+
+	* include/var_io.h Fixed various typos.
+
 2008-09-02  John Eigelaar <jeigelaar@mweb.co.za>
  
  	* include/var_io.h: Added support for a second flash controller.
Index: hal/arm/at91/var/current/include/var_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v
retrieving revision 1.21
diff -u -r1.21 var_io.h
--- hal/arm/at91/var/current/include/var_io.h	4 Sep 2008 05:50:54 -0000	1.21
+++ hal/arm/at91/var/current/include/var_io.h	19 Oct 2008 14:49:17 -0000
@@ -271,7 +271,7 @@
 #define AT91_USART_RXD2     AT91_PIN(0,0,22) // USART 2 receive data
 #define AT91_SPI_SPCK       AT91_PIN(0,0,23) // SPI Clock signal 
 #define AT91_SPI_MISO       AT91_PIN(0,0,24) // SPI Master In Slave Out 
-#define AT91_SPI_MOIS       AT91_PIN(0,0,25) // SPI Master Out Slave In 
+#define AT91_SPI_MOSI       AT91_PIN(0,0,25) // SPI Master Out Slave In 
 #define AT91_SPI_NPCS0      AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0
 #define AT91_SPI_NPCS1      AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1
 #define AT91_SPI_NPCS2      AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2
@@ -318,7 +318,7 @@
 #define AT91_PIO_PSR_RXD2    0x00400000 // USART 2 receive data
 #define AT91_PIO_PSR_SPCK    0x00800000 // SPI Clock signal 
 #define AT91_PIO_PSR_MISO    0x01000000 // SPI Master In Slave Out 
-#define AT91_PIO_PSR_MOIS    0x02000000 // SPI Master Out Slave In 
+#define AT91_PIO_PSR_MOSI    0x02000000 // SPI Master Out Slave In 
 #define AT91_PIO_PSR_NPCS0   0x04000000 // SPI Peripheral Chip Select 0
 #define AT91_PIO_PSR_NPCS1   0x08000000 // SPI Peripheral Chip Select 1
 #define AT91_PIO_PSR_NPCS2   0x10000000 // SPI Peripheral Chip Select 2
@@ -357,7 +357,7 @@
 #define AT91_DBG_DTXD       AT91_PIN(0,0,10) // Debug UART Transmit
 #define AT91_SPI_NPCS0      AT91_PIN(0,0,11) // SPI Chip Select 0
 #define AT91_SPI_MISO       AT91_PIN(0,0,12) // SPI Input
-#define AT91_SPI_MOIS       AT91_PIN(0,0,13) // SPI Output
+#define AT91_SPI_MOSI       AT91_PIN(0,0,13) // SPI Output
 #define AT91_SPI_SPCK       AT91_PIN(0,0,14) // SPI clock
 #define AT91_S2C_TF         AT91_PIN(0,0,15) // S2C Transmit Frame Sync
 #define AT91_S2C_TK         AT91_PIN(0,0,16) // S2C Transmit Clock
@@ -428,7 +428,7 @@
 #define AT91_PIO_PSR_DTXD     0x00000400 // Debug UART Transmit
 #define AT91_PIO_PSR_NPCS0    0x00000800 // SPI Chip Select 0
 #define AT91_PIO_PSR_MISO     0x00001000 // SPI Input
-#define AT91_PIO_PSR_MOIS     0x00002000 // SPI Output
+#define AT91_PIO_PSR_MOSI     0x00002000 // SPI Output
 #define AT91_PIO_PSR_SPCK     0x00004000 // SPI clock
 #define AT91_PIO_PSR_TF       0x00008000 // S2C Transmit Frame Sync
 #define AT91_PIO_PSR_TK       0x00010000 // S2C Transmit Clock
@@ -507,7 +507,7 @@
 #define AT91_SPI_NPCS2  AT91_PIN(0,0,14) // SPI 0 Chip Select 2 
 #define AT91_SPI_NPCS3  AT91_PIN(0,0,15) // SPI 0 Chip Select 3 
 #define AT91_SPI_MISO   AT91_PIN(0,0,16) // SPI 0 Master In Slave Out
-#define AT91_SPI_MOIS   AT91_PIN(0,0,17) // SPI 0 Master Out Slave In 
+#define AT91_SPI_MOSI   AT91_PIN(0,0,17) // SPI 0 Master Out Slave In 
 #define AT91_SPI_SPCK   AT91_PIN(0,0,18) // SPI 0 Clock
 #define AT91_CAN_CANRX  AT91_PIN(0,0,19) // CAN Receive
 #define AT91_CAN_CANTX  AT91_PIN(0,0,20) // CAN Transmit 
@@ -891,8 +891,8 @@
 #ifdef CYGHWR_HAL_ARM_AT91SAM7
 #define AT91_AIC_DCR    0x138 // Debug Control Register
 #define AT91_AIC_FFER   0x140 // Fast Forcing Enable Register
-#define AT91_AIC_FFDR   0x144 // Fast Forcing Enable Register
-#define AT91_AIC_FFSR   0x148 // Fast Forcing Enable Register
+#define AT91_AIC_FFDR   0x144 // Fast Forcing Disable Register
+#define AT91_AIC_FFSR   0x148 // Fast Forcing Status Register
 #endif // CYGHWR_HAL_ARM_AT91SAM7
 
 //=============================================================================
@@ -1262,7 +1262,7 @@
 #define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
 
 #define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
-#define AT91_PMC_PCER_ADC  (1 << 4) // Analog-to-Digital Conveter
+#define AT91_PMC_PCER_ADC  (1 << 4) // Analog-to-Digital Converter
 #define AT91_PMC_PCER_SPI  (1 << 5) // Serial Peripheral Interface
 #define AT91_PMC_PCER_US0  (1 << 6) // USART 0
 #define AT91_PMC_PCER_US1  (1 << 7) // USART 1
@@ -1297,7 +1297,7 @@
 #define AT91_PMC_PCER_TC2  (1 <<14) // Timer Counter 2
 #define AT91_PMC_PCER_CAN  (1 <<15) // Controller Area Network
 #define AT91_PMC_PCER_EMAC (1 <<16) // Ethernet MAC
-#define AT91_PMC_PCER_ADC  (1 <<17) // Analog-to-Digital Conveter
+#define AT91_PMC_PCER_ADC  (1 <<17) // Analog-to-Digital Converter
 #else // Something unknown
 
 #error Unknown AT91 variant
@@ -1814,10 +1814,10 @@
 #define AT91_SSC_TFMR_FSOS_LOW      (3<<16) //Low Level Frame Synch Output
 #define AT91_SSC_TFMR_FSOS_HIGH     (4<<16) //High Level Frame Synch Output
 #define AT91_SSC_TFMR_FSOS_TOGGLE   (5<<16) //Toggle Frame Synch Output
-#define AT91_SSC_RFMR_FSDEN_DEF     (0<<23) //Frame Sync is Default Data
-#define AT91_SSC_RFMR_FSDEN_TSHR    (1<<23) //Frame Sync is TSHR Data
-#define AT91_SSC_RFMR_FSEDGE_POS    (0<<24) //Intr on +ve edge of Frame Sync
-#define AT91_SSC_RFMR_FSEDGE_NEG    (1<<24) //Intr on -ve edge of Frame Sync
+#define AT91_SSC_TFMR_FSDEN_DEF     (0<<23) //Frame Sync is Default Data
+#define AT91_SSC_TFMR_FSDEN_TSHR    (1<<23) //Frame Sync is TSHR Data
+#define AT91_SSC_TFMR_FSEDGE_POS    (0<<24) //Intr on +ve edge of Frame Sync
+#define AT91_SSC_TFMR_FSEDGE_NEG    (1<<24) //Intr on -ve edge of Frame Sync
 #define AT91_SSC_RHR  (0x20)
 #define AT91_SSC_THR  (0x24)
 #define AT91_SSC_RSHR (0x30)
@@ -1856,8 +1856,8 @@
 
 #define AT91_SSC_PTCR_RXTEN  (1 << 0) //Receive Transfers Enabled
 #define AT91_SSC_PTCR_RXTDIS (1 << 1) //Receive Transfers Disabled 
-#define AT91_SSC_PTCR_TXTEN  (1 << 8) //Receive Transfers Enabled  
-#define AT91_SSC_PTCR_TXTDIS (1 << 9) //Receive Transfers Disabled 
+#define AT91_SSC_PTCR_TXTEN  (1 << 8) //Transmit Transfers Enabled  
+#define AT91_SSC_PTCR_TXTDIS (1 << 9) //Transmit Transfers Disabled 
 
 #endif
 
@@ -2563,7 +2563,7 @@
   CYG_MACRO_START                               \
   HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO);        \
   HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB);       \
-CYG_MACRO_END
+  CYG_MACRO_END
 
 // Configure a GPIO pin direction
 #define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_)            \
Index: devs/spi/arm/at91/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/spi/arm/at91/current/ChangeLog,v
retrieving revision 1.6
diff -u -r1.6 ChangeLog
--- devs/spi/arm/at91/current/ChangeLog	5 Mar 2007 17:08:11 -0000	1.6
+++ devs/spi/arm/at91/current/ChangeLog	19 Oct 2008 14:49:17 -0000
@@ -1,3 +1,8 @@
+2008-10-19  Igor B. Poretsky <poretsky@mlbox.ru>
+	
+	* src/spi_at91.c: Typo fixes from var_io.h.  Correctly calculate
+	  the board rate. Before it was two times too fast.
+
 2006-09-27  Andrew Lunn  <andrew.lunn@ascom.ch>
 
 	* src/spi_at91.c (spi_at91_transaction_begin): Don't use #ifdef
Index: devs/spi/arm/at91/current/src/spi_at91.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/spi/arm/at91/current/src/spi_at91.c,v
retrieving revision 1.6
diff -u -r1.6 spi_at91.c
--- devs/spi/arm/at91/current/src/spi_at91.c	5 Mar 2007 17:08:11 -0000	1.6
+++ devs/spi/arm/at91/current/src/spi_at91.c	19 Oct 2008 14:49:18 -0000
@@ -184,10 +184,10 @@
    //       in order to achieve better chip select control 
    //       in between transactions.
 
-   // Put SPI MISO, MOIS and SPCK pins into peripheral mode
+   // Put SPI MISO, MOSI and SPCK pins into peripheral mode
    HAL_ARM_AT91_PIO_CFG(AT91_SPI_SPCK);
    HAL_ARM_AT91_PIO_CFG(AT91_SPI_MISO);
-   HAL_ARM_AT91_PIO_CFG(AT91_SPI_MOIS);
+   HAL_ARM_AT91_PIO_CFG(AT91_SPI_MOSI);
    spi_at91_init_bus(&cyg_spi_at91_bus0);
 #endif
 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS1
@@ -197,7 +197,7 @@
    //       in order to achieve better chip select control 
    //       in between transactions.
 
-   // Put SPI MISO, MOIS and SPCK pins into peripheral mode
+   // Put SPI MISO, MOSI and SPCK pins into peripheral mode
    HAL_ARM_AT91_PIO_CFG(AT91_SPI1_SPCK);
    HAL_ARM_AT91_PIO_CFG(AT91_SPI1_MISO);
    HAL_ARM_AT91_PIO_CFG(AT91_SPI1_MOSI);
@@ -242,6 +242,7 @@
        if(spi_bus->cs_en[ctr])
        {
           HAL_ARM_AT91_GPIO_CFG_DIRECTION(spi_bus->cs_gpio[ctr],AT91_PIN_OUT);
+          HAL_ARM_AT91_GPIO_SET(spi_bus->cs_gpio[ctr]);
        }
     }
     // Call upper layer bus init
@@ -254,7 +255,7 @@
     cyg_uint32 stat;
     cyg_spi_at91_bus_t * spi_bus = (cyg_spi_at91_bus_t *)data;
     // Read the status register and disable
-    // the SPI int events that have occoured
+    // the SPI int events that have occurred
     
     HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR,   stat);
     HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_IDR, stat);
@@ -272,7 +273,7 @@
     cyg_uint32 stat;
     
     // Read the status register and 
-    // check for transfer completition
+    // check for transfer completion
     
     HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, stat);
 
@@ -298,7 +299,9 @@
     
     // Calculate SCBR from baud rate
     
-    scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (2*dev->cl_brate);
+    scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / dev->cl_brate;
+    if ((2*(CYGNUM_HAL_ARM_AT91_CLOCK_SPEED % dev->cl_brate)) >= dev->cl_brate)
+        scbr++;
 
     if (scbr < 2)
     {
@@ -310,7 +313,7 @@
     {
         dev->cl_div32 = 1;
         
-        scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (64*dev->cl_brate);
+        scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (32*dev->cl_brate);
 
         if (scbr < 2) 
         {
@@ -427,7 +430,7 @@
             // Unmask the SPI int
             cyg_drv_interrupt_unmask(spi_bus->interrupt_number);
         
-            // Wait for its completition
+            // Wait for its completion
             cyg_drv_dsr_lock();
             {
                 while (!spi_bus->transfer_end)
@@ -540,7 +543,7 @@
     HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
     
     /* As we are using this driver only in master mode with NPCS0 
-       configured as GPIO instead of a peripheral pin, it is neccessary 
+       configured as GPIO instead of a peripheral pin, it is necessary 
        for the Mode Failure detection to be switched off as this will
        cause havoc with the driver */ 
 

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