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new MCF5272 processor HAL
- From: Bart Veer <bartv at ecoscentric dot com>
- To: ecos-patches at sourceware dot org
- Date: Thu, 20 Nov 2008 22:51:20 +0000
- Subject: new MCF5272 processor HAL
This patch contributes eCosCentric's hal/m68k/mcfxxxx/mcf5272
processor HAL for the MCF5272 processor, replacing all the old code in
the same directory.
Bart
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/ChangeLog,v
retrieving revision 1.1
diff -u -p -r1.1 ChangeLog
--- ChangeLog 22 Apr 2004 12:55:09 -0000 1.1
+++ ChangeLog 20 Nov 2008 22:49:02 -0000
@@ -1,8 +1,186 @@
+2008-11-18 Bart Veer <bartv@ecoscentric.com>
+
+ * whole package. Replace the original M68K port.
+
+2008-11-17 Bart Veer <bartv@ecoscentric.com>
+
+ * cdl/hal_m68k_mcd5272.cdl, cdl/gpio.cdl, include/proc_arch.h,
+ include/proc_cache.h, include/proc.inc, include/proc_intr.h,
+ include/proc_io.h, src/mcf5272.c, src/mcf5272_profile.S: minor
+ clean-ups.
+
+2008-09-02 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_arch.h: allow platform HALs to override the
+ PROC_INIT() macro.
+
+2007-07-27 John Dallaway <jld@ecoscentric.com>
+
+ * cdl/hal_m68k_mcf52xx.cdl: Reference per-package documentation.
+
+2006-10-13 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_io.h (HAL_MCF52xx_ETHx_TXBD_DEF): fix naming of the
+ TXBD error conditions.
+
+2006-10-09 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc.inc: add utility macros for low-level bootstrap
+ (flash remapping etc.) to simplify most platform HALs.
+
+2006-09-11 Bart Veer <bartv@ecoscentric.com>
+
+ * cdl/gpio.cdl, cdl/hal_m68k_mcf52xx.cdl, src/gpio.c :
+ Rationalize pin naming.
+
+2006-09-10 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc.inc: take care to OR in the CSBR0 BW bits as per
+ the pin sampling on reset. Use more verbose names to distinguish
+ between registers and their values.
+
+ * include/proc_io.h (HAL_MCF52xx_MBAR): provide a default
+ definition if the platform HAL has not specified one.
+
+2006-09-08 Bart Veer <bartv@ecoscentric.com>
+
+ * cdl/hal_m68k_mcf5272.cdl: GPIO is now largely handled by the
+ processor HAL instead of the platform HAL. Diagnostics are now
+ handled by the variant HAL.
+
+ * src/mcf5272.c: add processor initialization code. The processor
+ HAL now largely takes care of GPIO pins, interrupts and
+ exceptions, so less has to be done by the platform HAL.
+
+ * src/mcf5272_profile.S: fix typo.
+
+ * include/proc_io.h: update to match variant HAL changes. The
+ processor HAL now picks up variant HAL definitions for the UARTs,
+ ethernet and QSPI which are largely compatible with the 5282.
+
+ * include/proc_intr.h: use HAL_DELAY_US() from the architectural
+ HAL. Add a reset macro which activates the watchdog.
+
+ * include/proc_cache.h: use updated register definitions.
+
+ * include/proc_arch.h: add processor init function and idle thread
+ action.
+
+ * include/proc.inc: add macros for handling the flash remapping,
+ system registers, and memory initialization.
+
+ * src/spi.c: instantiate the on-chip SPI bus device here.
+
+ * tests/iram1.c: new testcase for MCF5272 on-chip RAM
+
+ * cdl/gpio.cdl, src/gpio.c: make it easier for platform HALs to
+ define the GPIO pin connectivity.
+
+2006-09-06 Nick Garnett <nickg@ecoscentric.com>
+
+ * include/proc_io.h (HAL_MCF5272_QSPI_QCRn_QSPI_CS_CSn): Added
+ this macro to permit easier definition of demultiplexed SPI chip
+ selects.
+
+2005-04-15 Jonathan Larmour <jifl@eCosCentric.com>
+
+ * cdl/hal_m68k_mcf5272.cdl: Define a HAL processor variant header in
+ <pkgconf/system.h>
+
+2005-02-21 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_intr.h (HAL_CLOCK_INITIALIZE): fix initialization
+ values. Both the prescaler and the period were off by one.
+ Reported by Matthew Miller.
+
+ * src/mcf5272.c (hal_enable_profile_timer): similar adjustment for
+ the profile timer.
+
+2005-02-20 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_intr.h: implement HAL_CLOCK_LATENCY()
+
+2004-10-04 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_io.h (HAL_MCF5272_PBCNT_PBCNT5_TA): add missing
+ GPIO pin definition
+
+2004-06-24 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc.inc, src/mcf5272.c: move cacr and icr_pri shadow
+ copies from .data to .fixed_vectors, so that they can be shared
+ between RedBoot and the application.
+
+2004-06-22 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_intr.h (HAL_DELAY_US): try to give accurate timings
+ irrespective of whether or not the icache is enabled
+
+2004-05-17 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_io.h: add more SPI-related definitions
+
+2004-03-08 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_io.h (HAL_MCF52xx_ETH0_PROC_INIT): only connect the
+ phy pins if the ethernet driver expects a phy.
+
+ * cdl/hal_m68k_mcf5272.cdl: add calculated options for the legal
+ ISR priority range.
+
+2004-02-11 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_io.h: move cacr/acr/rambar/rombar definitions from
+ variant to processor HAL. Add processor-specific ethernet
+ initialization macro to allow the ethernet driver to be shared
+ between different coldfire processors. Add new HAL_MCF52xx() macro
+ to facilitate device driver sharing.
+
+ * include/proc_cache.h: cacr defines are now processor-specific,
+ rather than defined by the 52xx variant HAL.
+
+ * include/proc.inc: rework ISR vector extraction macros, to save
+ an instruction in the main VSR
+
+2003-11-13 Bart Veer <bartv@ecoscentric.com>
+
+ * src/mcf5272.c: fix typo in header
+
+2003-09-26 Bart Veer <bartv@ecoscentric.com>
+
+ * doc/mcf5272.sgml, cdl/hal_m68k_mcf5272.sgml,
+ include/proc_intr.h, src/mcf5272.c, src/mcf5272_profile.S:
+ Implement a profiling timer.
+
+2003-07-22 Bart Veer <bartv@ecoscentric.com>
+
+ * doc/mcf5272.sgml: fix various typos etc.
+
+2003-07-17 Bart Veer <bartv@ecoscentric.com>
+
+ * doc/mcf5272.sgml: Add documentation
+
+2003-07-08 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_io.h:
+ Make some UART definitions MCF52xx rather than MCF5272, so that
+ the generic driver can test for these and adapt to what the
+ current MCF52xx processor actually supports
+
+2003-07-05 Bart Veer <bartv@ecoscentric.com>
+
+ * include/proc_intr.h (HAL_MCF5272_EXTERNAL_INTERRUPTS):
+ Fix handling of external interrupts
+
+2003-06-04 Bart Veer <bartv@ecoscentric.com>
+
+ * New version of the M68K support
+
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
@@ -26,9 +204,6 @@
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
Index: cdl/gpio.cdl
===================================================================
RCS file: cdl/gpio.cdl
diff -N cdl/gpio.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ cdl/gpio.cdl 20 Nov 2008 22:49:04 -0000
@@ -0,0 +1,715 @@
+# ====================================================================
+#
+# gpio.cdl
+#
+# GPIO settings for a Freescale mcf5272
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+# -------------------------------------------
+# This file is part of eCos, the Embedded Configurable Operating System.
+# Copyright (C) 2006,2008 Free Software Foundation, Inc.
+#
+# eCos is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 or (at your option) any later version.
+#
+# eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with eCos; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+#
+# As a special exception, if other files instantiate templates or use macros
+# or inline functions from this file, or you compile this file and link it
+# with other works to produce a work based on this file, this file does not
+# by itself cause the resulting work to be covered by the GNU General Public
+# License. However the source code for this file must still be made available
+# in accordance with section (3) of the GNU General Public License.
+#
+# This exception does not invalidate any other reasons why a work based on
+# this file might be covered by the GNU General Public License.
+# -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+#######DESCRIPTIONBEGIN####
+#
+# Author(s): bartv
+# Date: 2006-07-10
+#
+#####DESCRIPTIONEND####
+#========================================================================
+
+cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA {
+ display "Configure port A pins"
+ flavor none
+ no_define
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0 {
+ display "Configure pin PA0"
+ flavor data
+ legal_values { "usb_tp" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_usb_tp") ? "usb_tp" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a0_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA0 can be configured as the USB TP signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1 {
+ display "Configure pin PA1"
+ flavor data
+ legal_values { "usb_rp" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_usb_rp") ? "usb_rp" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a1_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA1 can be configured as the USB RP signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2 {
+ display "Configure pin PA2"
+ flavor data
+ legal_values { "usb_rn" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_usb_rn") ? "usb_rn" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a2_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA2 can be configured as the USB RN signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3 {
+ display "Configure pin PA3"
+ flavor data
+ legal_values { "usb_tn" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_usb_tn") ? "usb_tn" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a3_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA3 can be configured as the USB TN signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4 {
+ display "Configure pin PA4"
+ flavor data
+ legal_values { "usb_susp" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_usb_susp") ? "usb_susp" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a4_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA4 can be configured as the USB suspend signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5 {
+ display "Configure pin PA5"
+ flavor data
+ legal_values { "usb_txen" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_usb_txen") ? "usb_txen" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a5_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA5 can be configured as the USB TxEn signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6 {
+ display "Configure pin PA6"
+ flavor data
+ legal_values { "usb_rxd" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_usb_rxd") ? "usb_rxd" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a6_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA6 can be configured as the USB RxD signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7 {
+ display "Configure pin PA7"
+ flavor data
+ legal_values { "qspi_cs3" "dout3" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_qspi_cs3") ? "qspi_cs3" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_dout3") ? "dout3" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a7_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA7 can be configured as the QSPI chip select 3 signal, the
+ PLIC DOUT3 signal, a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8 {
+ display "Configure pin PA8"
+ flavor data
+ legal_values { "fsc0_fsr0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_fsc0_fsr0") ? "fsc0_fsr0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a8_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA8 can be configured as the PLIC frame sync FSR0/FSC0 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9 {
+ display "Configure pin PA9"
+ flavor data
+ legal_values { "dgnt0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_dgnt0") ? "dgnt0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a9_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA9 can be configured as the PLIC D-Channel grant signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10 {
+ display "Configure pin PA10"
+ flavor data
+ legal_values { "dreq0_tp" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_dreq0") ? "dreq0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a10_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA10 can be configured as the PLIC D-Channel request signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11 {
+ display "Configure pin PA11"
+ flavor data
+ legal_values { "qspi_cs1" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_qspi_cs1") ? "qspi_cs1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a11_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA11 can be configured as the QSPI CS1 chip select signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12 {
+ display "Configure pin PA12"
+ flavor data
+ legal_values { "dfsc2" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_dfsc2") ? "dfsc2" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a12_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA12 can be configured as the PLIC delayed frame sync 2 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13 {
+ display "Configure pin PA13"
+ flavor data
+ legal_values { "dfsc3" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_dfsc3") ? "dfsc3" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a13_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA13 can be configured as the PLIC delayed frame sync 3 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14 {
+ display "Configure pin PA14"
+ flavor data
+ legal_values { "dreq1" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_dreq1") ? "dreq1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a14_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA14 can be configured as the PLIC D-channel request 1 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15 {
+ display "Configure pin PA15"
+ flavor data
+ legal_values { "dgnt1" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_dgnt1") ? "dgnt1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "a15_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PA15 can be configured as the PLIC D-channel grant 1 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+}
+
+cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB {
+ display "Configure port B pins"
+ flavor none
+ no_define
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0 {
+ display "Configure pin PB0"
+ flavor data
+ legal_values { "txd0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_txd0") ? "txd0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b0_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB0 can be configured as the UART0 tx signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1 {
+ display "Configure pin PB1"
+ flavor data
+ legal_values { "rxd0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_rxd0") ? "rxd0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b1_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB1 can be configured as the UART0 rx signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2 {
+ display "Configure pin PB2"
+ flavor data
+ legal_values { "cts0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_cts0") ? "cts0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b2_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB2 can be configured as the UART0 CTS signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3 {
+ display "Configure pin PB3"
+ flavor data
+ legal_values { "rts0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_rts0") ? "rts0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b3_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB3 can be configured as the UART0 RTS signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4 {
+ display "Configure pin PB4"
+ flavor data
+ legal_values { "clk0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_clk0") ? "clk0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b4_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB4 can be configured as the UART0 clock signal, a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5 {
+ display "Configure pin PB5"
+ flavor data
+ legal_values { "ta" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_ta") ? "ta" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b5_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB5 can be configured as the bus control transfer acknowledge
+ signal, a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6 {
+ display "Configure pin PB6"
+ flavor data
+ legal_values { "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b6_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b6_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b6_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB6 can be configured as a GPIO input, or
+ a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7 {
+ display "Configure pin PB7"
+ flavor data
+ legal_values { "tout0" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_tout0") ? "tout0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b7_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB7 can be configured as the timer output 0 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8 {
+ display "Configure pin PB8"
+ flavor data
+ legal_values { "etxd3" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_etxd3") ? "etxd3" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b8_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB8 can be configured as the ethernet TxD3 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9 {
+ display "Configure pin PB9"
+ flavor data
+ legal_values { "etxd2" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_etxd2") ? "etxd2" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b9_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB9 can be configured as the ethernet TxD2 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10 {
+ display "Configure pin PB10"
+ flavor data
+ legal_values { "etxd1" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_etxd1") ? "etxd1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b10_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB10 can be configured as the ethernet TxD1signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11 {
+ display "Configure pin PB11"
+ flavor data
+ legal_values { "erxd3" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_erxd3") ? "erxd3" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b11_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB11 can be configured as the ethernet RxD3 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12 {
+ display "Configure pin PB12"
+ flavor data
+ legal_values { "erxd2" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_erxd2") ? "erxd2" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b12_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB12 can be configured as the ethernet RxD2 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13 {
+ display "Configure pin PB13"
+ flavor data
+ legal_values { "erxd1" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_erxd1") ? "erxd1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b13_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB13 can be configured as the ethernet RxD1 signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14 {
+ display "Configure pin PB14"
+ flavor data
+ legal_values { "erxer" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_erxer") ? "erxer" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b14_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB14 can be configured as the ethernet RxER signal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15 {
+ display "Configure pin PB15"
+ flavor data
+ legal_values { "e_mdc" "in" "out0" "out1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_e_mdc") ? "e_mdc" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_in") ? "in" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_out0") ? "out0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "b15_out1") ? "out1" :
+ "invalid"
+ }
+ description "
+ Pin PB15 can be configured as the ethernet E_MDCsignal,
+ a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+}
+
+cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC {
+ display "Configure port C pins"
+ flavor none
+ no_define
+
+ for { set pin 0 } { $pin < 16 } { incr pin } {
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC[set pin] {
+ display "Configure pin PC[set pin]"
+ flavor data
+ legal_values { "in" "out0" "out1" }
+ default_value \
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, \"c[set pin]_in\") ? \"in\" : \
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, \"c[set pin]_out0\") ? \"out0\" : \
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, \"c[set pin]_out1\") ? \"out1\" : \
+ \"invalid\"
+ description "
+ Pin PC[set pin] can be configured as a GPIO input, or a GPIO output (initial value 0 or 1)."
+ }
+ }
+}
+
+cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD {
+ display "Configure port D pins"
+ flavor none
+ no_define
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0 {
+ display "Configure pin PD0"
+ flavor data
+ legal_values { "none" "dcl0" "clk1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d0_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d0_dcl0") ? "dcl0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d0_clk1") ? "clk1" :
+ "invalid"
+ }
+ description "
+ Pin PD0 can be configured as the IDL clock 0 signal, the UART1
+ clock signal, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1 {
+ display "Configure pin PD1"
+ flavor data
+ legal_values { "none" "din0" "rxd1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d1_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d1_din0") ? "din0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d1_rxd1") ? "rxd1" :
+ "invalid"
+ }
+ description "
+ Pin PD1 can be configured as the IDL input 0 signal, the UART1
+ rx signal, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2 {
+ display "Configure pin PD2"
+ flavor data
+ legal_values { "none" "cts1" "qspi_cs2" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d2_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d2_cts1") ? "cts1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d2_qspi_cs2") ? "qspi_cs2" :
+ "invalid"
+ }
+ description "
+ Pin PD2 can be configured as the UART1 CTS signal, the QSPI chip
+ select 2 signal, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3 {
+ display "Configure pin PD3"
+ flavor data
+ legal_values { "none" "rts1" "int5" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d3_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d3_rts1") ? "rts1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d3_int5") ? "int5" :
+ "invalid"
+ }
+ description "
+ Pin PD3 can be configured as the UART1 RTS signal, an external
+ interrupt input, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4 {
+ display "Configure pin PD4"
+ flavor data
+ legal_values { "none" "dout0" "txd1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d4_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d4_dout0") ? "dout0" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d4_txd1") ? "txd1" :
+ "invalid"
+ }
+ description "
+ Pin PD4 can be configured as the IDL serial data output 0 signal,
+ the UART1 TX signal, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5 {
+ display "Configure pin PD5"
+ flavor data
+ legal_values { "none" "din3" "int4" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d5_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d5_din3") ? "din3" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d5_int4") ? "int4" :
+ "invalid"
+ }
+ description "
+ Pin PD5 can be configured as the IDL input 3 signal, an
+ external interrupt input, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6 {
+ display "Configure pin PD6"
+ flavor data
+ legal_values { "none" "pwm_out1" "tout1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d6_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d6_pwm_out1") ? "pwm_out1" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d6_tout1") ? "tout1" :
+ "invalid"
+ }
+ description "
+ Pin PD6 can be configured as the PWM output 1 signal, the
+ timer 1 output signal, or left at high impedance."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7 {
+ display "Configure pin PD7"
+ flavor data
+ legal_values { "none" "pwm_out2" "tin1" }
+ default_value {
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d7_none") ? "none" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d7_pwm_out2") ? "pwm_out2" :
+ is_substr(CYGHWR_HAL_M68K_MCF5272_BOARD_PINS, "d7_tin1") ? "tin1" :
+ "invalid"
+ }
+ description "
+ Pin PD7 can be configured as the PWM output 2 signal,
+ the timer 1 input signal, or left at high impedance."
+ }
+}
Index: cdl/hal_m68k_mcf5272.cdl
===================================================================
RCS file: cdl/hal_m68k_mcf5272.cdl
diff -N cdl/hal_m68k_mcf5272.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ cdl/hal_m68k_mcf5272.cdl 20 Nov 2008 22:49:04 -0000
@@ -0,0 +1,228 @@
+# ====================================================================
+#
+# hal_m68k_mcf5272.cdl
+#
+# Processor settings for a Freescale mcf5272
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+# -------------------------------------------
+# This file is part of eCos, the Embedded Configurable Operating System.
+# Copyright (C) 2003,2004,2006,2007,2008 Free Software Foundation, Inc.
+#
+# eCos is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 or (at your option) any later version.
+#
+# eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with eCos; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+#
+# As a special exception, if other files instantiate templates or use macros
+# or inline functions from this file, or you compile this file and link it
+# with other works to produce a work based on this file, this file does not
+# by itself cause the resulting work to be covered by the GNU General Public
+# License. However the source code for this file must still be made available
+# in accordance with section (3) of the GNU General Public License.
+#
+# This exception does not invalidate any other reasons why a work based on
+# this file might be covered by the GNU General Public License.
+# -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+#######DESCRIPTIONBEGIN####
+#
+# Author(s): bartv
+# Date: 2003-06-04
+#
+#####DESCRIPTIONEND####
+#========================================================================
+
+cdl_package CYGPKG_HAL_M68K_MCF5272 {
+ display "MCF5272 ColdFire variant HAL"
+ doc ref/hal-m68k-mcf5272.html
+ parent CYGPKG_HAL_M68K_MCFxxxx
+ requires CYGPKG_HAL_M68K_MCFxxxx
+ implements CYGINT_HAL_M68K_VARIANT_CACHE
+ implements CYGINT_HAL_M68K_VARIANT_IRAM
+ hardware
+ include_dir cyg/hal
+
+ description "The mcf5272 M68k/ColdFire processor HAL package provides
+ generic support for this processor."
+
+ compile mcf5272.c
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_PROC_H <pkgconf/hal_m68k_mcf5272.h>"
+ }
+
+ cdl_component CYGPKG_HAL_M68K_MCF5272_HARDWARE {
+ display "Board-specific details"
+ flavor none
+
+ cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO {
+ display "Configure GPIO pins"
+ flavor none
+ active_if CYGHWR_HAL_M68K_MCF5272_BOARD_PINS
+ script gpio.cdl
+
+ description "
+ MCF5272 processors have 48 multi-purpose pins which can
+ be used for on-chip peripherals or for general purpose I/O.
+ Provided the platform HAL provides the appropriate information
+ the processor HAL will automatically set up each pin early on
+ during system initialization."
+ }
+
+ cdl_component CYGHWR_HAL_M68K_MCFxxxx_UART0 {
+ display "UART0 details"
+ flavor bool
+ default_value { (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0 == "txd0") || (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1 == "rxd0") }
+ description "
+ MCF5272 processors have three built-in UARTs which can be
+ used for HAL diagnostics or through the serial driver
+ CYGPKG_DEVS_SERIAL_MCFxxxx. By default support for each
+ UART is enabled if the relevant GPIO configuration options
+ are appropriate, disabled otherwise. Users can override this if
+ necessary, for example if the pins should come up in GPIO mode
+ but may be switched to UART mode later on."
+
+ cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS {
+ display "UART0 RTS connected"
+ flavor bool
+ default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3 == "rts0" }
+ implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+ description "
+ This option enables support elsewhere in the system
+ when the UART0 RTS signal is connected to a processor pin."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_CTS {
+ display "UART0 CTS connected"
+ flavor bool
+ default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2 == "cts0" }
+ implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+ description "
+ This option enables support elsewhere in the system
+ when the UART0 CTS signal is connected to a processor pin."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS {
+ display "UART0 RS485 support"
+ flavor bool
+ default_value 0
+ active_if CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS
+ requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "uart0" }
+ description "
+ If the UART0 signals are connected to an RS485 transceiver instead of
+ an RS232 transceiver and the UART0 RTS line activates that transceiver
+ then this option can be enabled. It primarily affects h/w flow control
+ and transmit code within the generic mcfxxxx serial driver."
+ }
+ }
+
+ cdl_component CYGHWR_HAL_M68K_MCFxxxx_UART1 {
+ display "UART1 details"
+ flavor bool
+ default_value { (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4 == "txd1") || (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1 == "rxd1") }
+ description "
+ MCF5272 processors have two built-in UARTs which can be
+ used for HAL diagnostics or through the serial driver
+ CYGPKG_DEVS_SERIAL_MCFxxxx. By default support for each
+ UART is enabled if the relevant GPIO configuration options
+ are appropriate, disabled otherwise. Users can override this if
+ necessary, for example if the pins should come up in GPIO mode
+ but may be switched to UART mode later on."
+
+ cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS {
+ display "UART1 RTS connected"
+ flavor bool
+ default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3 == "rts1" }
+ implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+ description "
+ This option enables support elsewhere in the system
+ when the UART1 RTS signal is connected to a processor pin."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_CTS {
+ display "UART1 CTS connected"
+ flavor bool
+ default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2 == "cts1" }
+ implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+ description "
+ This option enables support elsewhere in the system
+ when the UART1 CTS signal is connected to a processor pin."
+ }
+
+ cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_RS485_RTS {
+ display "UART1 RS485 support"
+ flavor bool
+ default_value 0
+ active_if CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS
+ requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "uart1" }
+ description "
+ If the UART1 signals are connected to an RS485 transceiver instead of
+ an RS232 transceiver and the UART1 RTS line activates that transceiver
+ then this option can be enabled. This primarily affects h/w flow control
+ and transmit code within the generic mcfxxxx serial driver."
+ }
+ }
+ }
+
+ cdl_option CYGIMP_HAL_M68K_MCF5272_IDLE {
+ display "Idle thread behaviour"
+ flavor data
+ legal_values { "run" "sleep" "stop" }
+ default_value { is_loaded(CYGPKG_CPULOAD) ? "run" : "sleep" }
+ description "
+ The processor can automatically enter a low power mode whenever
+ the system is idle. In run mode the cpu just spins. In sleep mode
+ the cpu clock is disabled but peripherals continue running, and any
+ interrupt will wake up the cpu. In stop mode the on-chip peripherals
+ are shut down as well and an external interrupt is required. The
+ MCF5272 provides finer-grained control over power management via
+ the PMR power management register but the processor HAL leaves
+ this to the application."
+ }
+
+ cdl_option CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER {
+ display "Support profiling"
+ active_if CYGPKG_PROFILE_GPROF
+ default_value 1
+ implements CYGINT_PROFILE_HAL_TIMER
+ compile mcf5272_profile.S
+
+ description "
+ The MCF5272 processor HAL can provide support for gprof-based
+ profiling. This uses timer TMR2 to generate regular interrupts,
+ and the interrupt handler records the PC at the time of the
+ interrupt."
+ }
+
+ cdl_option CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN {
+ display "Lowest permitted interrupt priority"
+ flavor data
+ calculated 1
+ description "
+ In the MCF5272 processor HAL interrupt priorities are mapped
+ directly onto M68K IPL levels, so valid priorities are in the
+ range 1 to 7. However IPL level 7 is non-maskable so should not
+ be used by typical eCos code."
+ }
+
+ cdl_option CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX {
+ display "Lowest permitted interrupt priority"
+ flavor data
+ calculated 6
+ description "
+ In the MCF5272 processor HAL interrupt priorities are mapped
+ directly onto M68K IPL levels, so valid priorities are in the
+ range 1 to 7. However IPL level 7 is non-maskable so should not
+ be used by typical eCos code."
+ }
+}
Index: cdl/hal_m68k_mcf52xx_mcf5272.cdl
===================================================================
RCS file: cdl/hal_m68k_mcf52xx_mcf5272.cdl
diff -N cdl/hal_m68k_mcf52xx_mcf5272.cdl
--- cdl/hal_m68k_mcf52xx_mcf5272.cdl 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,62 +0,0 @@
-# ====================================================================
-#
-# hal_m68k_m68000.cdl
-#
-# M68K/M68000 variant architectural HAL package configuration data
-#
-# ====================================================================
-#####ECOSGPLCOPYRIGHTBEGIN####
-## -------------------------------------------
-## This file is part of eCos, the Embedded Configurable Operating System.
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-##
-## eCos is free software; you can redistribute it and/or modify it under
-## the terms of the GNU General Public License as published by the Free
-## Software Foundation; either version 2 or (at your option) any later version.
-##
-## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-## WARRANTY; without even the implied warranty of MERCHANTABILITY or
-## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-## for more details.
-##
-## You should have received a copy of the GNU General Public License along
-## with eCos; if not, write to the Free Software Foundation, Inc.,
-## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-##
-## As a special exception, if other files instantiate templates or use macros
-## or inline functions from this file, or you compile this file and link it
-## with other works to produce a work based on this file, this file does not
-## by itself cause the resulting work to be covered by the GNU General Public
-## License. However the source code for this file must still be made available
-## in accordance with section (3) of the GNU General Public License.
-##
-## This exception does not invalidate any other reasons why a work based on
-## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
-## -------------------------------------------
-#####ECOSGPLCOPYRIGHTEND####
-# ====================================================================
-
-cdl_package CYGPKG_HAL_M68K_MCF52xx_MCF5272 {
- display "mcf5272 68k/Coldfire variant HAL"
- parent CYGPKG_HAL_M68K_MCF52xx
- requires CYGPKG_HAL_M68K_MCF52xx
- implements CYGINT_HAL_M68K_VARIANT
- hardware
- include_dir cyg/hal
- define_header hal_m68k_mcf52xx_mcf5272.h
-
- description "The mcf5272 68k/Coldfire variant HAL package provides
- generic support for this processor architecture. It is also
- necessary to select a specific target platform HAL package."
-
- define_proc {
- puts $::cdl_header "#include <pkgconf/hal_m68k_mcf52xx.h>"
- }
-
- compile proc_startup.c proc_arch.S proc_misc.c memcpy.c
-
-}
-
Index: doc/mcf5272.sgml
===================================================================
RCS file: doc/mcf5272.sgml
diff -N doc/mcf5272.sgml
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ doc/mcf5272.sgml 20 Nov 2008 22:49:04 -0000
@@ -0,0 +1,227 @@
+<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" -->
+
+<!-- {{{ Banner -->
+
+<!-- =============================================================== -->
+<!-- -->
+<!-- mcf5272.sgml -->
+<!-- -->
+<!-- mcf5272 processor HAL documentation. -->
+<!-- -->
+<!-- =============================================================== -->
+<!-- ####COPYRIGHTBEGIN#### -->
+<!-- -->
+<!-- Copyright (C) 2003,2008 -->
+<!-- Free Software Foundation, Inc. -->
+<!-- This material may be distributed only subject to the terms -->
+<!-- and conditions set forth in the Open Publication License, v1.0 -->
+<!-- or later (the latest version is presently available at -->
+<!-- http://www.opencontent.org/openpub/) -->
+<!-- Distribution of the work or derivative of the work in any -->
+<!-- standard (paper) book form is prohibited unless prior -->
+<!-- permission obtained from the copyright holder -->
+<!-- -->
+<!-- ####COPYRIGHTEND#### -->
+<!-- =============================================================== -->
+<!-- #####DESCRIPTIONBEGIN#### -->
+<!-- -->
+<!-- Author(s): bartv -->
+<!-- Contact(s): bartv -->
+<!-- Date: 2003/07/15 -->
+<!-- Version: 0.01 -->
+<!-- -->
+<!-- ####DESCRIPTIONEND#### -->
+<!-- =============================================================== -->
+
+<!-- }}} -->
+
+<part id="hal-m68k-mcf5272"><title>Freescale MCF5272 Processor Support</title>
+
+<refentry id="m68k-mcf5272">
+ <refmeta>
+ <refentrytitle>The MCF5272 ColdFire Processor</refentrytitle>
+ </refmeta>
+ <refnamediv>
+ <refname><varname>CYGPKG_HAL_M68K_MCF5272</varname></refname>
+ <refpurpose>eCos Support for the Freescale MCF5272 Processor</refpurpose>
+ </refnamediv>
+
+ <refsect1 id="m68k-mcf5272-description"><title>Description</title>
+ <para>
+The MCF5272 is one member of the Freescale MCFxxxx ColdFire range of
+processors. It comes with a number of on-chip peripherals including 2
+UARTs, ethernet, and USB slave. The processor HAL package
+<varname>CYGPKG_HAL_M68K_MCF5272</varname> provides support for
+features that are specific to the MCF5272. It complements the M68K
+architectural HAL package <varname>CYGPKG_HAL_M68K</varname> and the
+variant HAL package <varname>CYGPKG_HAL_M68K_MCFxxxx</varname>. An
+eCos configuration should also include a platform HAL package, for
+example <varname>CYGPKG_HAL_M68K_M5272C3</varname> to support
+board-level details like the external memory chips.
+ </para>
+ </refsect1>
+
+ <refsect1 id="m68k-mcf5272-config"><title>Configuration</title>
+ <para>
+The MCF5272 processor HAL package should be loaded automatically when
+eCos is configured for appropriate target hardware. It should never be
+necessary to load this package explicitly. Unloading the package
+should only happen as a side effect of switching target hardware.
+ </para>
+ <para>
+The component <varname>CYGPKG_HAL_M68K_MCF5272_HARDWARE</varname>
+contains configuration options for the available hardware. This
+includes all GPIO pin settings, with defaults provided by the
+platform HAL. In turn the pin settings are used to determine defaults
+for other hardware settings, for example which of the two on-chip
+uarts are usable. Users can override these settings if necessary,
+subject to any constraints imposed by the platform HAL, but care has
+to be taken that the resulting configuration still matches the actual
+hardware.
+ </para>
+ <para>
+The option <varname>CYGIMP_HAL_M68K_MCF5272_IDLE</varname> controls
+what happens in configurations containing the eCos kernel when the
+idle thread runs, i.e. when there is nothing for the processor to do
+until the next interrupt comes in. Usually the processor made to
+sleep, halting the cpu but leaving all peripherals active.
+ </para>
+ <para>
+The package contains a single configuration option
+<varname>CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER</varname>. This
+controls the support for gprof-based profiling. By default it is
+active and enabled if the configuration contains the gprof profiling
+package, otherwise inactive. The relevant code uses hardware timer 2,
+so that timer is no longer available for application code. If the
+timer is required but a platform HAL provides an alternative
+implementation of the profiling support then this option can be
+disabled.
+ </para>
+ </refsect1>
+
+ <refsect1 id="m68k-mcf5272-port"><title>The HAL Port</title>
+ <para>
+This section describes how the MCF5272 processor HAL package
+implements parts of the eCos HAL specification. It should be read in
+conjunction with similar sections from the architectural and variant
+HAL documentation.
+ </para>
+
+ <refsect2 id="m68k-mcf5272-port-io"><title>HAL I/O</title>
+ <para>
+The header
+file <filename class="headerfile">cyg/hal/proc_io.h</filename>
+specifies which generic MCFxxxx devices are present, and provides
+details of MCF5272-specific devices. This header file is automatically
+included by the architectural
+header <filename class="headerfile">cyg/hal/hal_io.h</filename>, so
+typically application code and other packages will just include the
+latter.
+ </para>
+ <para>
+It should be noted that the Freescale documentation is occasionally
+confusing when it comes to numbering devices. For example the four
+on-chip timers are numbered TMR0 to TMR3, but in the interrupt
+controller the corresponding interrupts are numbered TMR1 to TMR4. The
+eCos port consistently starts numbering at 0, so these interrupts have
+been renamed TMR0 to TMR3.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-interrupts"><title>Interrupt Handling</title>
+ <para>
+The header file <filename
+class="headerfile">cyg/hal/proc_intr.h</filename> provides VSR and ISR
+vector numbers for all interrupt sources. The VSR vector number, for
+example <varname>CYGNUM_HAL_VECTOR_TMR0</varname>, should be used
+for calls like <function>cyg_interrupt_get_vsr</function>. It
+corresponds directly to the M68K exception number. The ISR vector
+number, for example <varname>CYGNUM_HAL_ISR_TMR0</varname>, should be
+used for calls like <function>cyg_interrupt_create</function>. This
+header file is automatically included by the architectural header
+<filename class="headerfile">cyg/hal/hal_intr.h</filename>, and other
+packages and application code will normally just include the latter.
+ </para>
+ <para>
+The eCos HAL macros <function>HAL_INTERRUPT_MASK</function>,
+<function>HAL_INTERRUPT_UNMASK</function>,
+<function>HAL_INTERRUPT_SET_LEVEL</function>,
+<function>HAL_INTERRUPT_ACKNOWLEDGE</function>, and
+<function>HAL_INTERRUPT_CONFIGURE</function> are implemented by the
+processor HAL. The mask and unmask operations are straightforward,
+simply manipulating the on-chip interrupt controller. The acknowledge
+and configure macros are only relevant for external interrupts:
+internal interrupts generated by on-chip devices do not need to be
+acknowledged. The set-level operation, used implicitly by higher level
+code such as <function>cyg_interrupt_create</function>, is mapped on
+to M68K IPL levels so interrupts can be given a priority between 1
+and 7. Priority 7 corresponds to non-maskable interrupts and must be
+used with care: such interrupts cannot be managed safely by the usual
+eCos ISR and DSR mechanisms; instead application code will have to
+install a custom VSR and manage the entire interrupt.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-clock"><title>Clock Support</title>
+ <para>
+The processor HAL provides support for the eCos system clock. This
+always uses hardware timer 3, which should not be used directly by
+application code. If gprof-based profiling is in use then that will
+use hardware timer 2. Timers 0 and 1 are never used by eCos so
+application code is free to manipulate these as required.
+ </para>
+ <para>
+Some of the configuration options related to the system clock, for
+example <varname>CYGNUM_HAL_RTC_PERIOD</varname>, are actually
+contained in the platform HAL rather than the processor HAL. These
+options need to take into account the processor clock speed, a
+characteristic of the platform rather than the processor.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-cache"><title>Cache Handling</title>
+ <para>
+The MCF5272 has a small instruction cache of 1024 bytes. This is fully
+supported by the processor HAL. There is no data cache.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-idle"><title>Idle Thread Support</title>
+ <para>
+The configuration
+option <varname>CYGIMP_HAL_M68K_MCF5272_IDLE</varname> controls what
+happens when the kernel idle thread runs. The default behaviour is to
+put the processor to sleep until the next interrupt.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-profiling"><title>Profiling Support</title>
+ <para>
+The MCF5272 processor HAL provides a profiling timer for use with the
+gprof profiling package. This uses hardware timer 2, so application
+code should not manipulate this timer if profiling is enabled. The
+M68K architectural HAL implements the <function>mcount</function>
+function so profiling is fully supported on all MCF5272-based platforms.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-other-hal"><title>Other Issues</title>
+ <para>
+The MCF5272 processor HAL does not affect the implementation of data
+types, stack size definitions, linker scripts, SMP support, system
+startup, or debug support. The architectural HAL's bit index
+instructions are used rather than the MCFxxxx variant HAL's versions
+since the MCF5272 does not implement the ff1 and bitrev instructions.
+ </para>
+ </refsect2>
+
+ <refsect2 id="m68k-mcf5272-port-other"><title>Other Functionality</title>
+ <para>
+The MCF5272 processor HAL only implements functionality defined in the
+eCos HAL specification and does not export any additional functions.
+ </para>
+ </refsect2>
+ </refsect1>
+</refentry>
+
+</part>
Index: include/mcf5272_sim.h
===================================================================
RCS file: include/mcf5272_sim.h
diff -N include/mcf5272_sim.h
--- include/mcf5272_sim.h 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,568 +0,0 @@
-#ifndef MCF5272_SIM_H
-#define MCF5272_SIM_H
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-
-/*
-
- Defines for the mcf5272 System Integration Module (SIM)
-
-*/
-
-#include <pkgconf/hal.h>
-#include <cyg/infra/cyg_type.h>
-
-/* General configuration registers. */
-typedef struct mcf5272_sim_cfg_t
-{
-
- u32_t mbar; /* Module base address register */
- /* (MBAR), after initialization */
-
- u16_t scr; /* System configuration register */
-
- u16_t spr; /* System protection register */
-
- u32_t pmr; /* Power management register */
-
- u16_t res1;
-
- u16_t alpr; /* Active low power register */
-
- u32_t dir; /* Device identification register */
-
- u32_t res2[3];
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t;
-
-/* Interrupt controller registers. */
-typedef struct mcf5272_sim_int_t
-{
-
- u32_t icr[4]; /* Interrupt control register 1-4 */
-
- u32_t isr; /* Interrupt source register */
-
- u32_t pitr; /* Programmable interrupt */
- /* transition register */
-
- u32_t piwr; /* Programmable interrupt wakeup */
- /* register */
-
- u8_t res1[3];
-
- u8_t ipvr; /* Programmable interrupt vector */
- /* register */
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t;
-
-/* Chip Select Module */
-typedef struct mcf5272_sim_cs_t
-{
-
- u32_t csbr; /* CS base register. */
-
- u32_t csor; /* CS option register. */
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t;
-
-/* General Purpose I/O Module */
-typedef struct mcf5272_sim_gpio_t
-{
-
- /* Use the following labels to initialize the bits in the data */
- /* direction registers. Setting the bit to zero indicates that this */
- /* pin is an input, one indicates an input. */
-
-#define MCF5272_GPIO_DDR_IN (0)
-#define MCF5272_GPIO_DDR_OUT (1)
-
- u32_t pacnt; /* Port A control register. */
-
- u16_t paddr; /* Port A data direction */
- /* register. */
-
- u16_t padat; /* Port A data register. */
-
- u32_t pbcnt; /* Port B control register. */
-
- /* Set these bits in the port B control register to enable the */
- /* Ethernet, UART0, and data transfer acknowledge pins. */
-
-#define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000)
-#define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000)
-#define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000)
-
-#define MCF5272_GPIO_PBCNT_TA_EN (0x00000400)
-#define MCF5272_GPIO_PBCNT_TA_DE (0x00000000)
-#define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00)
-
-#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155)
-#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000)
-#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF)
-
- u16_t pbddr; /* Port B data direction */
- /* register. */
-
- u16_t pbdat; /* Port B data register. */
-
- u32_t res1;
-
- u16_t pcddr; /* Port C data direction */
- /* register. */
-
- u16_t pcdat; /* Port C data register. */
-
- u32_t pdcnt; /* Port D control register. */
-
- /* Set these bits in the port D control register to enable the UART1 */
- /* and interrupt 4 pins. */
-
-#define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00)
-#define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000)
-#define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00)
-
-#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA)
-#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000)
-#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF)
-
- u16_t res2;
- u16_t res3;
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t;
-
-/* UART Module */
-typedef struct mcf5272_sim_uart_t
-{
-
- u8_t umr; /* UART mode register. */
- u8_t res1[3];
-
-#define MCF5272_UART_UMR_8BNP (0x13) /* Write this value to umr1 to */
- /* program the device for 8 bits */
- /* and no parity. */
-
-#define MCF5272_UART_UMR_1S (0x07) /* Write this value to umr2 to */
- /* program the device for 1 stop */
- /* bit. */
-
- u8_t usr_ucsr; /* UART status register (R) and */
- u8_t res2[3]; /* UART clock-select register (W). */
-
-#define MCF5272_UART_USR_RRDY (1<<0) /* Bit 0 of the device status */
- /* register is set when the receive */
- /* data register contains data. If */
- /* the data is not removed from the */
- /* holding register, additional */
- /* data will be placed in the FIFO */
- /* until the FIFO is overrun. */
-
-#define MCF5272_UART_USR_FFUL (1<<1) /* Bit 1 of the device status */
- /* register is set when the receive */
- /* data FIFO is full. If a */
- /* character is not removed before */
- /* the next character is received, */
- /* overrun will occur. */
-
-#define MCF5272_UART_USR_TXRDY (1<<2) /* Bit 2 of the device status */
- /* register is set when the */
- /* transmit data holding register */
- /* is empty. Note that this is */
- /* different than the FIFO being */
- /* empty as the FIFO may still */
- /* contain characters even if the */
- /* holding register is empty. */
-
-#define MCF5272_UART_USR_TXEMP (1<<3) /* Bit 3 of the device status */
- /* register is set when the */
- /* transmit data FIFO is empty. */
-
-#define MCF5272_UART_USR_OE (1<<4) /* Bit 4 of the device status */
- /* register is set when an overrun */
- /* error has occurred. */
-
-#define MCF5272_UART_USR_PE (1<<5) /* Bit 5 of the device status */
- /* register is set when a parity */
- /* error has occurred. */
-
-#define MCF5272_UART_USR_FE (1<<6) /* Bit 6 of the device status */
- /* register is set when a framing */
- /* error has occurred. */
-
-#define MCF5272_UART_USR_RB (1<<7) /* Bit 7 of the device status */
- /* register is set when a change in */
- /* break status has occurred on the */
- /* port. */
-
-#define MCF5272_UART_UCSR_CLKIN (0xDD) /* Writing this value to the ucsr */
- /* selects CLKIN/16 as the UART's */
- /* clock source. */
-
- u8_t ucr; /* UART command register (W). */
- u8_t res3[3];
-
-#define MCF5272_UART_UCR_RMR (0x01<<4) /* Write this value to ucr to */
- /* reset the mode register to umr1. */
-
-#define MCF5272_UART_UCR_RRX (0x02<<4) /* Write this value to ucr to */
- /* reset the receiver. */
-
-#define MCF5272_UART_UCR_RTX (0x03<<4) /* Write this value to ucr to */
- /* reset the transmitter. */
-
-#define MCF5272_UART_UCR_RES (0x04<<4) /* Write this value to ucr to */
- /* reset the error status. */
-
-#define MCF5272_UART_UCR_RBC (0x05<<4) /* Write this value to ucr to */
- /* reset the break change */
- /* interrupt. */
-
-#define MCF5272_UART_UCR_TXEN (1<<2) /* Write this value to ucr to */
- /* enable the transmitter. */
-
-#define MCF5272_UART_UCR_TXDE (1<<3) /* Write this value to ucr to */
- /* disable the transmitter. */
-
-#define MCF5272_UART_UCR_RXEN (1<<0) /* Write this value to ucr to */
- /* enable the receiver. */
-
-#define MCF5272_UART_UCR_RXDE (1<<1) /* Write this value to ucr to */
- /* disable the receiver. */
-
- /* Write this value to the ucr to */
- /* enablt the transmitter and */
- /* receiver. */
-
-#define MCF5272_UART_UCR_TXRXEN \
- (MCF5272_UART_UCR_TXEN | \
- MCF5272_UART_UCR_RXEN)
-
- u8_t urb_utb; /* UART receiver buffers (R) and */
- u8_t res4[3]; /* UART transmitter buffers (W). */
-
- u8_t uipcr_uacr; /* UART input port change */
- u8_t res5[3]; /* register (R) and UART auxiliary */
- /* control register (W). */
-
- u8_t uisr_uimr; /* UART interrupt status register */
- u8_t res6[3]; /* (R) and UART interrupt mask */
- /* register (W). */
-
- u8_t udu; /* UART divider upper register */
- u8_t res7[3]; /* (W). */
-
- u8_t udl; /* UART divider lower register */
- u8_t res8[3]; /* (W). */
-
- u8_t uabu; /* UART autobaud register MSB */
- u8_t res9[3]; /* (R). */
-
- u8_t uabl; /* UART autobaud register LSB */
- u8_t res10[3]; /* (R). */
-
- u8_t utf; /* UART transmitter FIFO */
- u8_t res11[3]; /* register. */
-
-#define MCF5272_UART_UTF_TXB (0x1F) /* Transmitter buffer data level. */
- /* Indicates the number of bytes */
- /* (0-24) currently stored in the */
- /* transmitter FIFO. */
-
- u8_t urf; /* UART receiver FIFO register. */
- u8_t res12[3];
-
- u8_t ufpd; /* UART Fractional Precision */
- u8_t res13[3]; /* Divider Control register. */
-
- u8_t uip; /* UART input port register (CTS) */
- u8_t res14[3]; /* (R). */
-
- u8_t uop1; /* UART output port bit set */
- u8_t res15[3]; /* command register (RTS) (W). */
-
- u8_t uop0; /* UART output port bit reset */
- u8_t res16[3]; /* command register (RTS) (W). */
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_uart_t;
-
-/* Timer Module */
-typedef struct mcf5272_sim_timer_t
-{
-
- u16_t tmr; /* Timer Mode Register */
- u16_t res1;
-
-#define MCF5272_TIMER_TMR_PS 0xFF00 /* Prescaler. Programmed to */
-#define MCF5272_TIMER_TMR_PS_BIT 8 /* divide the clock input by values */
- /* from 1 to 256. The value */
- /* 0000_0000 divides the clock by */
- /* 1; the value 1111_1111 divides */
- /* the clock by 256. */
-
-#define MCF5272_TIMER_TMR_CE 0x00C0 /* Capture edge and enable */
-#define MCF5272_TIMER_TMR_CE_BIT 6 /* interrupt. 00 Disable capture */
- /* and interrupt on capture event */
- /* 01 Capture on rising edge only */
- /* and generate interrupt on */
- /* capture event 10 Capture on */
- /* falling edge only and generate */
- /* interrupt on capture event 11 */
- /* Capture on any edge and generate */
- /* interrupt on capture event. */
-
-#define MCF5272_TIMER_TMR_OM 0x0020 /* Output mode (TMR0 and TMR1 */
-#define MCF5272_TIMER_TMR_OM_BIT 5 /* only. Reserved in TMR2 and */
- /* TMR3). 0 Active-low pulse for */
- /* one system clock cycle (15 nS at */
- /* 66 MHz). 1 Toggle output; TOUTn */
- /* is high at reset but is */
- /* unavailable externally until the */
- /* appropriate port control */
- /* register is configured for this */
- /* function. */
-
-#define MCF5272_TIMER_TMR_ORI 0x0010 /* Output reference interrupt */
-#define MCF5272_TIMER_TMR_ORI_BIT 4 /* enable. 0 Disable interrupt for */
- /* reference reached (does not */
- /* affect interrupt on capture */
- /* function). 1 Enable interrupt */
- /* upon reaching the reference */
- /* value. If ORI is 1 when the */
- /* TER[REF] is set, an immediate */
- /* interrupt occurs. */
-
-#define MCF5272_TIMER_TMR_FRR 0x0008 /* Free run/restart. 0 Free run. */
-#define MCF5272_TIMER_TMR_FRR_BIT 3 /* Timer count continues to */
- /* increment after the reference */
- /* value is reached. 1 Restart. */
- /* Timer count is reset immediately */
- /* after the reference value is */
- /* reached. */
-
-#define MCF5272_TIMER_TMR_CLK 0x0006 /* Input clock source for the */
-#define MCF5272_TIMER_TMR_CLK_BIT 1 /* timer. 00 Stop count. 01 */
- /* Master system clock. 10 Master */
- /* system clock divided by 16. */
- /* TIN0 and TIN1 are external to */
- /* the MCF5272 and are not */
- /* synchronized to the system */
- /* clock, so successive timeout */
- /* lengths may vary slightly. 11 */
- /* Corresponding TIN pin, TIN0 or */
- /* TIN1 (falling edge), unused in */
- /* TMR2 and TMR3. The minimum high */
- /* and low periods for TIN as the */
- /* clock source is 1 system clock, */
- /* which gives a maximum TIN */
- /* frequency of clock/2. */
-
-#define MCF5272_TIMER_TMR_RST 0x0001 /* Reset timer. 0 A transition */
-#define MCF5272_TIMER_TMR_RST_BIT 0 /* from 1 to 0 resets the timer. */
- /* Other register values can be */
- /* written. The */
- /* counter/timer/prescaler are not */
- /* clocked unless the timer is */
- /* enabled. 1 Enable timer. */
-
- u16_t trr; /* Timer Reference Register */
- u16_t res2;
-
- u16_t tcap; /* Timer Capture Register */
- u16_t res3;
-
- u16_t tcn; /* Timer Counter */
- u16_t res4;
-
- u16_t ter; /* Timer Event Register */
- u16_t res5;
-
-#define MCF5272_TIMER_TER_REF (0x0002) /* Output reference event. If */
-#define MCF5272_TIMER_TER_REF_BIT (1) /* the bit is 0, the counter has */
- /* not reached the TRR value; */
- /* otherwise, the counter has */
- /* reached the TRR value. Writing */
- /* a 1 clears this bit. */
-
-#define MCF5272_TIMER_TER_CAP (0x0001) /* Captuer event. If this bit is */
-#define MCF5272_TIMER_TER_CAP_BIT (0) /* 0, the counter value has not */
- /* been latched into the TCR; */
- /* otherwise, the counter value is */
- /* latched into the TCR. Writing a */
- /* 1 clears this bit. */
-
- u32_t res6[3];
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_timer_t;
-
-/* Watchdog timer */
-typedef struct mcf5272_sim_wdtmr_t
-{
-
- u16_t wrrr; /* Watchdog reset reference */
- u16_t res1; /* register. */
-
- u16_t wirr; /* Watchdog interrupt reference */
- u16_t res2; /* register. */
-
- u16_t wcr; /* Watchdog counter register. */
- u16_t res3;
-
- u16_t wer; /* Watchdog event register. */
- u16_t res4;
-
- u32_t res5[28];
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t;
-
-/* Ethernet Module */
-typedef struct mcf5272_sim_enet_t
-{
-
- u8_t res1[0x40];
-
- u32_t ecr; /* Ethernet control register */
-
- u32_t eir; /* Interrupt event register */
-
- u32_t eimr; /* Interrupt mask register */
-
- u32_t ivsr; /* Interrupt vector status */
- /* register */
-
- u32_t rdar; /* Receive descriptor active */
- /* register */
-
- u32_t tdar; /* Transmit descriptor active */
- /* register */
-
- u8_t res2[0x0880-0x0858];
-
- u32_t mmfr; /* MII management frame register */
-
- u32_t mscr; /* MII speed control register */
-
- u8_t res3[0x08cc-0x0888];
-
- u32_t frbr; /* FIFO receive bound register */
-
- u32_t frsr; /* FIFO receive start register */
-
- u8_t res4[0x08e4-0x08d4];
-
- u32_t tfwr; /* Transmit FIFO watermark */
-
- u8_t res5[0x08ec-0x08e8];
-
- u32_t tfsr; /* Transmit FIFO start register */
-
- u8_t res6[0x0944-0x08f0];
-
- u32_t rcr; /* Receive control register */
-
- u32_t mflr; /* Maximum frame length register */
-
- u8_t res7[0x0984-0x094c];
-
- u32_t tcr; /* Transmit control register */
-
- u8_t res8[0x0c00-0x0988];
-
- u32_t malr; /* Lower 32-bits of MAC address */
-
- u32_t maur; /* Upper 16-bits of MAC address */
-
- u32_t htur; /* Upper 32-bits of hash table */
-
- u32_t htlr; /* Lower 32-bits of hash table */
-
- u32_t erdsr; /* Pointer to receive descriptor */
- /* ring */
-
- u32_t etdsr; /* Pointer to transmit descriptor */
- /* ring */
-
- u32_t emrbr; /* Maximum receive buffer size */
-
- u8_t res9[0x0c40-0x0c1c];
-
- u8_t efifo[448]; /* FIFO RAM space */
-
- u8_t res10[0x1000-0x0e00];
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_enet_t;
-
-/* System Integration Module (SIM) This structure defines each */
-/* register's offset from the current value of the mbar register. */
-typedef struct mcf5272_sim_t
-{
-
- mcf5272_sim_cfg_t cfg; /* 0x0000: General configuration */
- /* registers. */
-
- mcf5272_sim_int_t intc; /* 0x0020: Interrupt controller */
- /* registers. */
-
- mcf5272_sim_cs_t cs[8]; /* 0x0040: Chip Select Module */
-
- mcf5272_sim_gpio_t gpio; /* 0x0080: General purpose I/O */
- /* control registers */
-
- u32_t qspi[8]; /* 0x00a0: Queued serial */
- /* peripheral interface module. */
-
- u32_t pwm[8]; /* 0x00c0: Pulse Width Modulation */
- /* (PWM) Module */
-
- u32_t dmac[8]; /* 0x00e0: DMA Controller */
-
- mcf5272_sim_uart_t uart[2]; /* 0x0100: UART Modules */
-
- u32_t sdramc[32]; /* 0x0180: SDRAM Controller */
-
- mcf5272_sim_timer_t timer[4]; /* 0x0200: Timer Module */
-
- mcf5272_sim_wdtmr_t wdtimer; /* 0x0280: Watchdog Timer Module */
-
- u32_t plic[320]; /* 0x0300: Physical Layer */
- /* Interface Controller */
-
- mcf5272_sim_enet_t enet; /* 0x0800: Ethernet Module */
-
- u32_t usb[512]; /* 0x1000: Universal Serial Bus */
-
-} __attribute__ ((aligned (4), packed)) mcf5272_sim_t;
-
-#endif /* MCF5272_SIM_H */
-
Index: include/proc.inc
===================================================================
RCS file: include/proc.inc
diff -N include/proc.inc
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ include/proc.inc 20 Nov 2008 22:49:06 -0000
@@ -0,0 +1,250 @@
+##=============================================================================
+##
+## proc.inc
+##
+## mcf5272 processor
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2003,2004,2006,2008 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): bartv
+## Date: 2003-06-04
+######DESCRIPTIONEND####
+##=============================================================================
+
+#include <pkgconf/hal_m68k_mcf5272.h>
+
+// Vectors support.
+// The 5272's interrupt vectors go up to slot 96: the standard 64 plus another
+// 32 for the on-chip peripherals.
+#define HAL_M68K_VSR_COUNT 96
+
+// The chip has 4K on-chip RAM so enable the relevant init code in vectors.S
+#define _HAL_M68K_INITIALIZE_IRAM_ 1
+
+// Fixed vectors data. The cacr cache control register is write-only so
+// a shadow copy is needed. This has to be shared between RedBoot and the
+// application, otherwise confusing things can happen when both manipulate
+// the cache e.g. during debugging. Shadow copies are also needed to
+// implement interrupt priorities. Some space is allocated for future
+// expansion.
+ .macro _hal_mcf5272_ram_vectors_
+ .global hal_mcf5272_cacr
+hal_mcf5272_cacr:
+ .long 0
+ .global hal_mcf5272_icr_pri_mirror
+hal_mcf5272_icr_pri_mirror:
+ .long 0, 0, 0, 0
+ .rept 11
+ .long 0
+ .endr
+ .endm
+
+#define _HAL_M68K_PROCESSOR_RAM_VECTORS_ _hal_mcf5272_ram_vectors_
+
+// ----------------------------------------------------------------------------
+// Utility macros for initialization. It is assumed that the platform HAL
+// has provided the magic numbers.
+
+// Remap. Typically on an MCF5272 board flash memory starts of at location
+// 0, everything else is still disabled. The flash needs to be moved to
+// its final location, usually in high memory, while we are still running
+// out of flash. The way to do this is to set the mask in the cs option
+// register to 0, causing the flash to be mirrored throughout the address
+// space, then branch to the actual flash location, and then the rest of
+// the memory map can be sorted out. To access CSOR0, first we need to map
+// the MBAR into memory. MBAR has priority over chip selects so it will
+// remain visible even if the flash is mirrored.
+
+ .macro _hal_mcf5272_remap_flash_
+ move.l # _HAL_MCF5272_MBAR_VALUE_, %d0
+ movec.l %d0, %mbar
+ move.l # HAL_MCFxxxx_MBAR, %a5
+ move.l # (_HAL_MCF5272_CSOR0_VALUE_ & ~HAL_MCF5272_CSOR_BA_MASK), %d0
+ move.l %d0, HAL_MCF5272_CSOR0 (%a5)
+
+ // dBUG inserts a nop here and another in the branch location.
+ // Presumably this avoids pipeline problems if the memory map
+ // changes under the pipeline's feet.
+ nop
+
+ // Now we can branch to the real location in the flash. The linker
+ // script is set up so that this code is mapped to the right place.
+ jmp _hal_mcf5272_flash_
+
+ // Put the next code in a separate section to stop the assembler turning
+ // the above jump into a PC-relative one
+ .section ".m68k_start.0", "ax"
+
+_hal_mcf5272_flash_:
+ // Another nop as per dBUG
+ nop
+ // We are now running out of flash. CSOR0 and MBAR have been changed,
+ // everything else is still at reset values.
+ .endm
+
+// Initialize all the system registers. Typically this is done unconditionally
+// on the off-chance that RedBoot and the application need different values.
+ .macro _hal_mcf5272_init_sysregs_
+ move.l # (HAL_MCFxxxx_CACR_CINV), %d0
+ movec.l %d0, %cacr
+ move.l # (CYGNUM_HAL_M68K_MCF5272_ACR0), %d0
+ movec.l %d0, %acr0
+ move.l # (CYGNUM_HAL_M68K_MCF5272_ACR1), %d0
+ movec.l %d0, %acr1
+ move.l # (CYGNUM_HAL_M68K_MCF5272_ROMBAR), %d0
+ movec.l %d0, %rombar
+ move.l # (CYGNUM_HAL_M68K_MCF5272_RAMBAR), %d0
+ movec.l %d0, %rambar0
+ move.l # (CYGNUM_HAL_M68K_MCF5272_CACR), %d0
+ movec.l %d0, %cacr
+ .endm
+
+// Initialize memory, including starting the SDRAM controller
+ .macro _hal_mcf5272_init_memory_
+ move.w # CYGNUM_HAL_M68K_MCF5272_SCR, %d0
+ move.w %d0, HAL_MCF5272_SCR (%a5)
+ move.w # 0xFFFF, %d0
+ move.w %d0, HAL_MCF5272_SPR (%a5)
+
+ // chip selects and SDRAM. CS0 should always be connected to
+ // a boot flash. The BW bits are set from external pins
+ // QSPI_CS0/CSPI_CLK and are preserved here. Arguably that
+ // should not be necessary but it allows for platforms where
+ // the hardware has gone through several revisions and it
+ // is undesirable to build different images for different
+ // revisions. The overhead is small, just two instructions.
+ move.l HAL_MCF5272_CSBR0 (%a5), %d0
+ andi.l # HAL_MCF5272_CSBR_BW_MASK, %d0
+ ori.l # (_HAL_MCF5272_CSBR0_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR0 (%a5)
+ move.l # (_HAL_MCF5272_CSOR0_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR0 (%a5)
+
+ // Chip selects 1-6 may or may not be connected. If not just leave
+ // them to their default disabled state.
+ .ifdef _HAL_MCF5272_CSBR1_VALUE_
+ move.l # (_HAL_MCF5272_CSBR1_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR1 (%a5)
+ move.l # (_HAL_MCF5272_CSOR1_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR1 (%a5)
+ .endif
+ .ifdef _HAL_MCF5272_CSBR2_VALUE_
+ move.l # (_HAL_MCF5272_CSBR2_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR2 (%a5)
+ move.l # (_HAL_MCF5272_CSOR2_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR2 (%a5)
+ .endif
+ .ifdef _HAL_MCF5272_CSBR3_VALUE_
+ move.l # (_HAL_MCF5272_CSBR3_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR3 (%a5)
+ move.l # (_HAL_MCF5272_CSOR3_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR3 (%a5)
+ .endif
+ .ifdef _HAL_MCF5272_CSBR4_VALUE_
+ move.l # (_HAL_MCF5272_CSBR4_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR4 (%a5)
+ move.l # (_HAL_MCF5272_CSOR4_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR4 (%a5)
+ .endif
+ .ifdef _HAL_MCF5272_CSBR5_VALUE_
+ move.l # (_HAL_MCF5272_CSBR5_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR5 (%a5)
+ move.l # (_HAL_MCF5272_CSOR5_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR5 (%a5)
+ .endif
+ .ifdef _HAL_MCF5272_CSBR6_VALUE_
+ move.l # (_HAL_MCF5272_CSBR6_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR6 (%a5)
+ move.l # (_HAL_MCF5272_CSOR6_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR6 (%a5)
+ .endif
+
+ // CS7 will go the SDRAM.
+ move.l # (_HAL_MCF5272_CSBR7_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSBR7 (%a5)
+ move.l # (_HAL_MCF5272_CSOR7_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_CSOR7 (%a5)
+
+ // The SDRAM should now be ready for its first commands.
+ // The timer register needs to be done first, then the
+ // control register, and finally a dummy write to memory.
+ // That dummy write causes the SDRAM controller to take
+ // the necessary actions, and the memory should be usable
+ // a few cycles later.
+ move.l # (_HAL_MCF5272_SDTR_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_SDTR (%a5)
+ move.l # (_HAL_MCF5272_SDCR_VALUE_), %d0
+ move.l %d0, HAL_MCF5272_SDCR (%a5)
+ clr.l 0
+ .endm
+
+// ----------------------------------------------------------------------------
+// Now that the utility macros are defined include the platform HAL.
+#include <cyg/hal/plf.inc>
+
+// And if the platform HAL requests it, provide the standard initialization
+// code.
+#if defined(_HAL_MCF5272_STANDARD_INIT_ROM_)
+ .macro _hal_m68k_mcf5272_start_
+ // Initial stack and program counter
+ .long 0
+ .long 8
+ _hal_mcf5272_remap_flash_
+ .endm
+
+ .macro _hal_m68k_mcf5272_setup1_
+ _hal_mcf5272_init_sysregs_
+ _hal_mcf5272_init_memory_
+ .endm
+
+# define _HAL_M68K_START_ _hal_m68k_mcf5272_start_
+# define _HAL_M68K_PLATFORM_SETUP1_ _hal_m68k_mcf5272_setup1_
+# define _HAL_M68K_COPY_ROM_DATA_TO_RAM_ 1
+
+#elif defined(_HAL_MCF5272_STANDARD_INIT_RAM_)
+ .macro _hal_m68k_mcf5272_start_
+ .endm
+
+ .macro _hal_m68k_mcf5272_setup1_
+ // Always initialize the remaining system registers, in case the
+ // application needs different values from RedBoot for some reason.
+ _hal_mcf5272_init_sysregs_
+ .endm
+
+# define _HAL_M68K_START_ _hal_m68k_mcf5272_start_
+# define _HAL_M68K_PLATFORM_SETUP1_ _hal_m68k_mcf5272_setup1_
+#endif
+
+// ----------------------------------------------------------------------------
+// end of proc.inc
Index: include/proc_arch.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_arch.h,v
retrieving revision 1.1
diff -u -p -r1.1 proc_arch.h
--- include/proc_arch.h 29 May 2002 18:28:16 -0000 1.1
+++ include/proc_arch.h 20 Nov 2008 22:49:06 -0000
@@ -7,11 +7,10 @@
// Processor variant specific abstractions
//
//=============================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
+// Copyright (C) 2003,2006,2008 Free Software Foundation, Inc.
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
@@ -34,32 +33,53 @@
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2003-06-04
+//
+//####DESCRIPTIONEND####
+//=============================================================================
-#include <pkgconf/hal.h>
+#include <pkgconf/hal_m68k_mcf5272.h>
+#include <cyg/hal/plf_arch.h>
#include <cyg/infra/cyg_type.h>
-#include <cyg/hal/mcf5272_sim.h>
-//#include <cyg/hal/hal_memmap.h>
-
-// Declare the global pointer to the SIM registers.
-// Everyone should use the MCF5272_SIM macro so it can be easily changed.
-externC volatile mcf5272_sim_t * const mcf5272_sim_p;
-#define MCF5272_SIM mcf5272_sim_p
-//#define MCF5272_SIM ((volatile mcf5272_sim_t *) MCF5272_MBAR)
-
-/* ************************************************************************ */
-/* These routines write to the special purpose registers in the ColdFire */
-/* core. Since these registers are write-only in the supervisor model, no */
-/* corresponding read routines exist. */
+// A processor-specific initialization routine is needed
+#if !defined(__ASSEMBLER__) && !defined(HAL_M68K_PROC_INIT)
+externC void hal_m68k_mcf5272_init(void);
+#define HAL_M68K_PROC_INIT() hal_m68k_mcf5272_init()
+#endif
+
+// The MCF5272 does not support the bitrev or ff1 instructions so the
+// architectural default versions of HAL_LSBIT_INDEX() and
+// HAL_MSBIT_INDEX() have to be used instead of the mcfxxxx ones.
+#define _HAL_M68K_MCFxxxx_NO_FF1_ 1
+
+// Idle action support.
+#if !defined(HAL_IDLE_THREAD_ACTION)
+# if defined(CYGIMP_HAL_M68K_MCF5272_IDLE_run)
+ // Do nothing, just use the architectural empty default
+# else
+
+# define HAL_IDLE_THREAD_ACTION(_count_) \
+ CYG_MACRO_START \
+ asm volatile ( \
+ "mov.w %%sr, %%d0 ; \n" \
+ "mov.w %%d0, 0(%[alpr]); \n" \
+ "stop #0x2000 ; \n" \
+ "mov.w %%d0, %%sr ; \n" \
+ : \
+ : [alpr] "a" (HAL_MCFxxxx_MBAR + HAL_MCF5272_ALPR) \
+ : "d0" ); \
+ CYG_MACRO_END
-externC void mcf5272_wr_mbar(CYG_WORD32);
+# endif
+#endif
-//-----------------------------------------------------------------------------
+// ----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PROC_ARCH_H
Index: include/proc_cache.h
===================================================================
RCS file: include/proc_cache.h
diff -N include/proc_cache.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ include/proc_cache.h 20 Nov 2008 22:49:06 -0000
@@ -0,0 +1,99 @@
+#ifndef CYGONCE_PROC_CACHE_H
+#define CYGONCE_PROC_CACHE_H
+//=============================================================================
+//
+// proc_cache.h
+//
+// Cache details for an mcf5272
+//
+//=============================================================================
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003,2004,2006,2008 Free Software Foundation, Inc.
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2003-06-04
+//
+//####DESCRIPTIONEND####
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/var_io.h>
+
+// An mcf5272 has a 1k direct-mapped instruction cache, 64 lines * 16 bytes.
+// There is no data cache. The cache control register is write-only so it
+// is necessary to keep a soft copy.
+
+externC cyg_uint32 hal_mcf5272_cacr;
+
+#define HAL_ICACHE_SIZE 1024
+#define HAL_ICACHE_LINE_SIZE 16
+#define HAL_ICACHE_WAYS 64
+#define HAL_ICACHE_SETS 1
+
+#define HAL_ICACHE_ENABLE() \
+ CYG_MACRO_START \
+ hal_mcf5272_cacr = (hal_mcf5272_cacr & ~HAL_MCFxxxx_CACR_CINV) | HAL_MCFxxxx_CACR_CENB; \
+ asm volatile ( "movec.l %0,%%cacr\n" : : "d" (hal_mcf5272_cacr) : "memory") ; \
+ CYG_MACRO_END
+
+#define HAL_ICACHE_DISABLE() \
+ CYG_MACRO_START \
+ hal_mcf5272_cacr &= ~(HAL_MCFxxxx_CACR_CENB | HAL_MCFxxxx_CACR_CINV); \
+ asm volatile ( "movec.l %0,%%cacr\n" : : "d" (hal_mcf5272_cacr) : "memory") ; \
+ CYG_MACRO_END
+
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ _state_ = (0 != (hal_mcf5272_cacr & HAL_MCFxxxx_CACR_CENB)); \
+ CYG_MACRO_END
+
+// A full cache invalidate takes 64 cycles. This is expensive if only one
+// or two lines need to be invalidated, but doing the arithmetic and tests
+// needed to affect just the necessary lines would also take quite a few
+// cycles. Hence it is simpler to just invalidate the lot.
+#define HAL_ICACHE_INVALIDATE_ALL() \
+ CYG_MACRO_START \
+ asm volatile ( "movec.l %0,%%cacr\n" : : "d" (hal_mcf5272_cacr | HAL_MCFxxxx_CACR_CINV) : "memory" ); \
+ CYG_MACRO_END
+
+#define HAL_ICACHE_INVALIDATE(_base_, _size_) \
+ CYG_MACRO_START \
+ HAL_ICACHE_INVALIDATE_ALL(); \
+ CYG_MACRO_END
+
+#define HAL_ICACHE_SYNC() \
+ CYG_MACRO_START \
+ HAL_ICACHE_INVALIDATE_ALL(); \
+ CYG_MACRO_END
+
+#endif // ifndef CYGONCE_PROC_CACHE_H
+// End of proc_cache.h
+
Index: include/proc_intr.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_intr.h,v
retrieving revision 1.1
diff -u -p -r1.1 proc_intr.h
--- include/proc_intr.h 29 May 2002 18:28:16 -0000 1.1
+++ include/proc_intr.h 20 Nov 2008 22:49:07 -0000
@@ -8,11 +8,10 @@
// mcf5272 Processor variant interrupt and clock support
//
//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
+// Copyright (C) 2003,2004,2005,2006,2008 Free Software Foundation, Inc.
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
@@ -35,177 +34,271 @@
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2003-06-04
+//
+//####DESCRIPTIONEND####
+//=============================================================================
-#include <pkgconf/hal.h>
-#include <cyg/infra/cyg_type.h>
-
-// Include any platform specific interrupt definitions.
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_cache.h>
#include <cyg/hal/plf_intr.h>
-// Include for the SIM address (MCF5272_SIM).
-#include <cyg/hal/proc_arch.h>
-
//---------------------------------------------------------------------------
// Interrupt controller management
+//
+// There are 32 interrupt sources, all vectored using VSR's 64 onwards.
+// The ISR vector numbers are 0 to 31.
-// This chip has a programmable interrupt vector base which is different
-// from the vector base register (VBR). All interrupts from the interrupt
-// controller are offsets from the programmable interrupt vector register
-// (PIVR).
-
-#define HAL_PROG_INT_VEC_BASE 64
+#define HAL_MCF5272_INT_VEC_BASE 64
// Vector numbers defined by the interrupt controller.
-// These are all relative to the interrupt vector base number.
-#define CYGNUM_HAL_VECTOR_USR_SPUR_INT (0 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_EXTINT1 (1 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_EXTINT2 (2 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_EXTINT3 (3 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_EXTINT4 (4 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_TMR1 (5 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_TMR2 (6 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_TMR3 (7 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_TMR4 (8 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_UART1 (9 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_UART2 (10 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_PLIP (11 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_PLIA (12 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB0 (13 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB1 (14 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB2 (15 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB3 (16 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB4 (17 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB5 (18 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB6 (19 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_USB7 (20 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_DMA (21 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_ERX (22 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_ETX (23 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_ENTC (24 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_QSPI (25 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_EXTINT5 (26 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_EXTINT6 (27 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_SWTO (28 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_RES1 (29 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_RES2 (30 + HAL_PROG_INT_VEC_BASE)
-#define CYGNUM_HAL_VECTOR_RES3 (31 + HAL_PROG_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USR_SPUR_INT ( 0 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EXTINT1 ( 1 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EXTINT2 ( 2 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EXTINT3 ( 3 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EXTINT4 ( 4 + HAL_MCF5272_INT_VEC_BASE)
+// The User's Manual uses TMR1 to TMR4 for the interrupt numbers, which
+// is inconsistent with the chapter on the timers themselves. TMR0-TMR3
+// are used here instead.
+#define CYGNUM_HAL_VECTOR_TMR0 ( 5 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_TMR1 ( 6 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_TMR2 ( 7 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_TMR3 ( 8 + HAL_MCF5272_INT_VEC_BASE)
+// The User's Manual uses UART1 and UART2 when describing the interrupt
+// controller. UART0 and UART1 are used instead here, for consistency
+// with other parts of the code and documentation.
+#define CYGNUM_HAL_VECTOR_UART0 ( 9 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_UART1 (10 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_PLIP (11 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_PLIA (12 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB0 (13 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB1 (14 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB2 (15 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB3 (16 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB4 (17 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB5 (18 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB6 (19 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_USB7 (20 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_DMA (21 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_ERX (22 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_ETX (23 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_ENTC (24 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_QSPI (25 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EXTINT5 (26 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EXTINT6 (27 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_SWTO (28 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_RES1 (29 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_RES2 (30 + HAL_MCF5272_INT_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_RES3 (31 + HAL_MCF5272_INT_VEC_BASE)
+
+// ISR numbering starts with 0 corresponding to VSR 64, even though
+// that interrupt won't actually be raised. This costs some memory and
+// adds a bit of complexity to the mask/unmask macros, but saves an
+// instruction during ISR decoding.
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_USR_SPUR_INT 0
+#define CYGNUM_HAL_ISR_EXTINT1 1
+#define CYGNUM_HAL_ISR_EXTINT2 2
+#define CYGNUM_HAL_ISR_EXTINT3 3
+#define CYGNUM_HAL_ISR_EXTINT4 4
+#define CYGNUM_HAL_ISR_TMR0 5
+#define CYGNUM_HAL_ISR_TMR1 6
+#define CYGNUM_HAL_ISR_TMR2 7
+#define CYGNUM_HAL_ISR_TMR3 8
+#define CYGNUM_HAL_ISR_UART0 9
+#define CYGNUM_HAL_ISR_UART1 10
+#define CYGNUM_HAL_ISR_PLIP 11
+#define CYGNUM_HAL_ISR_PLIA 12
+#define CYGNUM_HAL_ISR_USB0 13
+#define CYGNUM_HAL_ISR_USB1 14
+#define CYGNUM_HAL_ISR_USB2 15
+#define CYGNUM_HAL_ISR_USB3 16
+#define CYGNUM_HAL_ISR_USB4 17
+#define CYGNUM_HAL_ISR_USB5 18
+#define CYGNUM_HAL_ISR_USB6 19
+#define CYGNUM_HAL_ISR_USB7 20
+#define CYGNUM_HAL_ISR_DMA 21
+#define CYGNUM_HAL_ISR_ERX 22
+#define CYGNUM_HAL_ISR_ETX 23
+#define CYGNUM_HAL_ISR_ENTC 24
+#define CYGNUM_HAL_ISR_QSPI 25
+#define CYGNUM_HAL_ISR_EXTINT5 26
+#define CYGNUM_HAL_ISR_EXTINT6 27
+#define CYGNUM_HAL_ISR_SWTO 28
+#define CYGNUM_HAL_ISR_RES1 29
+#define CYGNUM_HAL_ISR_RES2 30
+#define CYGNUM_HAL_ISR_RES3 31
+
+#define CYGNUM_HAL_ISR_MAX 28
+#define CYGNUM_HAL_ISR_COUNT 29
//---------------------------------------------------------------------------
// Interrupt controller macros.
-// Declare a mirror copy of the interrupt control registers used to set
-// interrupt priorities. In order to mask and unmask a specific interrupt, we
-// must be able to set its priority to zero and then restore it to ist
-// original priority. We use these locations to determine the level to
-// restore the interrupt to in the unmask macro.
-
-externC cyg_uint32 hal_icr_pri_mirror[4];
-
-// Block the interrupt associated with the given vector. To do this, we
-// set the interrupt priority level to zero for the specified interrupt. To
-// set the interrupt priority level, we simultaneously write a 1 to the
-// pending interrupt field. The other interrupts are unaffected. Disable all
-// interrupts while we access the hardware registers.
-
-#define HAL_INTERRUPT_MASK( _vector_ ) \
-CYG_MACRO_START \
- cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
- cyg_uint32 _icr = _vec_offset / 8; \
- cyg_uint32 _icr_msk = 0xf0000000 >> ((_vec_offset % 8) * 4); \
- CYG_INTERRUPT_STATE _intr_state; \
- HAL_DISABLE_INTERRUPTS(_intr_state); \
- MCF5272_SIM->intc.icr[_icr] &= _icr_msk ^ 0x77777777; \
- HAL_RESTORE_INTERRUPTS(_intr_state); \
-CYG_MACRO_END
-
-// Unblock the interrupt associated with the given vector. Set the
-// interrupt priority using the value from the icr mirror variable. Disable
-// all interrupts while we access the hardware registers.
-
-#define HAL_INTERRUPT_UNMASK( _vector_ ) \
-CYG_MACRO_START \
- cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
- cyg_uint32 _icr = _vec_offset / 8; \
- cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \
- cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \
- cyg_uint32 _icr_val; \
- CYG_INTERRUPT_STATE _intr_state; \
- HAL_DISABLE_INTERRUPTS(_intr_state); \
- _icr_val = MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \
- _icr_val |= hal_icr_pri_mirror[_icr] & _icr_msk; \
- _icr_val |= 0x08 << _icr_msk_offset; \
- MCF5272_SIM->intc.icr[_icr] = _icr_val; \
- HAL_RESTORE_INTERRUPTS(_intr_state); \
-CYG_MACRO_END
-
-// Acknowledge the interrupt by writing a 1 to the corresponding
-// interrupt pending bit. Write 0 to all other interrupt pending bits. Leave
-// all priority levels unchanged. Disable all interrupts while we access the
-// hardware registers.
-
-#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
-CYG_MACRO_START \
- cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
- cyg_uint32 _icr = _vec_offset / 8; \
- cyg_uint32 _icr_msk = 0x80000000 >> ((_vec_offset % 8) * 4); \
- CYG_INTERRUPT_STATE _intr_state; \
- HAL_DISABLE_INTERRUPTS(_intr_state); \
- MCF5272_SIM->intc.icr[_icr] &= _icr_msk | 0x77777777; \
- HAL_RESTORE_INTERRUPTS(_intr_state); \
-CYG_MACRO_END
-
-// Set the priority in the interrupt control register and the icr mirror.
-// Do not copy the icr mirror into the icr because some interrupts may be
-// masked. Disable all interrupts while we access the hardware registers.
-
-#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_ ) \
-CYG_MACRO_START \
- cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
- cyg_uint32 _icr = _vec_offset / 8; \
- cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \
- cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \
- cyg_uint32 _icr_val = (0x08 | (_prilevel_ & 0x07)) << _icr_msk_offset; \
- CYG_INTERRUPT_STATE _intr_state; \
- HAL_DISABLE_INTERRUPTS(_intr_state); \
- cyg_uint32 _mir_val = hal_icr_pri_mirror[_icr] & 0x77777777 & ~_icr_msk; \
- hal_icr_pri_mirror[_icr] = _mir_val | _icr_val; \
- _icr_val |= MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \
- MCF5272_SIM->intc.icr[_icr] = _icr_val; \
- HAL_RESTORE_INTERRUPTS(_intr_state); \
-CYG_MACRO_END
-
-// Set/clear the interrupt transition register bit. Disable all
-// interrupts while we access the hardware registers.
-
-// WARNING: It seems that manual currently has the polarity of this bit
-// wrong.
-
-#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_ ) \
-CYG_MACRO_START \
- if (!(_leveltriggered_)) \
- { \
- cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
- cyg_uint32 _itr_bit = 0x80000000 >> _vec_offset; \
- CYG_INTERRUPT_STATE _intr_state; \
- HAL_DISABLE_INTERRUPTS(_intr_state); \
- if (_up_) \
- { \
- MCF5272_SIM->intc.pitr |= _itr_bit; \
- } \
- else \
- { \
- MCF5272_SIM->intc.pitr &= ~_itr_bit; \
- } \
- HAL_RESTORE_INTERRUPTS(_intr_state); \
- } \
-CYG_MACRO_END
+// Declare a mirror copy of the interrupt control registers used to
+// set interrupt priorities. In order to mask and unmask a specific
+// interrupt, we must be able to set its priority to zero and then
+// restore it to ist original priority. We use these locations to
+// determine the level to restore the interrupt to in the unmask
+// macro.
+
+externC cyg_uint32 hal_mcf5272_icr_pri_mirror[4];
+
+// Some of the operations should only be applied to external interrupts.
+#define HAL_MCF5272_EXTERNAL_INTERRUPTS \
+ ((0x01 << CYGNUM_HAL_ISR_EXTINT1) | (0x01 << CYGNUM_HAL_ISR_EXTINT2) | \
+ (0x01 << CYGNUM_HAL_ISR_EXTINT3) | (0x01 << CYGNUM_HAL_ISR_EXTINT4) | \
+ (0x01 << CYGNUM_HAL_ISR_EXTINT5) | (0x01 << CYGNUM_HAL_ISR_EXTINT6))
+
+// Block an interrupt source. This involves setting the ISR vector's
+// interrupt priority level to 0. The PI bit should be set to 1 for
+// just the interrupt of interest, and the rest of the word written
+// to the ICR register should be 0.
+
+#define HAL_INTERRUPT_MASK( _vector_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 offset = ((_vector_) - 1) / 8; \
+ cyg_uint32 shift = (((_vector_) - 1) % 8) * 4; \
+ cyg_uint32 mask = 0x80000000; \
+ mask >>= shift; \
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask); \
+ CYG_MACRO_END
+
+// Unblock an interrupt source. This involves restoring the ISR vector's
+// interrupt priority level using the saved mirrors. The PI bit should be
+// set to 1 for just the interrupt of interest, so the rest of the write
+// will be ignored.
+
+#define HAL_INTERRUPT_UNMASK( _vector_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 offset = ((_vector_) - 1) / 8; \
+ cyg_uint32 shift = (((_vector_) - 1) % 8) * 4; \
+ cyg_uint32 mask = 0x80000000; \
+ mask >>= shift; \
+ mask |= hal_mcf5272_icr_pri_mirror[offset]; \
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask); \
+ CYG_MACRO_END
+
+// Set the priority in the interrupt control register and the icr
+// mirror.
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_) \
+ CYG_MACRO_START \
+ CYG_INTERRUPT_STATE ints_enabled; \
+ cyg_uint32 offset = ((_vector_) - 1) / 8; \
+ cyg_uint32 shift = (((_vector_) - 1) % 8) * 4; \
+ cyg_uint32 mask = 0xF0000000; \
+ cyg_uint32 new_level = (_prilevel_) & 0x07; \
+ mask >>= shift; \
+ new_level <<= (28 - shift); \
+ HAL_DISABLE_INTERRUPTS(ints_enabled); \
+ hal_mcf5272_icr_pri_mirror[offset] &= ~mask; \
+ hal_mcf5272_icr_pri_mirror[offset] |= new_level; \
+ mask &= 0x88888888; \
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask | new_level); \
+ HAL_RESTORE_INTERRUPTS(ints_enabled); \
+ CYG_MACRO_END
+
+// Acknowledge is only relevant for external interrupts. It is necessary to
+// write a 1 to the PI bit, which will unfortunately also reset this
+// interrupt vector's priority level.
+#define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \
+ CYG_MACRO_START \
+ if (0 != (HAL_MCF5272_EXTERNAL_INTERRUPTS & (0x01 << (_vector_)))) { \
+ cyg_uint32 offset = ((_vector_) - 1) / 8; \
+ cyg_uint32 shift = (((_vector_ - 1)) % 8) * 4; \
+ cyg_uint32 mask = 0x80000000; \
+ mask >>= shift; \
+ mask |= hal_mcf5272_icr_pri_mirror[offset]; \
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_ICR1 + (offset << 2), mask); \
+ } \
+ CYG_MACRO_END
+
+// Select between level and edge triggered. This is only relevant for the external
+// interrupt sources. The interrupts remain level-triggered, but it is possible
+// to choose between rising and falling interrupts.
+//
+// NOTE: the manual states 0 for low->high, 1 for high->low. The original code
+// inverted this, claiming the manual is wrong. I have stuck with the original
+// code's usage, but have not tested this.
+
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_) \
+ CYG_MACRO_START \
+ if (0 != (HAL_MCF5272_EXTERNAL_INTERRUPTS & (0x01 << (_vector_)))) { \
+ cyg_uint32 mask = 0x80000000 >> ((_vector_) - 1); \
+ cyg_uint32 pitr; \
+ HAL_READ_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PITR, pitr); \
+ if (_up_) { \
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PITR, pitr | mask); \
+ } else { \
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PITR, pitr & ~mask); \
+ } \
+ } \
+ CYG_MACRO_END
+
+// ----------------------------------------------------------------------------
+// The clock. Timer 3 is used for the eCos system clock. Timers 0 and
+// 1 offer additional functionality which is not required by eCos, so
+// those are best left to application code. Timer 2 is used as the
+// profiling timer, if desired. The prescaler is set to the clock's
+// MHz rating provided by the platform HAL, so each tick is one
+// microsecond.
+
+#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_ISR_TMR3)
+
+#define HAL_CLOCK_INITIALIZE(_period_) \
+ CYG_MACRO_START \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TMR, 0); \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TRR, \
+ (_period_) - 1); \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TCN, 0); \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TER, \
+ HAL_MCF5272_TIMER_TER_REF | HAL_MCF5272_TIMER_TER_CAP); \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TMR, \
+ ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ - 1) << HAL_MCF5272_TIMER_TMR_PS_SHIFT) | \
+ HAL_MCF5272_TIMER_TMR_ORI | HAL_MCF5272_TIMER_TMR_FRR | \
+ HAL_MCF5272_TIMER_TMR_CLK_MASTER | HAL_MCF5272_TIMER_TMR_RST); \
+ CYG_MACRO_END
+
+// The timer itself runs in restart mode, but it is still necessary to
+// reset the bits affecting the interrupt controller.
+#define HAL_CLOCK_RESET(_vector_, _period_) \
+ CYG_MACRO_START \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TER, HAL_MCF5272_TIMER_TER_REF); \
+ CYG_MACRO_END
+
+#define HAL_CLOCK_READ(_pvalue_) \
+ CYG_MACRO_START \
+ cyg_uint16 _tmp_; \
+ HAL_READ_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER3_BASE + HAL_MCF5272_TIMER_TCN, _tmp_); \
+ *(_pvalue_) = _tmp_; \
+ CYG_MACRO_END
+
+#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
+
+// ----------------------------------------------------------------------------
+// HAL_DELAY_US(). Just use the default implementation from hal_intr.h
+#ifndef _HAL_M68K_DELAY_US_LOOPS_
+# define _HAL_M68K_DELAY_US_LOOPS_ 20
+# define _HAL_M68K_DELAY_US_UNCACHED_ 2
+#endif
+
+// ----------------------------------------------------------------------------
+// For reset, use the watchdog device.
+#ifndef HAL_PLATFORM_RESET
+# define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ int _ints_state_; \
+ HAL_DISABLE_INTERRUPTS(_ints_state_); \
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_WRRR, 0x03); \
+ for ( ; ; ) ; \
+ CYG_MACRO_END
+#endif
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PROC_INTR_H
-
Index: include/proc_io.h
===================================================================
RCS file: include/proc_io.h
diff -N include/proc_io.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ include/proc_io.h 20 Nov 2008 22:49:09 -0000
@@ -0,0 +1,1273 @@
+//=============================================================================
+//
+// proc_io.h
+//
+// Details of mcf5272 memory-mapped hardware
+//
+//=============================================================================
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003,2004,2006,2008 Free Software Foundation, Inc.
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2003-06-04
+//
+//####DESCRIPTIONEND####
+//=============================================================================
+
+// This header gets #include'd twice by var_io.h. The first time is to
+// define the peripherals which are shared with the 5282. The second
+// time is for overriding, in case of small differences between this
+// processor's on-chip peripherals and the 5282's.
+#if !defined(CYGONCE_HAL_PROC_IO_H_FIRST)
+# define CYGONCE_HAL_PROC_IO_H_FIRST
+
+# include <pkgconf/system.h>
+# include <pkgconf/hal_m68k_mcf5272.h>
+# include CYGBLD_HAL_PLATFORM_H
+
+# define HAL_MCFxxxx_HAS_MCF5282_RAMBAR 1
+# define HAL_MCFxxxx_HAS_MCF5282_VBR 1
+# define HAL_MCFxxxx_HAS_MCF5282_CACR_ACR 1
+
+# define HAL_MCFxxxx_HAS_MCF5282_UART 2
+# define HAL_MCFxxxx_UART0_BASE (HAL_MCFxxxx_MBAR + 0x00000100)
+# define HAL_MCFxxxx_UART1_BASE (HAL_MCFxxxx_MBAR + 0x00000140)
+# define HAL_MCFxxxx_UART0_RXFIFO_SIZE 24
+# define HAL_MCFxxxx_UART1_RXFIFO_SIZE 24
+# define HAL_MCFxxxx_HAS_MCF5282_QSPI 1
+# define HAL_MCFxxxx_QSPI0_BASE (HAL_MCFxxxx_MBAR + 0x000000A0)
+# define HAL_MCFxxxx_QSPI_SINGLETON_BASE HAL_MCFxxxx_QSPI0_BASE
+# define HAL_MCFxxxx_QSPI_SINGLETON_ISRVEC CYGNUM_HAL_ISR_QSPI
+# define HAL_MCFxxxx_QSPI_SINGLETON_ISRPRI CYGNUM_HAL_M68K_MCF5272_QSPI_ISRPRI
+# define HAL_MCFxxxx_HAS_MCF5282_ETH 1
+# define HAL_MCFxxxx_ETH0_BASE (HAL_MCFxxxx_MBAR + 0x0840)
+
+// ----------------------------------------------------------------------------
+#elif !defined(CYGONCE_HAL_PROC_IO_H_SECOND)
+# define CYGONCE_HAL_PROC_IO_H_SECOND
+
+// Now to handle the differences between the MCF5272 and the MCF5282
+// MBAR - controls access to the system integration module
+
+#define HAL_MCF5272_MBAR_BA_MASK 0xFFFF0000
+#define HAL_MCF5272_MBAR_BA_SHIFT 16
+#define HAL_MCF5272_MBAR_SC (0x01 << 4)
+#define HAL_MCF5272_MBAR_SD (0x01 << 3)
+#define HAL_MCF5272_MBAR_UC (0x01 << 2)
+#define HAL_MCF5272_MBAR_UD (0x01 << 1)
+#define HAL_MCF5272_MBAR_V (0x01 << 0)
+
+# undef HAL_MCFxxxx_RAMBAR
+# define HAL_MCFxxxx_RAMBAR 0x0C04
+# undef HAL_MCFxxxx_RAMBAR_PRI_MASK
+# undef HAL_MCFxxxx_RAMBAR_PRI_SHIFT
+# undef HAL_MCFxxxx_RAMBAR_PRI_CPU_CPU
+# undef HAL_MCFxxxx_RAMBAR_PRI_CPU_DMA
+# undef HAL_MCFxxxx_RAMBAR_PRI_DMA_CPU
+# undef HAL_MCFxxxx_RAMBAR_PRI_DMA_DMA
+# undef HAL_MCFxxxx_RAMBAR_SPV
+
+# undef HAL_MCFxxxx_CACR_DISI
+# undef HAL_MCFxxxx_CACR_DISD
+# undef HAL_MCFxxxx_CACR_INVI
+# undef HAL_MCFxxxx_CACR_INVD
+# undef HAL_MCFxxxx_CACR_EUSP
+
+// The UARTs. Five additional registers and some extra bits.
+// Baud rates can be set more precisely using the fractional
+// register.
+# define HAL_MCFxxxx_UARTx_UABU 0x20
+# define HAL_MCFxxxx_UARTx_UABL 0x24
+# define HAL_MCFxxxx_UARTx_UTF 0x28
+# define HAL_MCFxxxx_UARTx_URF 0x2C
+# define HAL_MCFxxxx_UARTx_UFPD 0x30
+
+#define HAL_MCFxxxx_UARTx_UCR_ENAB (0x01 << 7)
+
+#define HAL_MCFxxxx_UARTx_UISR_ABC (0x01 << 6)
+#define HAL_MCFxxxx_UARTx_UISR_RXFIFO (0x01 << 5)
+#define HAL_MCFxxxx_UARTx_UISR_TXFIFO (0x01 << 4)
+#define HAL_MCFxxxx_UARTx_UISR_RXFTO (0x01 << 3)
+
+#define HAL_MCFxxxx_UARTx_UIMR_ABC (0x01 << 6)
+#define HAL_MCFxxxx_UARTx_UIMR_RXFIFO (0x01 << 5)
+#define HAL_MCFxxxx_UARTx_UIMR_TXFIFO (0x01 << 4)
+#define HAL_MCFxxxx_UARTx_UIMR_RXFTO (0x01 << 3)
+
+// Automatic RTS control depending on fifo levels
+#define HAL_MCFxxxx_UARTx_UACR_RTSL_MASK (0x03 << 1)
+#define HAL_MCFxxxx_UARTx_UACR_RTSL_DISABLED (0x00 << 1)
+#define HAL_MCFxxxx_UARTx_UACR_RTSL_25 (0x01 << 1)
+#define HAL_MCFxxxx_UARTx_UACR_RTSL_50 (0x02 << 1)
+#define HAL_MCFxxxx_UARTx_UACR_RTSL_75 (0x03 << 1)
+
+// Fifo control
+#define HAL_MCFxxxx_UARTx_UTF_TXS_MASK (0x03 << 6)
+#define HAL_MCFxxxx_UARTx_UTF_TXS_INHIBIT (0x00 << 6)
+#define HAL_MCFxxxx_UARTx_UTF_TXS_25 (0x01 << 6)
+#define HAL_MCFxxxx_UARTx_UTF_TXS_50 (0x02 << 6)
+#define HAL_MCFxxxx_UARTx_UTF_TXS_75 (0x03 << 6)
+#define HAL_MCFxxxx_UARTx_UTF_FULL (0x01 << 5)
+#define HAL_MCFxxxx_UARTx_UTF_TXB_MASK (0x1F << 0)
+
+#define HAL_MCFxxxx_UARTx_URF_RXS_MASK (0x03 << 6)
+#define HAL_MCFxxxx_UARTx_URF_RXS_INHIBIT (0x00 << 6)
+#define HAL_MCFxxxx_UARTx_URF_RXS_25 (0x01 << 6)
+#define HAL_MCFxxxx_UARTx_URF_RXS_50 (0x02 << 6)
+#define HAL_MCFxxxx_UARTx_URF_RXS_75 (0x03 << 6)
+#define HAL_MCFxxxx_UARTx_URF_FULL (0x01 << 5)
+#define HAL_MCFxxxx_UARTx_URF_RXB_MASK (0x1F << 0)
+
+#define HAL_MCFxxxx_UARTx_UFPD_FD_MASK (0x0F << 0)
+
+#undef HAL_MCFxxxx_UARTx_SET_BAUD
+#define HAL_MCFxxxx_UARTx_SET_BAUD(_base_, _baud_) \
+ CYG_MACRO_START \
+ cyg_uint8 _udu_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (32 * (_baud_))) >> 8)); \
+ cyg_uint8 _udl_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (32 * (_baud_))) & 0x00FF)); \
+ cyg_uint8 _ufpd_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * (_baud_))) & 0x000F)); \
+ HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG1, _udu_); \
+ HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG2, _udl_); \
+ HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UFPD, _ufpd_); \
+ CYG_MACRO_END
+
+// QSPI. It is not clear the QWR CPTQP bits are defined. Otherwise the device
+// matches the 5282's exactly.
+
+// Ethernet. There are many differences between the 5272 and the 5282
+// implementations.
+# undef HAL_MCFxxxx_ETHx_ECR
+# define HAL_MCFxxxx_ETHx_ECR 0x0000
+# define HAL_MCFxxxx_ETHx_IVSR 0x000C
+# undef HAL_MCFxxxx_ETHx_MIBC
+# undef HAL_MCFxxxx_ETHx_RCR
+# define HAL_MCFxxxx_ETHx_RCR 0x0104
+# define HAL_MCFxxxx_ETHx_MFLR 0x0108
+# undef HAL_MCFxxxx_ETHx_TCR
+# define HAL_MCFxxxx_ETHx_TCR 0x0144
+# undef HAL_MCFxxxx_ETHx_PALR
+# define HAL_MCFxxxx_ETHx_PALR 0x03C0
+# undef HAL_MCFxxxx_ETHx_PAUR
+# define HAL_MCFxxxx_ETHx_PAUR 0x03C4
+# undef HAL_MCFxxxx_ETHx_OPD
+# undef HAL_MCFxxxx_ETHx_IAUR
+# undef HAL_MCFxxxx_ETHx_IALR
+# undef HAL_MCFxxxx_ETHx_GAUR
+# define HAL_MCFxxxx_ETHx_GAUR 0x03C8
+# undef HAL_MCFxxxx_ETHx_GALR
+# define HAL_MCFxxxx_ETHx_GALR 0x03CC
+# define HAL_MCFxxxx_ETHx_TFSR 0x00AC
+# undef HAL_MCFxxxx_ETHx_TFWR
+# define HAL_MCFxxxx_ETHx_TFWR 0x00A4
+# undef HAL_MCFxxxx_ETHx_FRBR
+# define HAL_MCFxxxx_ETHx_FRBR 0x008C
+# undef HAL_MCFxxxx_ETHx_FRSR
+# define HAL_MCFxxxx_ETHx_FRSR 0x0090
+# undef HAL_MCFxxxx_ETHx_ERDSR
+# define HAL_MCFxxxx_ETHx_ERDSR 0x03D0
+# undef HAL_MCFxxxx_ETHx_ETDSR
+# define HAL_MCFxxxx_ETHx_ETDSR 0x03D4
+# undef HAL_MCFxxxx_ETHx_EMRBR
+# define HAL_MCFxxxx_ETHx_EMRBR 0x03D8
+
+# undef HAL_MCFxxxx_ETHx_RMON_T_DROP
+# undef HAL_MCFxxxx_ETHx_RMON_T_PACKETS
+# undef HAL_MCFxxxx_ETHx_RMON_T_BC_PKT
+# undef HAL_MCFxxxx_ETHx_RMON_T_MC_PKT
+# undef HAL_MCFxxxx_ETHx_RMON_T_CRC_ALIGN
+# undef HAL_MCFxxxx_ETHx_RMON_T_UNDERSIZE
+# undef HAL_MCFxxxx_ETHx_RMON_T_OVERSIZE
+# undef HAL_MCFxxxx_ETHx_RMON_T_FRAG
+# undef HAL_MCFxxxx_ETHx_RMON_T_JAB
+# undef HAL_MCFxxxx_ETHx_RMON_T_COL
+# undef HAL_MCFxxxx_ETHx_RMON_T_P64
+# undef HAL_MCFxxxx_ETHx_RMON_T_P65TO127
+# undef HAL_MCFxxxx_ETHx_RMON_T_P128TO255
+# undef HAL_MCFxxxx_ETHx_RMON_T_P256TO511
+# undef HAL_MCFxxxx_ETHx_RMON_T_P512TO1023
+# undef HAL_MCFxxxx_ETHx_RMON_T_P1024TO2047
+# undef HAL_MCFxxxx_ETHx_RMON_T_PGTE2048
+# undef HAL_MCFxxxx_ETHx_RMON_T_OCTETS
+# undef HAL_MCFxxxx_ETHx_IEEE_T_DROP
+# undef HAL_MCFxxxx_ETHx_IEEE_T_FRAME_OK
+# undef HAL_MCFxxxx_ETHx_IEEE_T_1COL
+# undef HAL_MCFxxxx_ETHx_IEEE_T_MCOL
+# undef HAL_MCFxxxx_ETHx_IEEE_T_DEF
+# undef HAL_MCFxxxx_ETHx_IEEE_T_LCOL
+# undef HAL_MCFxxxx_ETHx_IEEE_T_EXCOL
+# undef HAL_MCFxxxx_ETHx_IEEE_T_MACERR
+# undef HAL_MCFxxxx_ETHx_IEEE_T_CSERR
+# undef HAL_MCFxxxx_ETHx_IEEE_T_SQE
+# undef HAL_MCFxxxx_ETHx_IEEE_T_FDXFC
+# undef HAL_MCFxxxx_ETHx_IEEE_T_OCTETS_OK
+# undef HAL_MCFxxxx_ETHx_RMON_R_PACKETS
+# undef HAL_MCFxxxx_ETHx_RMON_R_BC_PKT
+# undef HAL_MCFxxxx_ETHx_RMON_R_MC_PKT
+# undef HAL_MCFxxxx_ETHx_RMON_R_CRC_ALIGN
+# undef HAL_MCFxxxx_ETHx_RMON_R_UNDERSIZE
+# undef HAL_MCFxxxx_ETHx_RMON_R_OVERSIZE
+# undef HAL_MCFxxxx_ETHx_RMON_R_FRAG
+# undef HAL_MCFxxxx_ETHx_RMON_R_JAB
+# undef HAL_MCFxxxx_ETHx_RMON_R_RESVD_0
+# undef HAL_MCFxxxx_ETHx_RMON_R_P64
+# undef HAL_MCFxxxx_ETHx_RMON_R_P65TO127
+# undef HAL_MCFxxxx_ETHx_RMON_R_P128TO255
+# undef HAL_MCFxxxx_ETHx_RMON_R_P256TO511
+# undef HAL_MCFxxxx_ETHx_RMON_R_P512TO1023
+# undef HAL_MCFxxxx_ETHx_RMON_R_P1024TO2047
+# undef HAL_MCFxxxx_ETHx_RMON_R_GTE2048
+# undef HAL_MCFxxxx_ETHx_RMON_R_OCTETS
+# undef HAL_MCFxxxx_ETHx_IEEE_R_DROP
+# undef HAL_MCFxxxx_ETHx_IEEE_R_FRAME_OK
+# undef HAL_MCFxxxx_ETHx_IEEE_R_CRC
+# undef HAL_MCFxxxx_ETHx_IEEE_R_ALIGN
+# undef HAL_MCFxxxx_ETHx_IEEE_R_MACERR
+# undef HAL_MCFxxxx_ETHx_IEEE_R_FDXFC
+# undef HAL_MCFxxxx_ETHx_IEEE_R_OCTETS_OK
+
+# undef HAL_MCFxxxx_ETHx_EIR_LC
+# undef HAL_MCFxxxx_ETHx_EIR_RL
+# undef HAL_MCFxxxx_ETHx_EIR_UN
+# define HAL_MCFxxxx_ETHx_EIR_UMINT (0x01 << 21)
+
+# undef HAL_MCFxxxx_ETHx_EIMR_LC
+# undef HAL_MCFxxxx_ETHx_EIMR_RL
+# undef HAL_MCFxxxx_ETHx_EIMR_UN
+
+# undef HAL_MCFxxxx_ETHx_MIBC_MIB_DISABLE
+# undef HAL_MCFxxxx_ETHx_MIBC_MIB_IDLE
+
+# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_MASK
+# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_SHIFT
+# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_VALUE
+# undef HAL_MCFxxxx_ETHx_RCR_FCE
+# undef HAL_MCFxxxx_ETHx_RCR_BC_REJ
+
+# undef HAL_MCFxxxx_ETHx_TCR_RFC_PAUSE
+# undef HAL_MCFxxxx_ETHx_TCR_TFC_PAUSE
+
+# undef HAL_MCFxxxx_ETHx_OPD_OPCODE_MASK
+# undef HAL_MCFxxxx_ETHx_OPD_OPCODE_SHIFT
+# undef HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_MASK
+# undef HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_SHIFT
+
+# define HAL_MCFxxxx_ETHx_RXBD_SH (0x01 << 3)
+
+# undef HAL_MCFxxxx_ETHx_TXBD_ABC
+# define HAL_MCFxxxx_ETHx_TXBD_DEF (0x01 << 9)
+# define HAL_MCFxxxx_ETHx_TXBD_HB (0x01 << 8)
+# define HAL_MCFxxxx_ETHx_TXBD_LC (0x01 << 7)
+# define HAL_MCFxxxx_ETHx_TXBD_RL (0x01 << 6)
+# define HAL_MCFxxxx_ETHx_TXBD_RC_MASK (0x0F << 2)
+# define HAL_MCFxxxx_ETHx_TXBD_RC_SHIFT 2
+# define HAL_MCFxxxx_ETHx_TXBD_UN (0x01 << 1)
+# define HAL_MCFxxxx_ETHx_TXBD_CSL (0x01 << 0)
+
+// ----------------------------------------------------------------------------
+// ----------------------------------------------------------------------------
+// Next the units specific to the 5272
+
+// The ROM base address register. The ROM size depends on the particular
+// processor, and that controls how many of bits 9 to 31 are significant.
+#define HAL_MCF5272_ROMBAR_WP (0x01 << 8)
+// Mask cpu space and interrupt acknowledge accesses
+#define HAL_MCF5272_ROMBAR_AS5 (0x01 << 5)
+// Mask supervisor code accesses
+#define HAL_MCF5272_ROMBAR_AS4 (0x01 << 4)
+// Mask supervisor data accesses
+#define HAL_MCF5272_ROMBAR_AS3 (0x01 << 3)
+// Mask user code accesses
+#define HAL_MCF5272_ROMBAR_AS2 (0x01 << 2)
+// Mask user data accesses
+#define HAL_MCF5272_ROMBAR_AS1 (0x01 << 1)
+// Has the ROMBAR register been initialized yet?
+#define HAL_MCF5272_ROMBAR_VALID (0x01 << 0)
+
+// ----------------------------------------------------------------------------
+// System registers in the system integration module. PMR and DIR are
+// 32-bit. SCR, SPR, and ALPR are 16-bit.
+
+#define HAL_MCF5272_SCR 0x0004
+#define HAL_MCF5272_SPR 0x0006
+#define HAL_MCF5272_PMR 0x0008
+#define HAL_MCF5272_ALPR 0x000E
+#define HAL_MCF5272_DIR 0x0010
+
+// System configuration register
+#define HAL_MCF5272_SCR_RSTSRC_MASK (0x03 << 12)
+#define HAL_MCF5272_SCR_RSTSRC_RSTI (0x01 << 12)
+#define HAL_MCF5272_SCR_RSTSRC_WATCHDOG (0x02 << 12)
+#define HAL_MCF5272_SCR_RSTSRC_RSTI_DRESETEN (0x03 << 12)
+#define HAL_MCF5272_SCR_PRIORITY_MASK (0x01 << 8)
+#define HAL_MCF5272_SCR_PRIORITY_ETHERNET (0x00 << 8)
+#define HAL_MCF5272_SCR_PRIORITY_CPU (0x01 << 8)
+#define HAL_MCF5272_SCR_AR_MASK (0x01 << 7)
+#define HAL_MCF5272_SCR_AR_RELINQUISH (0x00 << 7)
+#define HAL_MCF5272_SCR_AR_INCLUDE (0x01 << 7)
+#define HAL_MCF5272_SCR_AR_SOFTRST (0x01 << 6)
+#define HAL_MCF5272_SCR_BUSLOCK_MASK (0x01 << 3)
+#define HAL_MCF5272_SCR_BUSLOCK_ARBITRATION (0x00 << 3)
+#define HAL_MCF5272_SCR_BUSLOCK_RETAIN (0x01 << 3)
+#define HAL_MCF5272_SCR_HWR_MASK (0x07 << 0)
+#define HAL_MCF5272_SCR_HWR_128 (0x00 << 0)
+#define HAL_MCF5272_SCR_HWR_256 (0x01 << 0)
+#define HAL_MCF5272_SCR_HWR_512 (0x02 << 0)
+#define HAL_MCF5272_SCR_HWR_1024 (0x03 << 0)
+#define HAL_MCF5272_SCR_HWR_2048 (0x04 << 0)
+#define HAL_MCF5272_SCR_HWR_4096 (0x05 << 0)
+#define HAL_MCF5272_SCR_HWR_8192 (0x06 << 0)
+#define HAL_MCF5272_SCR_HWR_16384 (0x07 << 0)
+
+// System protection register
+#define HAL_MCF5272_SPR_ADC (0x01 << 15)
+#define HAL_MCF5272_SPR_WPV (0x01 << 14)
+#define HAL_MCF5272_SPR_SMV (0x01 << 13)
+#define HAL_MCF5272_SPR_PE (0x01 << 12)
+#define HAL_MCF5272_SPR_HWT (0x01 << 11)
+#define HAL_MCF5272_SPR_RPV (0x01 << 10)
+#define HAL_MCF5272_SPR_EXT (0x01 << 9)
+#define HAL_MCF5272_SPR_SUV (0x01 << 8)
+#define HAL_MCF5272_SPR_ADCEN (0x01 << 7)
+#define HAL_MCF5272_SPR_WPVEN (0x01 << 6)
+#define HAL_MCF5272_SPR_SMVEN (0x01 << 5)
+#define HAL_MCF5272_SPR_PEEN (0x01 << 4)
+#define HAL_MCF5272_SPR_HWTEN (0x01 << 3)
+#define HAL_MCF5272_SPR_RPVEN (0x01 << 2)
+#define HAL_MCF5272_SPR_EXTEN (0x01 << 1)
+#define HAL_MCF5272_SPR_SUVEN (0x01 << 0)
+
+// Power management register. For power-down, 0 is enabled, 1 disabled.
+// For wakeup 0 is disabled, 1 enabled
+#define HAL_MCF5272_PMR_BDMPDN (0x01 << 31)
+#define HAL_MCF5272_PMR_ENETPDN (0x01 << 26)
+#define HAL_MCF5272_PMR_PLIPDN (0x01 << 25)
+#define HAL_MCF5272_PMR_DRAMPDN (0x01 << 24)
+#define HAL_MCF5272_PMR_DMAPDN (0x01 << 23)
+#define HAL_MCF5272_PMR_PWMPDN (0x01 << 22)
+#define HAL_MCF5272_PMR_QSPIPDN (0x01 << 21)
+#define HAL_MCF5272_PMR_TIMERPDN (0x01 << 20)
+#define HAL_MCF5272_PMR_GPIOPDN (0x01 << 19)
+#define HAL_MCF5272_PMR_USBPDN (0x01 << 18)
+#define HAL_MCF5272_PMR_UART1PDN (0x01 << 17)
+#define HAL_MCF5272_PMR_UART0PDN (0x01 << 16)
+#define HAL_MCF5272_PMR_USBWK (0x01 << 10)
+#define HAL_MCF5272_PMR_UART1WK (0x01 << 9)
+#define HAL_MCF5272_PMR_UART0WK (0x01 << 8)
+#define HAL_MCF5272_PMR_MOS (0x01 << 5)
+#define HAL_MCF5272_PMR_SLPEN (0x01 << 4)
+
+// Device identification register
+#define HAL_MCF5272_DIR_VERSION_MASK (0x0F << 28)
+#define HAL_MCF5272_DIR_VERSION_SHIFT 28
+#define HAL_MCF5272_DIR_DESIGN_CENTER_MASK (0x3F << 22)
+#define HAL_MCF5272_DIR_DESIGN_CENTER_SHIFT 22
+#define HAL_MCF5272_DIR_DEVICE_NUMBER_MASK (0x3FF << 12)
+#define HAL_MCF5272_DIR_DEVICE_NUMBER_SHIFT 12
+#define HAL_MCF5272_DIR_JEDEC_ID_MASK (0x7FF << 1)
+#define HAL_MCF5272_DIR_JEDEC_ID_SHIFT 1
+
+// ----------------------------------------------------------------------------
+// The software watchdog. All registers are 2-bytes wide.
+
+#define HAL_MCF5272_WRRR 0x0280
+#define HAL_MCF5272_WIRR 0x0284
+#define HAL_MCF5272_WCR 0x0288
+#define HAL_MCF5272_WER 0x028C
+
+// ----------------------------------------------------------------------------
+// The interrupt controller. PIVR is a single byte, the others are 32-bit.
+// The bits within the registers are defined by the ISR numbers in proc_intr.h
+#define HAL_MCF5272_ICR1 0x0020
+#define HAL_MCF5272_ICR2 0x0024
+#define HAL_MCF5272_ICR3 0x0028
+#define HAL_MCF5272_ICR4 0x002C
+#define HAL_MCF5272_ISR 0x0030
+#define HAL_MCF5272_PITR 0x0034
+#define HAL_MCF5272_PIWR 0x0038
+#define HAL_MCF5272_PIVR 0x003F
+
+// ----------------------------------------------------------------------------
+// Chip select module. All registers are 32-bit
+#define HAL_MCF5272_CSBR0 0x0040
+#define HAL_MCF5272_CSOR0 0x0044
+#define HAL_MCF5272_CSBR1 0x0048
+#define HAL_MCF5272_CSOR1 0x004C
+#define HAL_MCF5272_CSBR2 0x0050
+#define HAL_MCF5272_CSOR2 0x0054
+#define HAL_MCF5272_CSBR3 0x0058
+#define HAL_MCF5272_CSOR3 0x005C
+#define HAL_MCF5272_CSBR4 0x0060
+#define HAL_MCF5272_CSOR4 0x0064
+#define HAL_MCF5272_CSBR5 0x0068
+#define HAL_MCF5272_CSOR5 0x006C
+#define HAL_MCF5272_CSBR6 0x0070
+#define HAL_MCF5272_CSOR6 0x0074
+#define HAL_MCF5272_CSBR7 0x0078
+#define HAL_MCF5272_CSOR7 0x007C
+
+#define HAL_MCF5272_CSBR_BA_MASK (0xFFFFF000)
+#define HAL_MCF5272_CSBR_EBI_MASK (0x03 << 10)
+#define HAL_MCF5272_CSBR_EBI_16_32 (0x00 << 10)
+#define HAL_MCF5272_CSBR_EBI_SDRAM (0x01 << 10)
+#define HAL_MCF5272_CSBR_EBI_8 (0x03 << 10)
+#define HAL_MCF5272_CSBR_BW_MASK (0x03 << 8)
+#define HAL_MCF5272_CSBR_BW_32 (0x00 << 8)
+#define HAL_MCF5272_CSBR_BW_8 (0x01 << 8)
+#define HAL_MCF5272_CSBR_BW_16 (0x02 << 8)
+#define HAL_MCF5272_CSBR_BW_CACHELINE (0x03 << 8)
+#define HAL_MCF5272_CSBR_SUPER (0x01 << 7)
+#define HAL_MCF5272_CSBR_TT_MASK (0x03 << 5)
+#define HAL_MCF5272_CSBR_TM_MASK (0x07 << 2)
+#define HAL_MCF5272_CSBR_CTM (0x01 << 1)
+#define HAL_MCF5272_CSBR_ENABLE (0x01 << 0)
+
+#define HAL_MCF5272_CSOR_BA_MASK (0xFFFFF000)
+#define HAL_MCF5272_CSOR_ASET (0x01 << 11)
+#define HAL_MCF5272_CSOR_WRAH (0x01 << 10)
+#define HAL_MCF5272_CSOR_RDAH (0x01 << 9)
+#define HAL_MCF5272_CSOR_EXTBURST (0x01 << 8)
+#define HAL_MCF5272_CSOR_WS_MASK (0x1F << 2)
+#define HAL_MCF5272_CSOR_WS_SHIFT 2
+#define HAL_MCF5272_CSOR_RW (0x01 << 1)
+#define HAL_MCF5272_CSOR_MRW (0x01 << 0)
+
+// ----------------------------------------------------------------------------
+// SDRAM controller. Two 16-bit registers.
+
+#define HAL_MCF5272_SDCR 0x0180
+#define HAL_MCF5272_SDTR 0x0184
+
+#define HAL_MCF5272_SDCR_MCAS_MASK (0x03 << 13)
+#define HAL_MCF5272_SDCR_MCAS_A7 (0x00 << 13)
+#define HAL_MCF5272_SDCR_MCAS_A8 (0x01 << 13)
+#define HAL_MCF5272_SDCR_MCAS_A9 (0x02 << 13)
+#define HAL_MCF5272_SDCR_MCAS_A10 (0x03 << 13)
+#define HAL_MCF5272_SDCR_BALOC_MASK (0x07 << 8)
+#define HAL_MCF5272_SDCR_BALOC_A21_A20 (0x01 << 8)
+#define HAL_MCF5272_SDCR_BALOC_A22_A21 (0x02 << 8)
+#define HAL_MCF5272_SDCR_BALOC_A23_A22 (0x03 << 8)
+#define HAL_MCF5272_SDCR_BALOC_A24_A23 (0x04 << 8)
+#define HAL_MCF5272_SDCR_BALOC_A25_A24 (0x05 << 8)
+#define HAL_MCF5272_SDCR_GSL (0x01 << 7)
+#define HAL_MCF5272_SDCR_REG (0x01 << 4)
+#define HAL_MCF5272_SDCR_INV (0x01 << 3)
+#define HAL_MCF5272_SDCR_SLEEP (0x01 << 2)
+#define HAL_MCF5272_SDCR_ACT (0x01 << 1)
+#define HAL_MCF5272_SDCR_INIT (0x01 << 0)
+
+#define HAL_MCF5272_SDTR_RTP_MASK (0x3F << 10)
+#define HAL_MCF5272_SDTR_RTP_66 (0x3D << 10)
+#define HAL_MCF5272_SDTR_RTP_48 (0x2B << 10)
+#define HAL_MCF5272_SDTR_RTP_33 (0x1D << 10)
+#define HAL_MCF5272_SDTR_RTP_25 (0x15 << 10)
+#define HAL_MCF5272_SDTR_RTP_5 (0x04 << 10)
+#define HAL_MCF5272_SDTR_RC_MASK (0x03 << 8)
+#define HAL_MCF5272_SDTR_RC_5 (0x00 << 8)
+#define HAL_MCF5272_SDTR_RC_6 (0x01 << 8)
+#define HAL_MCF5272_SDTR_RC_7 (0x02 << 8)
+#define HAL_MCF5272_SDTR_RC_8 (0x03 << 8)
+#define HAL_MCF5272_SDTR_RP_MASK (0x03 << 4)
+#define HAL_MCF5272_SDTR_RP_1 (0x00 << 4)
+#define HAL_MCF5272_SDTR_RP_2 (0x01 << 4)
+#define HAL_MCF5272_SDTR_RP_3 (0x02 << 4)
+#define HAL_MCF5272_SDTR_RP_4 (0x03 << 4)
+#define HAL_MCF5272_SDTR_RCD_MASK (0x03 << 2)
+#define HAL_MCF5272_SDTR_RCD_1 (0x00 << 2)
+#define HAL_MCF5272_SDTR_RCD_2 (0x01 << 2)
+#define HAL_MCF5272_SDTR_RCD_3 (0x02 << 2)
+#define HAL_MCF5272_SDTR_RCD_4 (0x03 << 2)
+#define HAL_MCF5272_SDTR_CLT_MASK (0x03 << 0)
+#define HAL_MCF5272_SDTR_CLT_2 (0x01 << 0)
+
+// ----------------------------------------------------------------------------
+// DMA controller. DCIR is 16-bit, the rest 32-bit
+#define HAL_MCF5272_DMA_DCMR 0x00E0
+#define HAL_MCF5272_DMA_DCIR 0x00E6
+#define HAL_MCF5272_DMA_DBCR 0x00E8
+#define HAL_MCF5272_DMA_DSAR 0x00EC
+#define HAL_MCF5272_DMA_DDAR 0x00F0
+
+#define HAL_MCF5272_DMA_DCMR_RESET (0x01 << 31)
+#define HAL_MCF5272_DMA_DCMR_EN (0x01 << 30)
+#define HAL_MCF5272_DMA_DCMR_RQM_MASK (0x03 << 18)
+#define HAL_MCF5272_DMA_DCMR_RQM_DUAL (0x03 << 18)
+#define HAL_MCF5272_DMA_DCMR_DSTM_MASK (0x03 << 13)
+#define HAL_MCF5272_DMA_DCMR_DSTM_STATIC (0x00 << 13)
+#define HAL_MCF5272_DMA_DCMR_DSTM_INCREMENT (0x01 << 13)
+#define HAL_MCF5272_DMA_DCMR_DSTT_MASK (0x07 << 10)
+#define HAL_MCF5272_DMA_DCMR_DSTT_UDA (0x01 << 10)
+#define HAL_MCF5272_DMA_DCMR_DSTT_UCA (0x02 << 10)
+#define HAL_MCF5272_DMA_DCMR_DSTT_SDA (0x05 << 10)
+#define HAL_MCF5272_DMA_DCMR_DSTT_SCA (0x06 << 10)
+#define HAL_MCF5272_DMA_DCMR_DSTS_MASK (0x03 << 8)
+#define HAL_MCF5272_DMA_DCMR_DSTS_4 (0x00 << 8)
+#define HAL_MCF5272_DMA_DCMR_DSTS_1 (0x01 << 8)
+#define HAL_MCF5272_DMA_DCMR_DSTS_2 (0x02 << 8)
+#define HAL_MCF5272_DMA_DCMR_DSTS_16 (0x03 << 8)
+#define HAL_MCF5272_DMA_DCMR_SRCM_MASK (0x01 << 5)
+#define HAL_MCF5272_DMA_DCMR_SRCM_STATIC (0x00 << 5)
+#define HAL_MCF5272_DMA_DCMR_SRCM_INCREMENT (0x01 << 5)
+#define HAL_MCF5272_DMA_DCMR_SRCT_MASK (0x07 << 2)
+#define HAL_MCF5272_DMA_DCMR_SRCT_UDA (0x01 << 2)
+#define HAL_MCF5272_DMA_DCMR_SRCT_UCA (0x02 << 2)
+#define HAL_MCF5272_DMA_DCMR_SRCT_SDA (0x05 << 2)
+#define HAL_MCF5272_DMA_DCMR_SRCT_SCA (0x06 << 2)
+#define HAL_MCF5272_DMA_DCMR_SRCS_MASK (0x03 << 0)
+#define HAL_MCF5272_DMA_DCMR_SRCS_4 (0x00 << 0)
+#define HAL_MCF5272_DMA_DCMR_SRCS_1 (0x01 << 0)
+#define HAL_MCF5272_DMA_DCMR_SRCS_2 (0x02 << 0)
+#define HAL_MCF5272_DMA_DCMR_SRCS_16 (0x03 << 0)
+
+#define HAL_MCF5272_DMA_DIR_INVEN (0x01 << 12)
+#define HAL_MCF5272_DMA_DIR_ASCEN (0x01 << 11)
+#define HAL_MCF5272_DMA_DIR_TEEN (0x01 << 9)
+#define HAL_MCF5272_DMA_DIR_TCEN (0x01 << 8)
+#define HAL_MCF5272_DMA_DIR_INV (0x01 << 4)
+#define HAL_MCF5272_DMA_DIR_ASC (0x01 << 3)
+#define HAL_MCF5272_DMA_DIR_TE (0x01 << 1)
+#define HAL_MCF5272_DMA_DIR_TC (0x01 << 0)
+
+// ----------------------------------------------------------------------------
+// USB
+#define HAL_MCF5272_USB_FNR 0x1002
+#define HAL_MCF5272_USB_FNMR 0x1006
+#define HAL_MCF5272_USB_RFMR 0x100A
+#define HAL_MCF5272_USB_RFMMR 0x100E
+#define HAL_MCF5272_USB_FAR 0x1013
+#define HAL_MCF5272_USB_ASR 0x1014
+#define HAL_MCF5272_USB_DDR1 0x1018
+#define HAL_MCF5272_USB_DDR2 0x101C
+#define HAL_MCF5272_USB_SPECR 0x1022
+#define HAL_MCF5272_USB_EP0SR 0x1026
+#define HAL_MCF5272_USB_IEP0CFG 0x1028
+#define HAL_MCF5272_USB_OEP0CFG 0x102C
+#define HAL_MCF5272_USB_EP1CFG 0x1030
+#define HAL_MCF5272_USB_EP2CFG 0x1034
+#define HAL_MCF5272_USB_EP3CFG 0x1038
+#define HAL_MCF5272_USB_EP4CFG 0x103C
+#define HAL_MCF5272_USB_EP5CFG 0x1040
+#define HAL_MCF5272_USB_EP6CFG 0x1044
+#define HAL_MCF5272_USB_EP7CFG 0x1048
+#define HAL_MCF5272_USB_EP0CTL 0x104C
+#define HAL_MCF5272_USB_EP1CTL 0x1052
+#define HAL_MCF5272_USB_EP2CTL 0x1056
+#define HAL_MCF5272_USB_EP3CTL 0x105A
+#define HAL_MCF5272_USB_EP4CTL 0x105E
+#define HAL_MCF5272_USB_EP5CTL 0x1062
+#define HAL_MCF5272_USB_EP6CTL 0x1066
+#define HAL_MCF5272_USB_EP7CTL 0x106A
+#define HAL_MCF5272_USB_EP0ISR 0x106C
+#define HAL_MCF5272_USB_EP1ISR 0x1072
+#define HAL_MCF5272_USB_EP2ISR 0x1076
+#define HAL_MCF5272_USB_EP3ISR 0x107A
+#define HAL_MCF5272_USB_EP4ISR 0x107E
+#define HAL_MCF5272_USB_EP5ISR 0x1082
+#define HAL_MCF5272_USB_EP6ISR 0x1086
+#define HAL_MCF5272_USB_EP7ISR 0x108A
+#define HAL_MCF5272_USB_EP0IMR 0x108C
+#define HAL_MCF5272_USB_EP1IMR 0x1092
+#define HAL_MCF5272_USB_EP2IMR 0x1096
+#define HAL_MCF5272_USB_EP3IMR 0x109A
+#define HAL_MCF5272_USB_EP4IMR 0x109E
+#define HAL_MCF5272_USB_EP5IMR 0x10A2
+#define HAL_MCF5272_USB_EP6IMR 0x10A6
+#define HAL_MCF5272_USB_EP7IMR 0x10AA
+#define HAL_MCF5272_USB_EP0DR 0x10AC
+#define HAL_MCF5272_USB_EP1DR 0x10B0
+#define HAL_MCF5272_USB_EP2DR 0x10B4
+#define HAL_MCF5272_USB_EP3DR 0x10B8
+#define HAL_MCF5272_USB_EP4DR 0x10BC
+#define HAL_MCF5272_USB_EP5DR 0x10C0
+#define HAL_MCF5272_USB_EP6DR 0x10C4
+#define HAL_MCF5272_USB_EP7DR 0x10C8
+#define HAL_MCF5272_USB_EP0DPR 0x10CE
+#define HAL_MCF5272_USB_EP1DPR 0x10D2
+#define HAL_MCF5272_USB_EP2DPR 0x10D6
+#define HAL_MCF5272_USB_EP3DPR 0x10DA
+#define HAL_MCF5272_USB_EP4DPR 0x10DE
+#define HAL_MCF5272_USB_EP5DPR 0x10E2
+#define HAL_MCF5272_USB_EP6DPR 0x10E6
+#define HAL_MCF5272_USB_EP7DPR 0x10EA
+#define HAL_MCF5272_USB_CONFIG 0x1400
+
+#define HAL_MCF5272_USB_ASR_IF15_MASK (0x03 << 30)
+#define HAL_MCF5272_USB_ASR_IF15_SHIFT 30
+#define HAL_MCF5272_USB_ASR_IF14_MASK (0x03 << 28)
+#define HAL_MCF5272_USB_ASR_IF14_SHIFT 28
+#define HAL_MCF5272_USB_ASR_IF13_MASK (0x03 << 26)
+#define HAL_MCF5272_USB_ASR_IF13_SHIFT 26
+#define HAL_MCF5272_USB_ASR_IF12_MASK (0x03 << 24)
+#define HAL_MCF5272_USB_ASR_IF12_SHIFT 24
+#define HAL_MCF5272_USB_ASR_IF11_MASK (0x03 << 22)
+#define HAL_MCF5272_USB_ASR_IF11_SHIFT 22
+#define HAL_MCF5272_USB_ASR_IF10_MASK (0x03 << 20)
+#define HAL_MCF5272_USB_ASR_IF10_SHIFT 20
+#define HAL_MCF5272_USB_ASR_IF9_MASK (0x03 << 18)
+#define HAL_MCF5272_USB_ASR_IF9_SHIFT 18
+#define HAL_MCF5272_USB_ASR_IF8_MASK (0x03 << 16)
+#define HAL_MCF5272_USB_ASR_IF8_SHIFT 16
+#define HAL_MCF5272_USB_ASR_IF7_MASK (0x03 << 14)
+#define HAL_MCF5272_USB_ASR_IF7_SHIFT 14
+#define HAL_MCF5272_USB_ASR_IF6_MASK (0x03 << 12)
+#define HAL_MCF5272_USB_ASR_IF6_SHIFT 12
+#define HAL_MCF5272_USB_ASR_IF5_MASK (0x03 << 10)
+#define HAL_MCF5272_USB_ASR_IF5_SHIFT 10
+#define HAL_MCF5272_USB_ASR_IF4_MASK (0x03 << 8)
+#define HAL_MCF5272_USB_ASR_IF4_SHIFT 8
+#define HAL_MCF5272_USB_ASR_IF3_MASK (0x03 << 6)
+#define HAL_MCF5272_USB_ASR_IF3_SHIFT 6
+#define HAL_MCF5272_USB_ASR_IF2_MASK (0x03 << 4)
+#define HAL_MCF5272_USB_ASR_IF2_SHIFT 4
+#define HAL_MCF5272_USB_ASR_IF1_MASK (0x03 << 2)
+#define HAL_MCF5272_USB_ASR_IF1_SHIFT 2
+#define HAL_MCF5272_USB_ASR_IF0_MASK (0x03 << 0)
+#define HAL_MCF5272_USB_ASR_IF0_SHIFT 0
+
+#define HAL_MCF5272_USB_DDR1_wValue_MASK (0x0FFFF << 16)
+#define HAL_MCF5272_USB_DDR1_wValue_SHIFT 16
+#define HAL_MCF5272_USB_DDR1_bRequest_MASK (0x0FF << 8)
+#define HAL_MCF5272_USB_DDR1_bRequest_SHIFT 8
+#define HAL_MCF5272_USB_DDR1_bmRequestType_MASK (0x0FF << 0)
+#define HAL_MCF5272_USB_DDR1_bmRequestType_SHIFT 0
+#define HAL_MCF5272_USB_DDR2_wLength_MASK (0x0FFFF << 16)
+#define HAL_MCF5272_USB_DDR2_wLength_SHIFT 16
+#define HAL_MCF5272_USB_DDR2_wIndex_MASK (0x0FFFF << 0)
+#define HAL_MCF5272_USB_DDR2_wIndex_SHIFT 0
+
+#define HAL_MCF5272_USB_SPECR_SPEC_MASK (0x0FFF0 << 4)
+#define HAL_MCF5272_USB_SPECR_SPEC_SHIFT 4
+#define HAL_MCF5272_USB_SPECR_MRN_MASK (0x0F << 0)
+#define HAL_MCF5272_USB_SPECR_MRN_SHIFT (0x0F << 0)
+
+#define HAL_MCF5272_USB_EP0SR_CONFIG_MASK (0x0F << 12)
+#define HAL_MCF5272_USB_EP0SR_CONFIG_SHIFT 12
+#define HAL_MCF5272_USB_EP0SR_WAKE_ST (0x01 << 11)
+#define HAL_MCF5272_USB_EP0SR_HALT_ST (0x01 << 2)
+#define HAL_MCF5272_USB_EP0SR_DIR_MASK (0x01 << 1)
+#define HAL_MCF5272_USB_EP0SR_DIR_IN (0x01 << 1)
+#define HAL_MCF5272_USB_EP0SR_DIR_OUT (0x00 << 1)
+
+#define HAL_MCF5272_USB_IEP0CFG_MAX_PACKET_MASK (0x03FF << 22)
+#define HAL_MCF5272_USB_IEP0CFG_MAX_PACKET_SHIFT 22
+#define HAL_MCF5272_USB_IEP0CFG_FIFO_SIZE_MASK (0x03FF << 11)
+#define HAL_MCF5272_USB_IEP0CFG_FIFO_SIZE_SHIFT 11
+#define HAL_MCF5272_USB_IEP0CFG_FIFO_ADDR_MASK (0x03FF << 0)
+#define HAL_MCF5272_USB_IEP0CFG_FIFO_ADDR_SHIFT 0
+
+#define HAL_MCF5272_USB_OEP0CFG_MAX_PACKET_MASK (0x03FF << 22)
+#define HAL_MCF5272_USB_OEP0CFG_MAX_PACKET_SHIFT 22
+#define HAL_MCF5272_USB_OEP0CFG_FIFO_SIZE_MASK (0x03FF << 11)
+#define HAL_MCF5272_USB_OEP0CFG_FIFO_SIZE_SHIFT 11
+#define HAL_MCF5272_USB_OEP0CFG_FIFO_ADDR_MASK (0x03FF << 0)
+#define HAL_MCF5272_USB_OEP0CFG_FIFO_ADDR_SHIFT 0
+
+#define HAL_MCF5272_USB_EPnCFG_MAX_PACKET_MASK (0x03FF << 22)
+#define HAL_MCF5272_USB_EPnCFG_MAX_PACKET_SHIFT 22
+#define HAL_MCF5272_USB_EPnCFG_FIFO_SIZE_MASK (0x03FF << 11)
+#define HAL_MCF5272_USB_EPnCFG_FIFO_SIZE_SHIFT 11
+#define HAL_MCF5272_USB_EPnCFG_FIFO_ADDR_MASK (0x03FF << 0)
+#define HAL_MCF5272_USB_EPnCFG_FIFO_ADDR_SHIFT 0
+
+#define HAL_MCF5272_USB_EP0CTL_DEBUG (0x01 << 18)
+#define HAL_MCF5272_USB_EP0CTL_WOR_LVL (0x01 << 17)
+#define HAL_MCF5272_USB_EP0CTL_WOR_EN (0x01 << 16)
+#define HAL_MCF5272_USB_EP0CTL_CLK_SEL (0x01 << 15)
+#define HAL_MCF5272_USB_EP0CTL_RESUME (0x01 << 14)
+#define HAL_MCF5272_USB_EP0CTL_AFE_EN (0x01 << 13)
+#define HAL_MCF5272_USB_EP0CTL_BUS_PWR (0x01 << 12)
+#define HAL_MCF5272_USB_EP0CTL_USB_EN (0x01 << 11)
+#define HAL_MCF5272_USB_EP0CTL_CFG_RAM_VAL (0x01 << 10)
+#define HAL_MCF5272_USB_EP0CTL_CMD_ERR (0x01 << 9)
+#define HAL_MCF5272_USB_EP0CTL_CMD_OVER (0x01 << 8)
+#define HAL_MCF5272_USB_EP0CTL_CMD_CRC_ERR (0x01 << 7)
+#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_MASK (0x03 << 4)
+#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_25 (0x00 << 4)
+#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_50 (0x01 << 4)
+#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_75 (0x02 << 4)
+#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_100 (0x03 << 4)
+#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_MASK (0x03 << 2)
+#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_25 (0x00 << 2)
+#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_50 (0x01 << 2)
+#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_75 (0x02 << 2)
+#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_100 (0x03 << 2)
+#define HAL_MCF5272_USB_EP0CTL_IN_DONE (0x01 << 1)
+
+#define HAL_MCF5272_USB_EPnCR_CRC_ERR (0x01 << 7)
+#define HAL_MCF5272_USB_EPnCR_ISO_MODE (0x01 << 6)
+#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_MASK (0x03 << 2)
+#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_25 (0x00 << 2)
+#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_50 (0x01 << 2)
+#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_75 (0x02 << 2)
+#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_100 (0x03 << 2)
+#define HAL_MCF5272_USB_EPnCR_IN_DONE (0x01 << 1)
+#define HAL_MCF5272_USB_EPnCR_STALL (0x01 << 0)
+
+#define HAL_MCF5272_USB_EP0IMR_DEV_CFG (0x01 << 16)
+#define HAL_MCF5272_USB_EP0IMR_VEND_REQ (0x01 << 15)
+#define HAL_MCF5272_USB_EP0IMR_FRM_MAT (0x01 << 14)
+#define HAL_MCF5272_USB_EP0IMR_ASOF (0x01 << 13)
+#define HAL_MCF5272_USB_EP0IMR_SOF (0x01 << 12)
+#define HAL_MCF5272_USB_EP0IMR_WAKE_CHG (0x01 << 11)
+#define HAL_MCF5272_USB_EP0IMR_RESUME (0x01 << 10)
+#define HAL_MCF5272_USB_EP0IMR_SUSPEND (0x01 << 9)
+#define HAL_MCF5272_USB_EP0IMR_RESET (0x01 << 8)
+#define HAL_MCF5272_USB_EP0IMR_OUT_EOT (0x01 << 7)
+#define HAL_MCF5272_USB_EP0IMR_OUT_EOP (0x01 << 6)
+#define HAL_MCF5272_USB_EP0IMR_OUT_LVL (0x01 << 5)
+#define HAL_MCF5272_USB_EP0IMR_IN_EOT (0x01 << 4)
+#define HAL_MCF5272_USB_EP0IMR_IN_EOP (0x01 << 3)
+#define HAL_MCF5272_USB_EP0IMR_UNHALT (0x01 << 2)
+#define HAL_MCF5272_USB_EP0IMR_HALT (0x01 << 1)
+#define HAL_MCF5272_USB_EP0IMR_IN_LVL (0x01 << 0)
+
+#define HAL_MCF5272_USB_EP0ISR_DEV_CFG HAL_MCF5272_USB_EP0IMR_DEV_CFG
+#define HAL_MCF5272_USB_EP0ISR_VEND_REQ HAL_MCF5272_USB_EP0IMR_VEND_REQ
+#define HAL_MCF5272_USB_EP0ISR_FRM_MAT HAL_MCF5272_USB_EP0IMR_FRM_MAT
+#define HAL_MCF5272_USB_EP0ISR_ASOF HAL_MCF5272_USB_EP0IMR_ASOF
+#define HAL_MCF5272_USB_EP0ISR_SOF HAL_MCF5272_USB_EP0IMR_SOF
+#define HAL_MCF5272_USB_EP0ISR_WAKE_CHG HAL_MCF5272_USB_EP0IMR_WAKE_CHG
+#define HAL_MCF5272_USB_EP0ISR_RESUME HAL_MCF5272_USB_EP0IMR_RESUME
+#define HAL_MCF5272_USB_EP0ISR_SUSPEND HAL_MCF5272_USB_EP0IMR_SUSPEND
+#define HAL_MCF5272_USB_EP0ISR_RESET HAL_MCF5272_USB_EP0IMR_RESET
+#define HAL_MCF5272_USB_EP0ISR_OUT_EOT HAL_MCF5272_USB_EP0IMR_OUT_EOT
+#define HAL_MCF5272_USB_EP0ISR_OUT_EOP HAL_MCF5272_USB_EP0IMR_OUT_EOP
+#define HAL_MCF5272_USB_EP0ISR_OUT_LVL HAL_MCF5272_USB_EP0IMR_OUT_LVL
+#define HAL_MCF5272_USB_EP0ISR_IN_EOT HAL_MCF5272_USB_EP0IMR_IN_EOT
+#define HAL_MCF5272_USB_EP0ISR_IN_EOP HAL_MCF5272_USB_EP0IMR_IN_EOP
+#define HAL_MCF5272_USB_EP0ISR_UNHALT HAL_MCF5272_USB_EP0IMR_UNHALT
+#define HAL_MCF5272_USB_EP0ISR_HALT HAL_MCF5272_USB_EP0IMR_HALT
+#define HAL_MCF5272_USB_EP0ISR_IN_LVL HAL_MCF5272_USB_EP0IMR_IN_LVL
+
+#define HAL_MCF5272_USB_EPnISR_HALT_ST (0x01 << 15)
+#define HAL_MCF5272_USB_EPnISR_DIR (0x01 << 14)
+#define HAL_MCF5272_USB_EPnISR_PRES (0x01 << 13)
+#define HAL_MCF5272_USB_EPnISR_EOT (0x01 << 4)
+#define HAL_MCF5272_USB_EPnISR_EOP (0x01 << 3)
+#define HAL_MCF5272_USB_EPnISR_UNHALT (0x01 << 2)
+#define HAL_MCF5272_USB_EPnISR_HALT (0x01 << 1)
+#define HAL_MCF5272_USB_EPnISR_FIFO_LVL (0x01 << 0)
+
+#define HAL_MCF5272_USB_EPnIMR_EOT HAL_MCF5272_USB_EPnISR_EOT
+#define HAL_MCF5272_USB_EPnIMR_EOP HAL_MCF5272_USB_EPnISR_EOP
+#define HAL_MCF5272_USB_EPnIMR_UNHALT HAL_MCF5272_USB_EPnISR_UNHALT
+#define HAL_MCF5272_USB_EPnIMR_HALT HAL_MCF5272_USB_EPnISR_HALT
+#define HAL_MCF5272_USB_EPnIMR_FIFO_LVL HAL_MCF5272_USB_EPnISR_FIFO_LVL
+
+// ----------------------------------------------------------------------------
+// PLIC
+
+#define HAL_MCF5272_PLIC_P0B1RR 0x0300
+#define HAL_MCF5272_PLIC_P1B1RR 0x0304
+#define HAL_MCF5272_PLIC_P2B1RR 0x0308
+#define HAL_MCF5272_PLIC_P3B1RR 0x030C
+#define HAL_MCF5272_PLIC_P0B2RR 0x0310
+#define HAL_MCF5272_PLIC_P1B2RR 0x0314
+#define HAL_MCF5272_PLIC_P2B2RR 0x0318
+#define HAL_MCF5272_PLIC_P3B2RR 0x031C
+#define HAL_MCF5272_PLIC_P0DDR 0x0320
+#define HAL_MCF5272_PLIC_P1DDR 0x0321
+#define HAL_MCF5272_PLIC_P2DDR 0x0322
+#define HAL_MCF5272_PLIC_P3DDR 0x0323
+#define HAL_MCF5272_PLIC_P0B1TR 0x0328
+#define HAL_MCF5272_PLIC_P1B1TR 0x032C
+#define HAL_MCF5272_PLIC_P2B1TR 0x0330
+#define HAL_MCF5272_PLIC_P3B1TR 0x0334
+#define HAL_MCF5272_PLIC_P0B2TR 0x0338
+#define HAL_MCF5272_PLIC_P1B2TR 0x033C
+#define HAL_MCF5272_PLIC_P2B2TR 0x0340
+#define HAL_MCF5272_PLIC_P3B2TR 0x0344
+#define HAL_MCF5272_PLIC_P0DTR 0x0348
+#define HAL_MCF5272_PLIC_P1DTR 0x0349
+#define HAL_MCF5272_PLIC_P2DTR 0x034A
+#define HAL_MCF5272_PLIC_P3DTR 0x034B
+#define HAL_MCF5272_PLIC_P0CR 0x0350
+#define HAL_MCF5272_PLIC_P1CR 0x0352
+#define HAL_MCF5272_PLIC_P2CR 0x0354
+#define HAL_MCF5272_PLIC_P3CR 0x0356
+#define HAL_MCF5272_PLIC_P0ICR 0x0358
+#define HAL_MCF5272_PLIC_P1ICR 0x035A
+#define HAL_MCF5272_PLIC_P2ICR 0x035C
+#define HAL_MCF5272_PLIC_P3ICR 0x035E
+#define HAL_MCF5272_PLIC_P0GMR 0x0360
+#define HAL_MCF5272_PLIC_P1GMR 0x0362
+#define HAL_MCF5272_PLIC_P2GMR 0x0364
+#define HAL_MCF5272_PLIC_P3GMR 0x0366
+#define HAL_MCF5272_PLIC_P0GMT 0x0368
+#define HAL_MCF5272_PLIC_P1GMT 0x036A
+#define HAL_MCF5272_PLIC_P2GMT 0x036C
+#define HAL_MCF5272_PLIC_P3GMT 0x036E
+#define HAL_MCF5272_PLIC_PGMTS 0x0371
+#define HAL_MCF5272_PLIC_PGMTA 0x0372
+#define HAL_MCF5272_PLIC_P0GCIR 0x0374
+#define HAL_MCF5272_PLIC_P1GCIR 0x0375
+#define HAL_MCF5272_PLIC_P2GCIR 0x0376
+#define HAL_MCF5272_PLIC_P3GCIR 0x0377
+#define HAL_MCF5272_PLIC_P0GCIT 0x0378
+#define HAL_MCF5272_PLIC_P1GCIT 0x0379
+#define HAL_MCF5272_PLIC_P2GCIT 0x037A
+#define HAL_MCF5272_PLIC_P3GCIT 0x037B
+#define HAL_MCF5272_PLIC_PGCITSR 0x037F
+#define HAL_MCF5272_PLIC_PDCSR 0x0383
+#define HAL_MCF5272_PLIC_P0PSR 0x0384
+#define HAL_MCF5272_PLIC_P1PSR 0x0386
+#define HAL_MCF5272_PLIC_P2PSR 0x0388
+#define HAL_MCF5272_PLIC_P3PSR 0x038A
+#define HAL_MCF5272_PLIC_PASR 0x038C
+#define HAL_MCF5272_PLIC_PLCR 0x038F
+#define HAL_MCF5272_PLIC_PDRQR 0x0392
+#define HAL_MCF5272_PLIC_P0SDR 0x0394
+#define HAL_MCF5272_PLIC_P1SDR 0x0396
+#define HAL_MCF5272_PLIC_P2SDR 0x0398
+#define HAL_MCF5272_PLIC_P3SDR 0x039A
+#define HAL_MCF5272_PLIC_PCSR 0x039E
+
+#define HAL_MCF5272_PLIC_PnCR_ON_OFF (0x01 << 15)
+#define HAL_MCF5272_PLIC_PnCR_M_MASK (0x07 << 12)
+#define HAL_MCF5272_PLIC_PnCR_M_SHIFT 12
+#define HAL_MCF5272_PLIC_PnCR_IDL8 (0x00 << 12)
+#define HAL_MCF5272_PLIC_PnCR_IDL10 (0x01 << 12)
+#define HAL_MCF5272_PLIC_PnCR_GCI (0x02 << 12)
+#define HAL_MCF5272_PLIC_PnCR_M_S (0x01 << 11)
+#define HAL_MCF5272_PLIC_PnCR_G_S (0x01 << 10)
+#define HAL_MCF5272_PLIC_PnCR_FSM (0x01 << 9)
+#define HAL_MCF5272_PLIC_PnCR_ACT (0x01 << 8)
+#define HAL_MCF5272_PLIC_PnCR_DMX (0x01 << 7)
+#define HAL_MCF5272_PLIC_PnCR_SHB2 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PnCR_SHB1 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PnCR_ENB2 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PnCR_ENB1 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PLCR_LM3_MASK (0x03 << 6)
+#define HAL_MCF5272_PLIC_PLCR_LM3_SHIFT 6
+#define HAL_MCF5272_PLIC_PLCR_LM2_MASK (0x03 << 4)
+#define HAL_MCF5272_PLIC_PLCR_LM2_SHIFT 4
+#define HAL_MCF5272_PLIC_PLCR_LM1_MASK (0x03 << 2)
+#define HAL_MCF5272_PLIC_PLCR_LM1_SHIFT 2
+#define HAL_MCF5272_PLIC_PLCR_LM0_MASK (0x03 << 0)
+#define HAL_MCF5272_PLIC_PLCR_LM0_SHIFT 0
+#define HAL_MCF5272_PLIC_PLCR_LMn_NORMAL (0x00)
+#define HAL_MCF5272_PLIC_PLCR_LMn_AUTO_ECHO (0x01)
+#define HAL_MCF5272_PLIC_PLCR_LMn_LOCAL_LOOPBACK (0x02)
+#define HAL_MCF5272_PLIC_PLCR_LMn_REMOTE_LOOPBACK (0x03)
+#define HAL_MCF5272_PLIC_PLCR_LM3_NORMAL (0x00 << 6)
+#define HAL_MCF5272_PLIC_PLCR_LM3_AUTO_ECHO (0x01 << 6)
+#define HAL_MCF5272_PLIC_PLCR_LM3_LOCAL_LOOPBACK (0x02 << 6)
+#define HAL_MCF5272_PLIC_PLCR_LM3_REMOTE_LOOPBACK (0x03 << 6)
+#define HAL_MCF5272_PLIC_PLCR_LM2_NORMAL (0x00 << 4)
+#define HAL_MCF5272_PLIC_PLCR_LM2_AUTO_ECHO (0x01 << 4)
+#define HAL_MCF5272_PLIC_PLCR_LM2_LOCAL_LOOPBACK (0x02 << 4)
+#define HAL_MCF5272_PLIC_PLCR_LM2_REMOTE_LOOPBACK (0x03 << 4)
+#define HAL_MCF5272_PLIC_PLCR_LM1_NORMAL (0x00 << 2)
+#define HAL_MCF5272_PLIC_PLCR_LM1_AUTO_ECHO (0x01 << 2)
+#define HAL_MCF5272_PLIC_PLCR_LM1_LOCAL_LOOPBACK (0x02 << 2)
+#define HAL_MCF5272_PLIC_PLCR_LM1_REMOTE_LOOPBACK (0x03 << 2)
+#define HAL_MCF5272_PLIC_PLCR_LM0_NORMAL (0x00 << 0)
+#define HAL_MCF5272_PLIC_PLCR_LM0_AUTO_ECHO (0x01 << 0)
+#define HAL_MCF5272_PLIC_PLCR_LM0_LOCAL_LOOPBACK (0x02 << 0)
+#define HAL_MCF5272_PLIC_PLCR_LM0_REMOTE_LOOPBACK (0x03 << 0)
+
+#define HAL_MCF5272_PLIC_PnICR_IE (0x01 << 15)
+#define HAL_MCF5272_PLIC_PnICR_GCR (0x01 << 11)
+#define HAL_MCF5272_PLIC_PnICR_GCT (0x01 << 10)
+#define HAL_MCF5272_PLIC_PnICR_GMR (0x01 << 9)
+#define HAL_MCF5272_PLIC_PnICR_GMT (0x01 << 8)
+#define HAL_MCF5272_PLIC_PnICR_DTIE (0x01 << 5)
+#define HAL_MCF5272_PLIC_PnICR_B2TIE (0x01 << 4)
+#define HAL_MCF5272_PLIC_PnICR_B1TIE (0x01 << 3)
+#define HAL_MCF5272_PLIC_PnICR_DRIE (0x01 << 2)
+#define HAL_MCF5272_PLIC_PnICR_B2RIE (0x01 << 1)
+#define HAL_MCF5272_PLIC_PnICR_B1RIE (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PnPSR_DTUE (0x01 << 11)
+#define HAL_MCF5272_PLIC_PnPSR_B2TUE (0x01 << 10)
+#define HAL_MCF5272_PLIC_PnPSR_B1TUE (0x01 << 9)
+#define HAL_MCF5272_PLIC_PnPSR_DROE (0x01 << 8)
+#define HAL_MCF5272_PLIC_PnPSR_B2ROE (0x01 << 7)
+#define HAL_MCF5272_PLIC_PnPSR_B1ROE (0x01 << 6)
+#define HAL_MCF5272_PLIC_PnPSR_DTDE (0x01 << 5)
+#define HAL_MCF5272_PLIC_PnPSR_B2TDE (0x01 << 4)
+#define HAL_MCF5272_PLIC_PnPSR_B1TDE (0x01 << 3)
+#define HAL_MCF5272_PLIC_PnPSR_DRDF (0x01 << 2)
+#define HAL_MCF5272_PLIC_PnPSR_B2RDE (0x01 << 1)
+#define HAL_MCF5272_PLIC_PnPSR_B1RDE (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PASR_3_MASK (0x0F << 12)
+#define HAL_MCF5272_PLIC_PASR_3_SHIFT 12
+#define HAL_MCF5272_PLIC_PASR_2_MASK (0x0F << 8)
+#define HAL_MCF5272_PLIC_PASR_2_SHIFT 8
+#define HAL_MCF5272_PLIC_PASR_1_MASK (0x0F << 4)
+#define HAL_MCF5272_PLIC_PASR_1_SHIFT 4
+#define HAL_MCF5272_PLIC_PASR_0_MASK (0x0F << 0)
+#define HAL_MCF5272_PLIC_PASR_0_SHIFT 0
+#define HAL_MCF5272_PLCI_PASR_GCRn (0x01 << 3)
+#define HAL_MCF5272_PLIC_PASR_GCTn (0x01 << 2)
+#define HAL_MCF5272_PLIC_PASR_GMRn (0x01 << 1)
+#define HAL_MCF5272_PLIC_PASR_GMTn (0x01 << 0)
+#define HAL_MCF5272_PLIC_PASR_GCR3 (0x01 << 15)
+#define HAL_MCF5272_PLIC_PASR_GCT3 (0x01 << 14)
+#define HAL_MCF5272_PLIC_PASR_GMR3 (0x01 << 13)
+#define HAL_MCF5272_PLIC_PASR_GMT3 (0x01 << 12)
+#define HAL_MCF5272_PLIC_PASR_GCR2 (0x01 << 11)
+#define HAL_MCF5272_PLIC_PASR_GCT2 (0x01 << 10)
+#define HAL_MCF5272_PLIC_PASR_GMR2 (0x01 << 9)
+#define HAL_MCF5272_PLIC_PASR_GMT2 (0x01 << 8)
+#define HAL_MCF5272_PLIC_PASR_GCR1 (0x01 << 7)
+#define HAL_MCF5272_PLIC_PASR_GCT1 (0x01 << 6)
+#define HAL_MCF5272_PLIC_PASR_GMR1 (0x01 << 5)
+#define HAL_MCF5272_PLIC_PASR_GMT1 (0x01 << 4)
+#define HAL_MCF5272_PLIC_PASR_GCR0 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PASR_GCT0 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PASR_GMR0 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PASR_GMT0 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PnGMR_EOM (0x01 << 10)
+#define HAL_MCF5272_PLIC_PnGMR_AB (0x01 << 9)
+#define HAL_MCF5272_PLIC_PnGMR_MC (0x01 << 8)
+#define HAL_MCF5272_PLIC_PnGMR_M_MASK (0x0FF << 0)
+#define HAL_MCF5272_PLIC_PnGMR_M_SHIFT 0
+
+#define HAL_MCF5272_PLIC_PnGMT_L (0x01 << 9)
+#define HAL_MCF5272_PLIC_PnGMT_R (0x01 << 8)
+#define HAL_MCF5272_PLIC_PnGMT_M_MASK (0x0FF << 0)
+#define HAL_MCF5272_PLIC_PnGMT_M_SHIFT 0
+
+#define HAL_MCF5272_PLIC_PGMTA_AR3 (0x01 << 7)
+#define HAL_MCF5272_PLIC_PGMTA_AR2 (0x01 << 6)
+#define HAL_MCF5272_PLIC_PGMTA_AR1 (0x01 << 5)
+#define HAL_MCF5272_PLIC_PGMTA_AR0 (0x01 << 4)
+
+#define HAL_MCF5272_PLIC_PGMTS_ACKn (0x01 << 4)
+#define HAL_MCF5272_PLIC_PGMTS_ABn (0x01 << 0)
+#define HAL_MCF5272_PLIC_PGMTS_3_SHIFT 3
+#define HAL_MCF5272_PLIC_PGMTS_2_SHIFT 2
+#define HAL_MCF5272_PLIC_PGMTS_1_SHIFT 1
+#define HAL_MCF5272_PLIC_PGMTS_0_SHIFT 0
+#define HAL_MCF5272_PLIC_PGMTS_ACK3 (0x01 << 7)
+#define HAL_MCF5272_PLIC_PGMTS_ACK2 (0x01 << 6)
+#define HAL_MCF5272_PLIC_PGMTS_ACK1 (0x01 << 5)
+#define HAL_MCF5272_PLIC_PGMTS_ACK0 (0x01 << 4)
+#define HAL_MCF5272_PLIC_PGMTS_AB3 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PGMTS_AB2 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PGMTS_AB1 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PGMTS_AB0 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PnGCIR_F (0x01 << 4)
+#define HAL_MCF5272_PLIC_PnGCIR_C3 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PnGCIR_C2 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PnGCIR_C1 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PnGCIR_C0 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PnGCIT_R (0x01 << 4)
+#define HAL_MCF5272_PLIC_PnGCIT_C3 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PnGCIT_C2 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PnGCIT_C1 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PnGCIT_C0 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PGCITSR_ACK3 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PGCITSR_ACK2 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PGCITSR_ACK1 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PGCITSR_ACK0 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PDCSR_DG1 (0x01 << 5)
+#define HAL_MCF5272_PLIC_PDCSR_DG0 (0x01 << 4)
+#define HAL_MCF5272_PLIC_PDCSR_DC3 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PDCSR_DC2 (0x01 << 2)
+#define HAL_MCF5272_PLIC_PDCSR_DC1 (0x01 << 1)
+#define HAL_MCF5272_PLIC_PDCSR_DC0 (0x01 << 0)
+
+#define HAL_MCF5272_PLIC_PDRQR_SHDD1 (0x01 << 11)
+#define HAL_MCF5272_PLIC_PDRQR_DCNT1 (0x01 << 10)
+#define HAL_MCF5272_PLIC_PDRQR_SHDD0 (0x01 << 9)
+#define HAL_MCF5272_PLIC_PDRQR_DCNT0 (0x01 << 8)
+#define HAL_MCF5272_PLIC_PDRQR_DRQ_MASK (0x03 << 0)
+#define HAL_MCF5272_PLIC_PDRQR_DRQ_SHIFT 0
+
+#define HAL_MCF5272_PLIC_PnSDR_FSW_MASK (0x03 << 14)
+#define HAL_MCF5272_PLIC_PnSDR_FSW_SHIFT 14
+#define HAL_MCF5272_PLIC_PnSDR_FSW_1 (0x00 << 14)
+#define HAL_MCF5272_PLIC_PnSDR_FSW_2 (0x01 << 14)
+#define HAL_MCF5272_PLIC_PnSDR_FSW_8 (0x02 << 14)
+#define HAL_MCF5272_PLIC_PnSDR_FSW_16 (0x03 << 14)
+#define HAL_MCF5272_PLIC_PnSDR_SD_MASK (0x03FF << 0)
+#define HAL_MCF5272_PLIC_PnSDR_SD_SHIFT 0
+
+#define HAL_MCF5272_PLIC_PCSR_NBP (0x01 << 15)
+#define HAL_MCF5272_PLIC_PCSR_CKI_MASK (0x03 << 6)
+#define HAL_MCF5272_PLIC_PCSR_CKI_SHIFT 6
+#define HAL_MCF5272_PLIC_PCSR_CKI_DCL0 (0x00 << 6)
+#define HAL_MCF5272_PLIC_PCSR_CKI_FSC0 (0x01 << 6)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_MASK (0x07 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_SHIFT 3
+#define HAL_MCF5272_PLIC_PCSR_FDIV_4 (0x00 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_8 (0x01 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_16 (0x02 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_32 (0x03 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_64 (0x04 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_128 (0x05 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_192 (0x06 << 3)
+#define HAL_MCF5272_PLIC_PCSR_FDIV_256 (0x07 << 3)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_MASK (0x07 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_SHIFT 0
+#define HAL_MCF5272_PLIC_PCSR_CMULT_2 (0x00 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_4 (0x01 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_8 (0x02 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_16 (0x03 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_32 (0x04 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_64 (0x05 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_128 (0x06 << 0)
+#define HAL_MCF5272_PLIC_PCSR_CMULT_256 (0x07 << 0)
+
+// ----------------------------------------------------------------------------
+// The system timers. There are four timers at different MBAR offsets
+//
+// Some of these definitions could be re-used on other xxxx processors, but
+// recent ones from the 5282 onwards have very different timer support.
+
+#define HAL_MCF5272_TIMER0_BASE 0x0200
+#define HAL_MCF5272_TIMER1_BASE 0x0220
+#define HAL_MCF5272_TIMER2_BASE 0x0240
+#define HAL_MCF5272_TIMER3_BASE 0x0260
+
+// The register offsets for each timer. All registers are 16 bits
+#define HAL_MCF5272_TIMER_TMR 0x0000
+#define HAL_MCF5272_TIMER_TRR 0x0004
+#define HAL_MCF5272_TIMER_TCR 0x0008
+#define HAL_MCF5272_TIMER_TCN 0x000C
+#define HAL_MCF5272_TIMER_TER 0x0010
+
+// The bits
+#define HAL_MCF5272_TIMER_TMR_PS_MASK 0xFF00
+#define HAL_MCF5272_TIMER_TMR_PS_SHIFT 8
+#define HAL_MCF5272_TIMER_TMR_CE_MASK (0x0003 << 6)
+// OM is only available for timers 0 and 1
+#define HAL_MCF5272_TIMER_TMR_OM (0x0001 << 5)
+#define HAL_MCF5272_TIMER_TMR_ORI (0x0001 << 4)
+#define HAL_MCF5272_TIMER_TMR_FRR (0x0001 << 3)
+#define HAL_MCF5272_TIMER_TMR_CLK_MASK (0x0003 << 1)
+#define HAL_MCF5272_TIMER_TMR_CLK_STOP (0x0000 << 1)
+#define HAL_MCF5272_TIMER_TMR_CLK_MASTER (0x0001 << 1)
+#define HAL_MCF5272_TIMER_TMR_CLK_MASTER_DIV_16 (0x0002 << 1)
+#define HAL_MCF5272_TIMER_TMR_CLK_TIN (0x0003 << 1)
+#define HAL_MCF5272_TIMER_TMR_RST (0x0001 << 0)
+
+#define HAL_MCF5272_TIMER_TER_REF (0x0001 << 1)
+#define HAL_MCF5272_TIMER_TER_CAP (0x0001 << 0)
+
+// ----------------------------------------------------------------------------
+// GPIO pins. PACNT/PBCNT/PDCNT are 32-bit. The others are 16-bit.
+
+#define HAL_MCF5272_PACNT 0x0080
+#define HAL_MCF5272_PADDR 0x0084
+#define HAL_MCF5272_PADAT 0x0086
+#define HAL_MCF5272_PBCNT 0x0088
+#define HAL_MCF5272_PBDDR 0x008C
+#define HAL_MCF5272_PBDAT 0x008E
+#define HAL_MCF5272_PCDDR 0x0094
+#define HAL_MCF5272_PCDAT 0x0096
+#define HAL_MCF5272_PDCNT 0x0098
+
+// Then the bits. The direction and data registers are only
+// relevant if the pin is controlled for GPIO, as per the
+// appropriate 2-bit entry in the control register.
+#define HAL_MCF5272_PACNT_PACNT15_MASK (0x03 << 30)
+#define HAL_MCF5272_PACNT_PACNT15_PA15 (0x00 << 30)
+#define HAL_MCF5272_PACNT_PACNT15_DGNT1 (0x01 << 30)
+#define HAL_MCF5272_PACNT_PACNT14_MASK (0x03 << 28)
+#define HAL_MCF5272_PACNT_PACNT14_PA14 (0x00 << 28)
+#define HAL_MCF5272_PACNT_PACNT14_DREQ1 (0x01 << 28)
+#define HAL_MCF5272_PACNT_PACNT13_MASK (0x03 << 26)
+#define HAL_MCF5272_PACNT_PACNT13_PA13 (0x00 << 26)
+#define HAL_MCF5272_PACNT_PACNT13_DFSC3 (0x01 << 26)
+#define HAL_MCF5272_PACNT_PACNT12_MASK (0x03 << 24)
+#define HAL_MCF5272_PACNT_PACNT12_PA12 (0x00 << 24)
+#define HAL_MCF5272_PACNT_PACNT12_DFSC2 (0x01 << 24)
+#define HAL_MCF5272_PACNT_PACNT11_MASK (0x03 << 22)
+#define HAL_MCF5272_PACNT_PACNT11_PA11 (0x00 << 22)
+#define HAL_MCF5272_PACNT_PACNT11_QSPI_CS1 (0x02 << 22)
+#define HAL_MCF5272_PACNT_PACNT10_MASK (0x03 << 20)
+#define HAL_MCF5272_PACNT_PACNT10_PA10 (0x00 << 20)
+#define HAL_MCF5272_PACNT_PACNT10_DREQ0 (0x01 << 20)
+#define HAL_MCF5272_PACNT_PACNT9_MASK (0x03 << 18)
+#define HAL_MCF5272_PACNT_PACNT9_PA9 (0x00 << 18)
+#define HAL_MCF5272_PACNT_PACNT9_DGNT0 (0x01 << 18)
+#define HAL_MCF5272_PACNT_PACNT8_MASK (0x03 << 16)
+#define HAL_MCF5272_PACNT_PACNT8_PA8 (0x00 << 16)
+#define HAL_MCF5272_PACNT_PACNT8_FSC0_FSR0 (0x01 << 16)
+#define HAL_MCF5272_PACNT_PACNT7_MASK (0x03 << 14)
+#define HAL_MCF5272_PACNT_PACNT7_PA7 (0x00 << 14)
+#define HAL_MCF5272_PACNT_PACNT7_QSPI_CS3 (0x01 << 14)
+#define HAL_MCF5272_PACNT_PACNT7_DOUT3 (0x02 << 14)
+#define HAL_MCF5272_PACNT_PACNT6_MASK (0x03 << 12)
+#define HAL_MCF5272_PACNT_PACNT6_PA6 (0x00 << 12)
+#define HAL_MCF5272_PACNT_PACNT6_USB_RXD (0x01 << 12)
+#define HAL_MCF5272_PACNT_PACNT5_MASK (0x03 << 10)
+#define HAL_MCF5272_PACNT_PACNT5_PA5 (0x00 << 10)
+#define HAL_MCF5272_PACNT_PACNT5_USB_TXEN (0x01 << 10)
+#define HAL_MCF5272_PACNT_PACNT4_MASK (0x03 << 8)
+#define HAL_MCF5272_PACNT_PACNT4_PA4 (0x00 << 8)
+#define HAL_MCF5272_PACNT_PACNT4_USB_SUSP (0x01 << 8)
+#define HAL_MCF5272_PACNT_PACNT3_MASK (0x03 << 6)
+#define HAL_MCF5272_PACNT_PACNT3_PA3 (0x00 << 6)
+#define HAL_MCF5272_PACNT_PACNT3_USB_TN (0x01 << 6)
+#define HAL_MCF5272_PACNT_PACNT2_MASK (0x03 << 4)
+#define HAL_MCF5272_PACNT_PACNT2_PA2 (0x00 << 4)
+#define HAL_MCF5272_PACNT_PACNT2_USB_RN (0x01 << 4)
+#define HAL_MCF5272_PACNT_PACNT1_MASK (0x03 << 2)
+#define HAL_MCF5272_PACNT_PACNT1_PA1 (0x00 << 2)
+#define HAL_MCF5272_PACNT_PACNT1_USB_RP (0x01 << 2)
+#define HAL_MCF5272_PACNT_PACNT0_MASK (0x03 << 0)
+#define HAL_MCF5272_PACNT_PACNT0_PA0 (0x00 << 0)
+#define HAL_MCF5272_PACNT_PACNT0_USB_TP (0x01 << 0)
+
+#define HAL_MCF5272_PBCNT_PBCNT15_MASK (0x03 << 30)
+#define HAL_MCF5272_PBCNT_PBCNT15_PB15 (0x00 << 30)
+#define HAL_MCF5272_PBCNT_PBCNT15_E_MDC (0x01 << 30)
+#define HAL_MCF5272_PBCNT_PBCNT14_MASK (0x03 << 28)
+#define HAL_MCF5272_PBCNT_PBCNT14_PB14 (0x00 << 28)
+#define HAL_MCF5272_PBCNT_PBCNT14_E_RXER (0x01 << 28)
+#define HAL_MCF5272_PBCNT_PBCNT13_MASK (0x03 << 26)
+#define HAL_MCF5272_PBCNT_PBCNT13_PB13 (0x00 << 26)
+#define HAL_MCF5272_PBCNT_PBCNT13_E_RXD1 (0x01 << 26)
+#define HAL_MCF5272_PBCNT_PBCNT12_MASK (0x03 << 24)
+#define HAL_MCF5272_PBCNT_PBCNT12_PB12 (0x00 << 24)
+#define HAL_MCF5272_PBCNT_PBCNT12_E_RXD2 (0x01 << 24)
+#define HAL_MCF5272_PBCNT_PBCNT11_MASK (0x03 << 22)
+#define HAL_MCF5272_PBCNT_PBCNT11_PB11 (0x00 << 22)
+#define HAL_MCF5272_PBCNT_PBCNT11_E_RXD3 (0x01 << 22)
+// The original user manual defined QSPI_CS for 0x02. This has
+// been removed in the errata.
+#define HAL_MCF5272_PBCNT_PBCNT10_MASK (0x03 << 20)
+#define HAL_MCF5272_PBCNT_PBCNT10_PB10 (0x00 << 20)
+#define HAL_MCF5272_PBCNT_PBCNT10_E_TXD1 (0x01 << 20)
+#define HAL_MCF5272_PBCNT_PBCNT9_MASK (0x03 << 18)
+#define HAL_MCF5272_PBCNT_PBCNT9_PB9 (0x00 << 18)
+#define HAL_MCF5272_PBCNT_PBCNT9_E_TXD2 (0x01 << 18)
+#define HAL_MCF5272_PBCNT_PBCNT8_MASK (0x03 << 16)
+#define HAL_MCF5272_PBCNT_PBCNT8_PB8 (0x00 << 16)
+#define HAL_MCF5272_PBCNT_PBCNT8_E_TXD3 (0x01 << 16)
+#define HAL_MCF5272_PBCNT_PBCNT7_MASK (0x03 << 14)
+#define HAL_MCF5272_PBCNT_PBCNT7_PB7 (0x00 << 14)
+#define HAL_MCF5272_PBCNT_PBCNT7_TOUT0 (0x01 << 14)
+#define HAL_MCF5272_PBCNT_PBCNT6_MASK (0x03 << 12)
+#define HAL_MCF5272_PBCNT_PBCNT6_PB6 (0x00 << 12)
+#define HAL_MCF5272_PBCNT_PBCNT5_MASK (0x03 << 10)
+#define HAL_MCF5272_PBCNT_PBCNT5_PB5 (0x00 << 10)
+#define HAL_MCF5272_PBCNT_PBCNT5_TA (0x01 << 10)
+#define HAL_MCF5272_PBCNT_PBCNT4_MASK (0x03 << 8)
+#define HAL_MCF5272_PBCNT_PBCNT4_PB4 (0x00 << 8)
+#define HAL_MCF5272_PBCNT_PBCNT4_URT0_CLK (0x01 << 8)
+#define HAL_MCF5272_PBCNT_PBCNT3_MASK (0x03 << 6)
+#define HAL_MCF5272_PBCNT_PBCNT3_PB3 (0x00 << 6)
+#define HAL_MCF5272_PBCNT_PBCNT3_URT0_RTS (0x01 << 6)
+#define HAL_MCF5272_PBCNT_PBCNT2_MASK (0x03 << 4)
+#define HAL_MCF5272_PBCNT_PBCNT2_PB2 (0x00 << 4)
+#define HAL_MCF5272_PBCNT_PBCNT2_URT0_CTS (0x01 << 4)
+#define HAL_MCF5272_PBCNT_PBCNT1_MASK (0x03 << 2)
+#define HAL_MCF5272_PBCNT_PBCNT1_PB1 (0x00 << 2)
+#define HAL_MCF5272_PBCNT_PBCNT1_URT0_RXD (0x01 << 2)
+#define HAL_MCF5272_PBCNT_PBCNT0_MASK (0x03 << 0)
+#define HAL_MCF5272_PBCNT_PBCNT0_PB0 (0x00 << 0)
+#define HAL_MCF5272_PBCNT_PBCNT0_URT0_TXD (0x01 << 0)
+
+#define HAL_MCF5272_PDCNT_PDCNT7_MASK (0x03 << 14)
+#define HAL_MCF5272_PDCNT_PDCNT7_HIGH (0x00 << 14)
+#define HAL_MCF5272_PDCNT_PDCNT7_PWM_OUT3 (0x01 << 14)
+#define HAL_MCF5272_PDCNT_PDCNT7_TIN1 (0x02 << 14)
+#define HAL_MCF5272_PDCNT_PDCNT6_MASK (0x03 << 12)
+#define HAL_MCF5272_PDCNT_PDCNT6_HIGH (0x00 << 12)
+#define HAL_MCF5272_PDCNT_PDCNT6_PWM_OUT2 (0x01 << 12)
+#define HAL_MCF5272_PDCNT_PDCNT6_TOUT1 (0x02 << 12)
+#define HAL_MCF5272_PDCNT_PDCNT5_MASK (0x03 << 10)
+#define HAL_MCF5272_PDCNT_PDCNT5_HIGH (0x00 << 10)
+#define HAL_MCF5272_PDCNT_PDCNT5_DIN3 (0x02 << 10)
+#define HAL_MCF5272_PDCNT_PDCNT5_INT4 (0x03 << 10)
+#define HAL_MCF5272_PDCNT_PDCNT4_MASK (0x03 << 8)
+#define HAL_MCF5272_PDCNT_PDCNT4_HIGH (0x00 << 8)
+#define HAL_MCF5272_PDCNT_PDCNT4_DOUT0 (0x01 << 8)
+#define HAL_MCF5272_PDCNT_PDCNT4_URT1_TXD (0x02 << 8)
+#define HAL_MCF5272_PDCNT_PDCNT3_MASK (0x03 << 6)
+#define HAL_MCF5272_PDCNT_PDCNT3_HIGH (0x00 << 6)
+#define HAL_MCF5272_PDCNT_PDCNT3_URT1_RTS (0x02 << 6)
+#define HAL_MCF5272_PDCNT_PDCNT3_INT5 (0x03 << 6)
+#define HAL_MCF5272_PDCNT_PDCNT2_MASK (0x03 << 4)
+#define HAL_MCF5272_PDCNT_PDCNT2_HIGH (0x00 << 4)
+#define HAL_MCF5272_PDCNT_PDCNT2_URT1_CTS (0x02 << 4)
+#define HAL_MCF5272_PDCNT_PDCNT2_QSPI_CS2 (0x03 << 4)
+#define HAL_MCF5272_PDCNT_PDCNT1_MASK (0x03 << 2)
+#define HAL_MCF5272_PDCNT_PDCNT1_HIGH (0x00 << 2)
+#define HAL_MCF5272_PDCNT_PDCNT1_DIN0 (0x01 << 2)
+#define HAL_MCF5272_PDCNT_PDCNT1_URT1_RXD (0x02 << 2)
+#define HAL_MCF5272_PDCNT_PDCNT0_MASK (0x03 << 0)
+#define HAL_MCF5272_PDCNT_PDCNT0_HIGH (0x00 << 0)
+#define HAL_MCF5272_PDCNT_PDCNT0_DCL0 (0x01 << 0)
+#define HAL_MCF5272_PDCNT_PDCNT0_URT1_CLK (0x02 << 0)
+
+// ----------------------------------------------------------------------------
+// PWM: six 8-bit registers, in three pairs
+#define HAL_MCF5272_PWCR0 0x00C0
+#define HAL_MCF5272_PWCR1 0x00C4
+#define HAL_MCF5272_PWCR2 0x00C8
+#define HAL_MCF5272_PWWD0 0x00D0
+#define HAL_MCF5272_PWWD1 0x00D4
+#define HAL_MCF5272_PWWD2 0x00D8
+
+#define HAL_MCF5272_PWCR_EN (0x01 << 7)
+#define HAL_MCF5272_PWCR_FRC1 (0x01 << 6)
+#define HAL_MCF5272_PWCR_LVL (0x01 << 5)
+#define HAL_MCF5272_PWCR_CKSL_MASK (0x0F << 0)
+#define HAL_MCF5272_PWCR_CKSL_SHIFT 0
+#define HAL_MCF5272_PWCR_CKSL_1 (0x00 << 0)
+#define HAL_MCF5272_PWCR_CKSL_2 (0x01 << 0)
+#define HAL_MCF5272_PWCR_CKSL_4 (0x02 << 0)
+#define HAL_MCF5272_PWCR_CKSL_8 (0x03 << 0)
+#define HAL_MCF5272_PWCR_CKSL_16 (0x04 << 0)
+#define HAL_MCF5272_PWCR_CKSL_32 (0x05 << 0)
+#define HAL_MCF5272_PWCR_CKSL_64 (0x06 << 0)
+#define HAL_MCF5272_PWCR_CKSL_128 (0x07 << 0)
+#define HAL_MCF5272_PWCR_CKSL_256 (0x08 << 0)
+#define HAL_MCF5272_PWCR_CKSL_512 (0x09 << 0)
+#define HAL_MCF5272_PWCR_CKSL_1024 (0x0A << 0)
+#define HAL_MCF5272_PWCR_CKSL_2048 (0x0B << 0)
+#define HAL_MCF5272_PWCR_CKSL_4096 (0x0C << 0)
+#define HAL_MCF5272_PWCR_CKSL_8192 (0x0D << 0)
+#define HAL_MCF5272_PWCR_CKSL_16384 (0x0E << 0)
+#define HAL_MCF5272_PWCR_CKSL_32768 (0x0F << 0)
+
+// ----------------------------------------------------------------------------
+// Now allow platform-specific overrides and additions
+#include <cyg/hal/plf_io.h>
+
+#ifndef HAL_MCFxxxx_MBAR
+# define HAL_MCFxxxx_MBAR 0x10000000
+#endif
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PROC_IO_H_FIRST_SECOND
Index: include/proc_startup.h
===================================================================
RCS file: include/proc_startup.h
diff -N include/proc_startup.h
--- include/proc_startup.h 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,49 +0,0 @@
-#ifndef _PROC_STARTUP_H
-#define _PROC_STARTUP_H
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-
-#include <cyg/infra/cyg_type.h>
-
-// Include the platform-specific startup header.
-
-#include <cyg/hal/plf_startup.h>
-
-// Processor-specific reset vector initialization routine
-
-externC void proc_reset(void);
-
-#endif // _PROC_STARTUP_H
-
Index: src/gpio.c
===================================================================
RCS file: src/gpio.c
diff -N src/gpio.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ src/gpio.c 20 Nov 2008 22:49:11 -0000
@@ -0,0 +1,959 @@
+//==========================================================================
+//
+// gpio.c
+//
+// MCF5272 GPIO support
+//
+//==========================================================================
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003,2004,2005,2006,2008 Free Software Foundation, Inc.
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2006-09-05
+//
+//####DESCRIPTIONEND####
+//=============================================================================
+
+// This file is just #include'd by the main mcf5272.c file. It serves
+// to keep all the GPIO definitions in a separate file. GPIO
+// initialization is all handled by configury, thus minimizing the
+// amount of work explicitly needed in application code.
+
+#define A0_DAT 1
+#define A1_DAT 1
+#define A2_DAT 1
+#define A3_DAT 1
+#define A4_DAT 1
+#define A5_DAT 1
+#define A6_DAT 1
+#define A7_DAT 1
+#define A8_DAT 1
+#define A9_DAT 1
+#define A10_DAT 1
+#define A11_DAT 1
+#define A12_DAT 1
+#define A13_DAT 1
+#define A14_DAT 1
+#define A15_DAT 1
+
+#define A0_DDR 0
+#define A1_DDR 0
+#define A2_DDR 0
+#define A3_DDR 0
+#define A4_DDR 0
+#define A5_DDR 0
+#define A6_DDR 0
+#define A7_DDR 0
+#define A8_DDR 0
+#define A9_DDR 0
+#define A10_DDR 0
+#define A11_DDR 0
+#define A12_DDR 0
+#define A13_DDR 0
+#define A14_DDR 0
+#define A15_DDR 0
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_usb_tp)
+# define A0_PAR 1
+#else
+# define A0_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_in)
+# undef A0_DDR
+# define A0_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_out0)
+# undef A0_DAT
+# define A0_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA0_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_usb_rp)
+# define A1_PAR 1
+#else
+# define A1_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_in)
+# undef A1_DDR
+# define A1_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_out0)
+# undef A1_DAT
+# define A1_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA1_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_usb_rn)
+# define A2_PAR 1
+#else
+# define A2_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_in)
+# undef A2_DDR
+# define A2_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_out0)
+# undef A2_DAT
+# define A2_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA2_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_usb_tn)
+# define A3_PAR 1
+#else
+# define A3_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_in)
+# undef A3_DDR
+# define A3_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_out0)
+# undef A3_DAT
+# define A3_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA3_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_usb_susp)
+# define A4_PAR 1
+#else
+# define A4_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_in)
+# undef A4_DDR
+# define A4_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_out0)
+# undef A4_DAT
+# define A4_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA4_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_usb_txen)
+# define A5_PAR 1
+#else
+# define A5_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_in)
+# undef A5_DDR
+# define A5_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_out0)
+# undef A5_DAT
+# define A5_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA5_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_usb_rxd)
+# define A6_PAR 1
+#else
+# define A6_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_in)
+# undef A6_DDR
+# define A6_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_out0)
+# undef A6_DAT
+# define A6_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA6_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_qspi_cs3)
+# define A7_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_dout3)
+# define A7_PAR 2
+#else
+# define A7_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_in)
+# undef A7_DDR
+# define A7_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_out0)
+# undef A7_DAT
+# define A7_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA7_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_fsc0_fsr0)
+# define A8_PAR 1
+#else
+# define A8_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_in)
+# undef A8_DDR
+# define A8_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_out0)
+# undef A8_DAT
+# define A8_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA8_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_dgnt0)
+# define A9_PAR 1
+#else
+# define A9_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_in)
+# undef A9_DDR
+# define A9_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_out0)
+# undef A9_DAT
+# define A9_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA9_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_dreq0)
+# define A10_PAR 1
+#else
+# define A10_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_in)
+# undef A10_DDR
+# define A10_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_out0)
+# undef A10_DAT
+# define A10_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA10_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_qspi_cs1)
+# define A11_PAR 2
+#else
+# define A11_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_in)
+# undef A11_DDR
+# define A11_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_out0)
+# undef A11_DAT
+# define A11_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA11_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_dfsc2)
+# define A12_PAR 1
+#else
+# define A12_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_in)
+# undef A12_DDR
+# define A12_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_out0)
+# undef A12_DAT
+# define A12_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA12_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_dfsc3)
+# define A13_PAR 1
+#else
+# define A13_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_in)
+# undef A13_DDR
+# define A13_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_out0)
+# undef A13_DAT
+# define A13_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA13_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_dreq1)
+# define A14_PAR 1
+#else
+# define A14_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_in)
+# undef A14_DDR
+# define A14_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_out0)
+# undef A14_DAT
+# define A14_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA14_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_dgnt1)
+# define A15_PAR 1
+#else
+# define A15_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_in)
+# undef A15_DDR
+# define A15_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_out0)
+# undef A15_DAT
+# define A15_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTA_PA15_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#define A_DAT ((A0_DAT << 0) | (A1_DAT << 1) | (A2_DAT << 2) | (A3_DAT << 3) | \
+ (A4_DAT << 4) | (A5_DAT << 5) | (A6_DAT << 6) | (A7_DAT << 7) | \
+ (A8_DAT << 8) | (A9_DAT << 9) | (A10_DAT << 10) | (A11_DAT << 11) | \
+ (A12_DAT << 12) | (A13_DAT << 13) | (A14_DAT << 14) | (A15_DAT << 15))
+#define A_DDR ((A0_DDR << 0) | (A1_DDR << 1) | (A2_DDR << 2) | (A3_DDR << 3) | \
+ (A4_DDR << 4) | (A5_DDR << 5) | (A6_DDR << 6) | (A7_DDR << 7) | \
+ (A8_DDR << 8) | (A9_DDR << 9) | (A10_DDR << 10) | (A11_DDR << 11) | \
+ (A12_DDR << 12) | (A13_DDR << 13) | (A14_DDR << 14) | (A15_DDR << 15))
+#define A_PAR ((A0_PAR << 0) | (A1_PAR << 2) | (A2_PAR << 4) | (A3_PAR << 6) | \
+ (A4_PAR << 8) | (A5_PAR << 10) | (A6_PAR << 12) | (A7_PAR << 14) | \
+ (A8_PAR << 16) | (A9_PAR << 18) | (A10_PAR << 20) | (A11_PAR << 22) | \
+ (A12_PAR << 24) | (A13_PAR << 26) | (A14_PAR << 28) | (A15_PAR << 30))
+
+// ----------------------------------------------------------------------------
+#define B0_DAT 1
+#define B1_DAT 1
+#define B2_DAT 1
+#define B3_DAT 1
+#define B4_DAT 1
+#define B5_DAT 1
+#define B6_DAT 1
+#define B7_DAT 1
+#define B8_DAT 1
+#define B9_DAT 1
+#define B10_DAT 1
+#define B11_DAT 1
+#define B12_DAT 1
+#define B13_DAT 1
+#define B14_DAT 1
+#define B15_DAT 1
+
+#define B0_DDR 0
+#define B1_DDR 0
+#define B2_DDR 0
+#define B3_DDR 0
+#define B4_DDR 0
+#define B5_DDR 0
+#define B6_DDR 0
+#define B7_DDR 0
+#define B8_DDR 0
+#define B9_DDR 0
+#define B10_DDR 0
+#define B11_DDR 0
+#define B12_DDR 0
+#define B13_DDR 0
+#define B14_DDR 0
+#define B15_DDR 0
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_txd0)
+# define B0_PAR 1
+#else
+# define B0_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_in)
+# undef B0_DDR
+# define B0_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_out0)
+# undef B0_DAT
+# define B0_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_rxd0)
+# define B1_PAR 1
+#else
+# define B1_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_in)
+# undef B1_DDR
+# define B1_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_out0)
+# undef B1_DAT
+# define B1_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_cts0)
+# define B2_PAR 1
+#else
+# define B2_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_in)
+# undef B2_DDR
+# define B2_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_out0)
+# undef B2_DAT
+# define B2_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_rts0)
+# define B3_PAR 1
+#else
+# define B3_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_in)
+# undef B3_DDR
+# define B3_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_out0)
+# undef B3_DAT
+# define B3_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_clk0)
+# define B4_PAR 1
+#else
+# define B4_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_in)
+# undef B4_DDR
+# define B4_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_out0)
+# undef B4_DAT
+# define B4_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB4_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_ta)
+# define B5_PAR 1
+#else
+# define B5_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_in)
+# undef B5_DDR
+# define B5_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_out0)
+# undef B5_DAT
+# define B5_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB5_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+# define B6_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6_in)
+# undef B6_DDR
+# define B6_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6_out0)
+# undef B6_DAT
+# define B6_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB6_out1)
+# error GPIO data mismatch
+# endif
+# endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_tout0)
+# define B7_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_dout3)
+# define B7_PAR 2
+#else
+# define B7_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_in)
+# undef B7_DDR
+# define B7_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_out0)
+# undef B7_DAT
+# define B7_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB7_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_etxd3)
+# define B8_PAR 1
+#else
+# define B8_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_in)
+# undef B8_DDR
+# define B8_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_out0)
+# undef B8_DAT
+# define B8_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB8_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_etxd2)
+# define B9_PAR 1
+#else
+# define B9_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_in)
+# undef B9_DDR
+# define B9_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_out0)
+# undef B9_DAT
+# define B9_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB9_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_etxd1)
+# define B10_PAR 1
+#else
+# define B10_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_in)
+# undef B10_DDR
+# define B10_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_out0)
+# undef B10_DAT
+# define B10_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB10_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_erxd3)
+# define B11_PAR 1
+#else
+# define B11_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_in)
+# undef B11_DDR
+# define B11_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_out0)
+# undef B11_DAT
+# define B11_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB11_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_erxd2)
+# define B12_PAR 1
+#else
+# define B12_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_in)
+# undef B12_DDR
+# define B12_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_out0)
+# undef B12_DAT
+# define B12_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB12_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_erxd1)
+# define B13_PAR 1
+#else
+# define B13_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_in)
+# undef B13_DDR
+# define B13_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_out0)
+# undef B13_DAT
+# define B13_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB13_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_erxer)
+# define B14_PAR 1
+#else
+# define B14_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_in)
+# undef B14_DDR
+# define B14_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_out0)
+# undef B14_DAT
+# define B14_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB14_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_e_mdc)
+# define B15_PAR 1
+#else
+# define B15_PAR 0
+# if !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_in)
+# undef B15_DDR
+# define B15_DDR 1
+# if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_out0)
+# undef B15_DAT
+# define B15_DAT 0
+# elif !defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB15_out1)
+# error GPIO data mismatch
+# endif
+# endif
+#endif
+
+#define B_DAT ((B0_DAT << 0) | (B1_DAT << 1) | (B2_DAT << 2) | (B3_DAT << 3) | \
+ (B4_DAT << 4) | (B5_DAT << 5) | (B6_DAT << 6) | (B7_DAT << 7) | \
+ (B8_DAT << 8) | (B9_DAT << 9) | (B10_DAT << 10) | (B11_DAT << 11) | \
+ (B12_DAT << 12) | (B13_DAT << 13) | (B14_DAT << 14) | (B15_DAT << 15))
+#define B_DDR ((B0_DDR << 0) | (B1_DDR << 1) | (B2_DDR << 2) | (B3_DDR << 3) | \
+ (B4_DDR << 4) | (B5_DDR << 5) | (B6_DDR << 6) | (B7_DDR << 7) | \
+ (B8_DDR << 8) | (B9_DDR << 9) | (B10_DDR << 10) | (B11_DDR << 11) | \
+ (B12_DDR << 12) | (B13_DDR << 13) | (B14_DDR << 14) | (B15_DDR << 15))
+#define B_PAR ((B0_PAR << 0) | (B1_PAR << 2) | (B2_PAR << 4) | (B3_PAR << 6) | \
+ (B4_PAR << 8) | (B5_PAR << 10) | (B6_PAR << 12) | (B7_PAR << 14) | \
+ (B8_PAR << 16) | (B9_PAR << 18) | (B10_PAR << 20) | (B11_PAR << 22) | \
+ (B12_PAR << 24) | (B13_PAR << 26) | (B14_PAR << 28) | (B15_PAR << 30))
+
+// ----------------------------------------------------------------------------
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_in)
+# define C0_DDR 0
+# define C0_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_out0)
+# define C0_DDR 1
+# define C0_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_out1)
+# define C0_DDR 1
+# define C0_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC1_in)
+# define C1_DDR 0
+# define C1_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC1_out0)
+# define C1_DDR 1
+# define C1_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC1_out1)
+# define C1_DDR 1
+# define C1_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC2_in)
+# define C2_DDR 0
+# define C2_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC2_out0)
+# define C2_DDR 1
+# define C2_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC2_out1)
+# define C2_DDR 1
+# define C2_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC3_in)
+# define C3_DDR 0
+# define C3_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC3_out0)
+# define C3_DDR 1
+# define C3_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC3_out1)
+# define C3_DDR 1
+# define C3_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC4_in)
+# define C4_DDR 0
+# define C4_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC4_out0)
+# define C4_DDR 1
+# define C4_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC4_out1)
+# define C4_DDR 1
+# define C4_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC5_in)
+# define C5_DDR 0
+# define C5_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC5_out0)
+# define C5_DDR 1
+# define C5_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC5_out1)
+# define C5_DDR 1
+# define C5_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC6_in)
+# define C6_DDR 0
+# define C6_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC6_out0)
+# define C6_DDR 1
+# define C6_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC6_out1)
+# define C6_DDR 1
+# define C6_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC7_in)
+# define C7_DDR 0
+# define C7_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC7_out0)
+# define C7_DDR 1
+# define C7_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC7_out1)
+# define C7_DDR 1
+# define C7_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC8_in)
+# define C8_DDR 0
+# define C8_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC8_out0)
+# define C8_DDR 1
+# define C8_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC8_out1)
+# define C8_DDR 1
+# define C8_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC9_in)
+# define C9_DDR 0
+# define C9_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC9_out0)
+# define C9_DDR 1
+# define C9_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC9_out1)
+# define C9_DDR 1
+# define C9_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC10_in)
+# define C10_DDR 0
+# define C10_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC10_out0)
+# define C10_DDR 1
+# define C10_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC10_out1)
+# define C10_DDR 1
+# define C10_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC11_in)
+# define C11_DDR 0
+# define C11_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC11_out0)
+# define C11_DDR 1
+# define C11_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC11_out1)
+# define C11_DDR 1
+# define C11_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC12_in)
+# define C12_DDR 0
+# define C12_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC12_out0)
+# define C12_DDR 1
+# define C12_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC12_out1)
+# define C12_DDR 1
+# define C12_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC13_in)
+# define C13_DDR 0
+# define C13_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC13_out0)
+# define C13_DDR 1
+# define C13_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC13_out1)
+# define C13_DDR 1
+# define C13_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC14_in)
+# define C14_DDR 0
+# define C14_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC14_out0)
+# define C14_DDR 1
+# define C14_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC14_out1)
+# define C14_DDR 1
+# define C14_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC15_in)
+# define C15_DDR 0
+# define C15_DAT 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC15_out0)
+# define C15_DDR 1
+# define C15_DAT 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTC_PC0_out1)
+# define C15_DDR 1
+# define C15_DAT 1
+#else
+# error GPIO data mismatch
+#endif
+
+#define C_DAT ((C0_DAT << 0) | (C1_DAT << 1) | (C2_DAT << 2) | (C3_DAT << 3) | \
+ (C4_DAT << 4) | (C5_DAT << 5) | (C6_DAT << 6) | (C7_DAT << 7) | \
+ (C8_DAT << 8) | (C9_DAT << 9) | (C10_DAT << 10) | (C11_DAT << 11) | \
+ (C12_DAT << 12) | (C13_DAT << 13) | (C14_DAT << 14) | (C15_DAT << 15))
+#define C_DDR ((C0_DDR << 0) | (C1_DDR << 1) | (C2_DDR << 2) | (C3_DDR << 3) | \
+ (C4_DDR << 4) | (C5_DDR << 5) | (C6_DDR << 6) | (C7_DDR << 7) | \
+ (C8_DDR << 8) | (C9_DDR << 9) | (C10_DDR << 10) | (C11_DDR << 11) | \
+ (C12_DDR << 12) | (C13_DDR << 13) | (C14_DDR << 14) | (C15_DDR << 15))
+
+// ----------------------------------------------------------------------------
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0_none)
+# define D0_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0_dcl0)
+# define D0_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD0_clk1)
+# define D0_PAR 2
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1_none)
+# define D1_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1_din0)
+# define D1_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1_rxd1)
+# define D1_PAR 2
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2_none)
+# define D2_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2_cts1)
+# define D2_PAR 2
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2_qspi_cs2)
+# define D2_PAR 3
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3_none)
+# define D3_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3_rts1)
+# define D3_PAR 2
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3_int5)
+# define D3_PAR 3
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4_none)
+# define D4_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4_dout0)
+# define D4_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4_txd1)
+# define D4_PAR 2
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5_none)
+# define D5_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5_din3)
+# define D5_PAR 2
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD5_int4)
+# define D5_PAR 3
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6_none)
+# define D6_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6_pwm_out1)
+# define D6_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD6_tout1)
+# define D6_PAR 2
+#else
+# error GPIO data mismatch
+#endif
+
+#if defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7_none)
+# define D7_PAR 0
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7_pwm_out2)
+# define D7_PAR 1
+#elif defined(CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD7_tin1)
+# define D7_PAR 2
+#else
+# error GPIO data mismatch
+#endif
+
+#define D_PAR ((D0_PAR << 0) | (D1_PAR << 2) | (D2_PAR << 4) | (D3_PAR << 6) | \
+ (D4_PAR << 8) | (D5_PAR << 10) | (D6_PAR << 12) | (D7_PAR << 14))
Index: src/mcf5272.c
===================================================================
RCS file: src/mcf5272.c
diff -N src/mcf5272.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ src/mcf5272.c 20 Nov 2008 22:49:11 -0000
@@ -0,0 +1,192 @@
+//==========================================================================
+//
+// mcf5272.c
+//
+// MCF5272 processor support functions.
+//
+//==========================================================================
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003,2004,2005,2006,2008 Free Software Foundation, Inc.
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2003-06-04
+//
+//####DESCRIPTIONEND####
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_m68k.h>
+#include <pkgconf/hal_m68k_mcfxxxx.h>
+#include <pkgconf/hal_m68k_mcf5272.h>
+#include CYGBLD_HAL_PLATFORM_H
+#include <cyg/hal/hal_intr.h>
+#include <cyg/infra/cyg_type.h>
+
+#ifdef CYGHWR_HAL_M68K_MCF5272_GPIO
+# include "gpio.c"
+#endif
+
+// ----------------------------------------------------------------------------
+// Processor initialization.
+void
+hal_m68k_mcf5272_init(void)
+{
+ int i;
+
+ hal_mcf5272_cacr = CYGNUM_HAL_M68K_MCF5272_CACR;
+
+#ifdef CYGNUM_HAL_M68K_MCF5272_SCR
+ // SCR. This is configurable since applications may want different
+ // bus arbitration schemes. The #ifdef is for backwards compatibility.
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_SCR, CYGNUM_HAL_M68K_MCF5272_SCR);
+#endif
+
+ // Set up the GPIO pins if the platform HAL defines the appropriate settings.
+#ifdef CYGHWR_HAL_M68K_MCF5272_GPIO
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PADAT, A_DAT);
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PADDR, A_DDR);
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PACNT, A_PAR);
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBDAT, B_DAT);
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBDDR, B_DDR);
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBCNT, B_PAR);
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PCDAT, C_DAT);
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PCDDR, C_DDR);
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PDCNT, D_PAR);
+#endif
+
+ // Enable all exceptions.
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_SPR, 0x00FF);
+
+ // If we should enter low power mode when idling, set the PMR here.
+ // Application programs may tweak it as required.
+#if defined(CYGIMP_HAL_M68K_MCF5272_IDLE_run)
+ // Leave PMR to its default
+#elif defined(CYGIMP_HAL_M68K_MCF5272_IDLE_sleep)
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PMR, HAL_MCF5272_PMR_SLPEN);
+#elif defined(CYGIMP_HAL_M68K_MCF5272_IDLE_stop)
+ HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PMR, HAL_MCF5272_PMR_MOS);
+#else
+# error Unknown low power mode
+#endif
+
+ // Make sure that the interrupt controller matches the proc_intr.h
+ // vector definitions.
+ HAL_WRITE_UINT8( HAL_MCFxxxx_MBAR + HAL_MCF5272_PIVR, HAL_MCF5272_INT_VEC_BASE);
+
+ // The interrupt controller. All interrupts are set to priority 0,
+ // disabled until configured. This cannot be done when running on
+ // top of RedBoot, it would interfere with any devices in use for
+ // communication e.g. ethernet.
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
+ for (i = 0; i < 4; i++) {
+ hal_mcf5272_icr_pri_mirror[i] = 0x0;
+ }
+#endif
+
+ // Exception vectors. First the exceptions themselves. If running
+ // with a ROM monitor then leave these alone, otherwise claim the
+ // lot.
+#ifndef CYGSEM_HAL_USE_ROM_MONITOR
+ HAL_VSR_SET(CYGNUM_HAL_VECTOR_SSP, (void*) 0, (void*) 0);
+ HAL_VSR_SET(CYGNUM_HAL_VECTOR_RESET, &hal_m68k_exception_reset, (void*) 0);
+
+ for (i = CYGNUM_HAL_VECTOR_BUSERR; i < CYGNUM_HAL_VECTOR_SPURINT; i++) {
+ HAL_VSR_SET(i, &hal_m68k_exception_vsr, (void*) 0);
+ }
+ for (i = CYGNUM_HAL_VECTOR_TRAP0; i <= CYGNUM_HAL_VECTOR_TRAPLAST; i++) {
+ HAL_VSR_SET(i, &hal_m68k_exception_vsr, (void*) 0);
+ }
+#endif
+
+ // All the external interrupts can be handled by the same VSR, the default
+ // architectural one.
+ for (i = HAL_MCF5272_INT_VEC_BASE; i < CYGNUM_HAL_VECTOR_RES1; i++) {
+ HAL_VSR_SET(i, &hal_m68k_interrupt_vsr, (void*) 0);
+ }
+}
+
+// ----------------------------------------------------------------------------
+// Profiling support. This requires a hardware timer set to interrupt at
+// a rate determined by application code. The interrupt handler should
+// call __profile_hit() with a single argument, the interrupted PC.
+// Timer 2 is used to implement the profiling timer. Timer 3 is already
+// allocated for the system clock. Timers 0 and 1 have some extra
+// functionality so these are left for application code.
+//
+// Usually this would involve installing an ISR. However there is no
+// easy way for an ISR to get hold of the interrupted PC. In some
+// configurations the save state will be stored in hal_saved_interrupt_state,
+// but not always. It might be possible to extract the PC from the stack,
+// but that gets messy if a separate interrupt stack is used and would be
+// vulnerable to changes in the architectural VSR. Instead a custom VSR
+// is installed.
+
+#ifdef CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER
+
+extern void hal_mcf5272_profile_vsr(void);
+
+# include <cyg/profile/profile.h>
+
+int
+hal_enable_profile_timer(int resolution)
+{
+ // Reset the timer
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TMR, 0);
+
+ // The resolution is a time interval in microseconds. The clock is
+ // set to tick in microseconds by dividing by the system clock
+ // value.
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TRR,
+ resolution - 1);
+
+ // Timer captures are of no interest, but reset them just in case.
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TCN, 0);
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TER,
+ HAL_MCF5272_TIMER_TER_REF | HAL_MCF5272_TIMER_TER_CAP);
+
+ // Set up the interrupt handler. This is a high-priority interrupt
+ // so that we can get profiling information for other interrupt
+ // sources.
+ HAL_VSR_SET(CYGNUM_HAL_VECTOR_TMR2, &hal_mcf5272_profile_vsr, (cyg_uint32)0);
+ HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_ISR_TMR2, 6);
+ HAL_INTERRUPT_UNMASK(CYGNUM_HAL_ISR_TMR2);
+
+ // Now start the timer running.
+ HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TMR,
+ ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ - 1) << HAL_MCF5272_TIMER_TMR_PS_SHIFT) |
+ HAL_MCF5272_TIMER_TMR_ORI | HAL_MCF5272_TIMER_TMR_FRR |
+ HAL_MCF5272_TIMER_TMR_CLK_MASTER | HAL_MCF5272_TIMER_TMR_RST);
+
+ // The desired resolution is always supported
+ return resolution;
+}
+#endif
Index: src/mcf5272_profile.S
===================================================================
RCS file: src/mcf5272_profile.S
diff -N src/mcf5272_profile.S
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ src/mcf5272_profile.S 20 Nov 2008 22:49:11 -0000
@@ -0,0 +1,78 @@
+// #========================================================================
+// #
+// # mcf5272_profile.S
+// #
+// # Support for gprof-style profiling on an mcf5272
+// #
+// #========================================================================
+//=============================================================================
+//###ECOSGPLCOPYRIGHTBEGIN####
+//-------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003,2006,2008 Free Software Foundation, Inc.
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//============================================================================
+//###DESCRIPTIONBEGIN####
+//
+// Author(s): bartv
+// Date: 2003-09-01
+//
+//###DESCRIPTIONEND####
+//========================================================================
+
+#include <cyg/hal/arch.inc>
+#include <cyg/hal/var_io.h>
+
+ .file "mcf5272_profile.S"
+
+ // This VSR should call __profile_hit() with a single argument,
+ // the interrupted PC. The VSR has been installed as a
+ // high-priority interrupt source, so there is no need to worry
+ // about nested interrupts or an interrupt stack.
+ .extern __profile_hit
+
+ FUNC_START(hal_mcf5272_profile_vsr)
+ // On entry sp[0] holds sr and sp[1] holds the pc.
+ // Save the caller-save integer registers. There are no floating
+ // point registers to worry about. Make space for the argument
+ // to __profile_hit() while we are at it.
+ sub.l #20, %sp
+ movem.l %d0-%d1/%a0-%a1, 4(%sp)
+
+ // Now pick up the interrupted PC from its new offset and push it
+ // on the stack for __profile_hit().
+ move.l 24(%sp),(%sp)
+ jbsr __profile_hit
+
+ // The timer runs in restart mode, but the interrupt bit has to be reset.
+ moveq.l # HAL_MCF5272_TIMER_TER_REF, %d0
+ move.w %d0, HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TER
+
+ movem.l 4(%sp), %d0-%d1/%a0-%a1
+ add.l #20, %sp
+ rte
+
+ .end
Index: src/memcpy.c
===================================================================
RCS file: src/memcpy.c
diff -N src/memcpy.c
--- src/memcpy.c 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,123 +0,0 @@
-//==========================================================================
-//
-// memcpy.c
-//
-// memcpy() routine for coldfire
-//
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-
-/* INCLUDES */
-
-#include <cyg/infra/cyg_type.h> /* Common type definitions */
-#include <stddef.h> /* Compiler defns such as size_t, NULL etc. */
-
-/* EXPORTED SYMBOLS */
-
-externC void *
-memcpy( void * s1, const void * s2, size_t n ) __attribute__((alias("_memcpy")));
-
-/* FUNCTIONS */
-
-void *
-_memcpy( void * s1, const void * s2, size_t n )
-{
- char * dst = (char *) s1;
- const char * src = (const char *) s2;
- long longwords;
- int_t rem_bytes;
- int_t loops;
- int_t loop_index;
-
- /* Don't worry about alignment on the coldfire. Most large */
- /* structures should be aligned anyway. */
-
- longwords = (long)(n / 4);
- rem_bytes = n % 4;
- loops = (int_t)(longwords / 32);
- loop_index = (int_t)(longwords % 32);
-
- switch (loop_index)
- {
- do
- {
- *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 31: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 30: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 29: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 28: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 27: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 26: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 25: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 24: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 23: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 22: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 21: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 20: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 19: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 18: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 17: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 16: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 15: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 14: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 13: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 12: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 11: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 10: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 9: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 8: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 7: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 6: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 5: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 4: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 3: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 2: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 1: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
- case 0: ; /* Keep compiler from complaining. */
- } while (--loops >= 0);
- }
-
- /* Clean up the remaining bytes. */
-
- while (--rem_bytes >= 0)
- {
- *dst++ = *src++;
- }
-
- return s1;
-
-} /* _memcpy() */
-
-/* EOF memcpy.c */
Index: src/proc_arch.S
===================================================================
RCS file: src/proc_arch.S
diff -N src/proc_arch.S
--- src/proc_arch.S 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,68 +0,0 @@
-##=============================================================================
-##
-## proc_arch.S
-##
-## mcf5272 processor code
-##
-##=============================================================================
-##=============================================================================
-#####ECOSGPLCOPYRIGHTBEGIN####
-## -------------------------------------------
-## This file is part of eCos, the Embedded Configurable Operating System.
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-##
-## eCos is free software; you can redistribute it and/or modify it under
-## the terms of the GNU General Public License as published by the Free
-## Software Foundation; either version 2 or (at your option) any later version.
-##
-## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-## WARRANTY; without even the implied warranty of MERCHANTABILITY or
-## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-## for more details.
-##
-## You should have received a copy of the GNU General Public License along
-## with eCos; if not, write to the Free Software Foundation, Inc.,
-## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-##
-## As a special exception, if other files instantiate templates or use macros
-## or inline functions from this file, or you compile this file and link it
-## with other works to produce a work based on this file, this file does not
-## by itself cause the resulting work to be covered by the GNU General Public
-## License. However the source code for this file must still be made available
-## in accordance with section (3) of the GNU General Public License.
-##
-## This exception does not invalidate any other reasons why a work based on
-## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
-## -------------------------------------------
-#####ECOSGPLCOPYRIGHTEND####
-##=============================================================================
-
-#include <pkgconf/hal.h>
-
-#------------------------------------------------------------------------------
-# function declaration macro
-
-#define FUNC_START(name) \
- .text; \
- .even; \
- .globl name; \
-name:
-
-/* ************************************************************************ */
-/* These routines write to the special purpose registers in the ColdFire */
-/* core. Since these registers are write-only in the supervisor model, no */
-/* corresponding read routines exist. */
-
-FUNC_START(mcf5272_wr_mbar)
- move.l 4(%sp),%d0
- movec %d0,%mbar
- nop
- rts
-
-##=============================================================================
-##=============================================================================
-
-
Index: src/proc_misc.c
===================================================================
RCS file: src/proc_misc.c
diff -N src/proc_misc.c
--- src/proc_misc.c 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,62 +0,0 @@
-//==========================================================================
-//
-// proc_misc.c
-//
-// HAL implementation miscellaneous functions
-//
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-
-#include <pkgconf/hal.h>
-#include <cyg/infra/cyg_type.h>
-
-#include <cyg/hal/proc_arch.h>
-#include <cyg/hal/hal_memmap.h>
-
-// Define the global pointer to the SIM registers.
-
-volatile mcf5272_sim_t * const mcf5272_sim_p = (mcf5272_sim_t *)MCF5272_MBAR;
-
-// Define a mirror copy of the interrupt control registers used to set
-// interrupt priorities. In order to mask and unmask a specific interrupt, we
-// must be able to set its priority to zero and then restore it to ist
-// original priority. We use these locations to determine the level to
-// restore the interrupt to in the unmask macro.
-
-cyg_uint32 hal_icr_pri_mirror[4];
-
-//--------------------------------------------------------------------------
-// End of var_misc.c
-
Index: src/proc_startup.c
===================================================================
RCS file: src/proc_startup.c
diff -N src/proc_startup.c
--- src/proc_startup.c 29 May 2002 18:28:16 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,90 +0,0 @@
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-
-#include <cyg/infra/cyg_type.h>
-#include <pkgconf/hal.h>
-#include <cyg/hal/hal_startup.h>
-#include <cyg/hal/hal_memmap.h>
-#include <cyg/hal/hal_arch.h>
-#include <cyg/hal/hal_intr.h>
-
-/*****************************************************************************
-proc_reset -- Processor-specific reset vector initialization routine
-
- This routine must be called with interrupts disabled.
-
-INPUT:
-
-OUTPUT:
-
-RETURN VALUE:
-
- None
-
-*****************************************************************************/
-void proc_reset(void)
-{
- int i;
-
- // Set up the mapping of our internal registers. The LSB indicates that
- // the registers are valid.
-
- mcf5272_wr_mbar((CYG_WORD32)(MCF5272_MBAR | 1));
-
- // Initialize the vector base register in the interrupt controller.
-
- MCF5272_SIM->intc.ipvr = HAL_PROG_INT_VEC_BASE;
-
- // Initialize the interrupt control register and the icr priority
- // mirror. Disable all interrupts by setting all priorities to zero.
-
- for (i=0; i < 4; i++)
- {
- MCF5272_SIM->intc.icr[i] = hal_icr_pri_mirror[i] = 0x88888888;
- }
-
- // Enable/disable the data transfter acknowledge output pin.
-
- MCF5272_SIM->gpio.pbcnt = ((MCF5272_SIM->gpio.pbcnt &
- ~(MCF5272_GPIO_PBCNT_TA_MSK)) |
- ((HAL_MCF5272_ENABLE_DATA_TA) ?
- (MCF5272_GPIO_PBCNT_TA_EN) :
- (MCF5272_GPIO_PBCNT_TA_DE)));
-
- // Do any platform-specific reset initialization.
-
- plf_reset();
-}
-