diff --git a/packages/ecos.db b/packages/ecos.db index bd3595c..a133738 100644 --- a/packages/ecos.db +++ b/packages/ecos.db @@ -2701,6 +2701,17 @@ package CYGPKG_HAL_ARM_AT91SAM7 { an Atmel AT91SAM7 family of CPUs." } +package CYGPKG_HAL_ARM_AT91SAM9 { + alias { "Atmel AT91SAM9" hal_arm_at91sam9 arm_at91_sam9 } + directory hal/arm/at91/at91sam9 + script hal_arm_at91sam9.cdl + hardware + description " + The at91sam9 HAL package provides the support needed to run eCos on + an Atmel AT91SAM9 family of CPUs." +} + + package CYGPKG_HAL_ARM_AT91SAM7SEK { alias { "Atmel AT91SAM7S" hal_arm_at91sam7sek arm_at91_sam7sek } directory hal/arm/at91/at91sam7sek @@ -2781,6 +2792,16 @@ package CYGPKG_HAL_ARM_AT91_PHYCORE { an PHYTEC evaluation board (phyCORE AT91M55800A based on HD200)." } +package CYGPKG_HAL_ARM_AT91SAM9263EK { + alias { "Atmel AT91SAM9263-EK" hal_arm_at91sam9263ek arm_at91sam9263ek } + directory hal/arm/at91/at91sam9263ek + script hal_arm_at91sam9263ek.cdl + hardware + description " + The at91sam9263ek HAL package provides the support needed to run eCos on + an Atmel AT91SAM9263-EK development board." +} + package CYGPKG_HAL_ARM_LPC2XXX { alias { "Philips LPC2XXX variant HAL" hal_arm_lpc2xxx arm_lpc2xxx_hal } directory hal/arm/lpc2xxx/var @@ -4646,6 +4667,21 @@ target at91sam7xek { Atmel AT91SAM7X-EK evaluation board." } +target at91sam9263ek { + alias { "Atmel AT91SAM9263-EK evaluation board" at91_at91sam9263ek } + packages { CYGPKG_HAL_ARM + CYGPKG_HAL_ARM_AT91 + CYGPKG_HAL_ARM_AT91SAM9 + CYGPKG_HAL_ARM_AT91SAM9263EK + CYGPKG_IO_SERIAL_ARM_AT91 + } + description " + The at91sam9263ek target provides the packages needed to run eCos on an + Atmel AT91SAM9263-EK evaluation board." +} + + + target sam7ex256 { alias { "Olimex SAM7-EX256 evaluation board" at91_sam7ex256 } packages { CYGPKG_HAL_ARM diff --git a/packages/hal/arm/at91/at91sam9/current/cdl/hal_arm_at91sam9.cdl b/packages/hal/arm/at91/at91sam9/current/cdl/hal_arm_at91sam9.cdl new file mode 100644 index 0000000..5e237f3 --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/cdl/hal_arm_at91sam9.cdl @@ -0,0 +1,441 @@ +# ==================================================================== +# +# hal_arm_at91_sam9.cdl +# +# ARM AT91 SAM7 HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett +## Copyright (C) 2005 eCosCentric Ltd +## Copyright (C) 2005 Andrew Lunn +## Copyright (C) 2008 Evgeniy Dushistov +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Contributors: gthomas, tkoeller, nickg, Oliver Munz, asl +# Date: 2005-06-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_AT91SAM9 { + display "Atmel AT91SAM9 HAL" + parent CYGPKG_HAL_ARM + define_header hal_arm_at91sam9.h + include_dir cyg/hal + hardware + description " + The AT91SAM9 HAL package provides the support needed to run + eCos on an Atmel AT91SAM9 based board." + + compile at91sam9_misc.c + + requires { CYGHWR_HAL_ARM_AT91_FIQ } +# requires { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s32" implies +# CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0 == 0 } + + implements CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW + implements CYGINT_HAL_ARM_AT91_PIT_HW + implements CYGINT_HAL_ARM_AT91_SYS_INTERRUPT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " + puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H" + } + + cdl_option CYGHWR_HAL_ARM_AT91SAM9 { + display "AT91SAM9 variant used" + flavor data + default_value {"at91sam9263ek"} + legal_values {"at91sam9263ek"} + description " + The AT91SAM9 microcontroller family has several variants, + the main differences being the amount of on-chip SRAM, + FLASH, peripherals and their layout. This option allows the + platform HALs to select the specific microcontroller + being used." + } + + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + legal_values 1 to 0xffff + calculated { (CYGNUM_HAL_RTC_NUMERATOR * + CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / + (CYGBLD_HAL_ARM_AT91_TIMER_TC ? 32 : 16) / + CYGNUM_HAL_RTC_DENOMINATOR / + 1000000000 + ) + } + description "Value to program into the RTC clock generator." + } + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"ROM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targeting the AT91SAM9 eval boards it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using on board + debug software such as Angel or eCos GDB stubs. Select 'rom' + when building a stand-alone application which will be put + into ROM" + } + + cdl_option CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS { + display "Address in flash the image should live" + active_if { CYG_HAL_STARTUP == "ROM" } + flavor data + default_value 0x00100000 + description " + This optionspecifies where in flash the image + lives. By default it is at the bottom of the flash, + but for example redboot may be at the bottom and an + application lives higher up, which is acheived by + setting the address here." + } + + # Real-time clock/counter specifics + cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_SPEED { + display "CPU clock speed" + flavor data + calculated { CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN * + CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER / + CYGNUM_HAL_ARM_AT91_PLL_DIVIDER / 2} + legal_values { 0 to 220000000 } + description " + The master clock-frequency has to be 48MHz, 96MHz or + 192MHz for the USB to work correctly. The clock setup uses + PLL clock divided by two" + } + + cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_XIN_FREQ_MAX { + display "Input clock frequency maximum" + flavor data + calculated { CYGNUM_HAL_ARM_AT91_CLOCK_TYPE == "CRYSTAL" ? + 20000000 : 50000000 } + description " + + The oscilator in the AT91SAM allows a crystal of up to + 20MHz. However by feeding in directly a clock signal, it + is possible to use upto 50MHz in XIN." + } + + cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN { + display "Main oscillator frequency" + flavor data + legal_values { 3000000 to CYGNUM_HAL_ARM_AT91_CLOCK_XIN_FREQ_MAX } + default_value { 18432000 } + description " + The frequency of the clock input, be it a crystal or a clock + signal" + } + + cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_TYPE { + display "Type of main frequency input" + flavor data + default_value { "CRYSTAL" } + legal_values { "CRYSTAL" "EXTCLOCK" } + description " + Whether a crystal or a XIN input clock is clocking the device." + } + + cdl_option CYGNUM_HAL_ARM_AT91_PMC_MOR_OSCCOUNT { + display "Startup time for the main oscillator" + flavor data + legal_values { 0 to 255 } + default_value 64 + description " + Specifies the number of Slow Clock cycles multiplied by 8 + for the Main Oscillator start-up time. 64 is the number suggested + by the kind folk at Atmel" + } + + cdl_option CYGNUM_HAL_ARM_AT91_PLL_DIVIDER { + display "Divider for PLL clock" + flavor data + legal_values { 0 to 255 } + default_value 9 + description " + The X-tal clock is divided by this value when generating the + PLL clock" + } + + cdl_option CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER { + display "Multiplier for PLL clock" + flavor data + legal_values { 0 to 2047 } + default_value 109 + description " + The X-tal clock is multiplied by this value when generating + the PLL clock." + } + + cdl_option CYGNUM_HAL_ARM_AT91_PLL_COUNT { + display "Startup Counter for PLL clock" + flavor data + legal_values { 0 to 64 } + default_value 16 + description " + Specifies the number of slow clock cycles before the LOCK bit + is set in PMC_SR after PLL Register is written. The Atmel people + suggest that 16 should be fine" + } + + cdl_option CYGNUM_HAL_ARM_AT91_SLOW_CLOCK { + display "Slow clock frequency" + flavor data + default_value { 32768 } + description " + The slow clock is an LC oscillator which runs all the + time. The accuracy of this clock is not very high and + is temperature dependent." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + default_value 4 + description " + The AT91SAM9 development boards has two Serial port connectors. + these correspond to USART0 and the Debug Serial port. The chip + has a third serial port which does not have a 9pin D + connector, but is accessible via the patch panel pins." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The AT91SAM9 has three serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 1 + description " + The AT91SAM9 board has three USART serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGBLD_HAL_ARM_AT91_BAUD_DYNAMIC { + display "Dynamic calculation of baud rate" + default_value 0 + description " + The AT91SAM9 has a flexible clock generation mechanism + where the main clock used to drive peripherals can be + changed during run time. Such changes affect the serial port + baud rate generators. Enabling this option includes code + which calculates the baud rate setting dynamically from the + current clock settings. Without this option a static + calculation is performed which assumes the clock frequency + has not been changed." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm926ej-s -mfloat-abi=softfp -mfpu=vfp -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { (CYGHWR_THUMB ? "-mthumb " : "") . (CYGBLD_ARM_ENABLE_THUMB_INTERWORK ? "-mthumb-interwork " : "") . "-mcpu=arm926ej-s -mfloat-abi=softfp -mfpu=vfp -Wl,--gc-sections -Wl,-static -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? \ + "arm_" . CYGHWR_HAL_ARM_AT91SAM9 . "_ram" : + "arm_" . CYGHWR_HAL_ARM_AT91SAM9 . "_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? \ + "" : + "" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? \ + "" : + "" } + } + } +} diff --git a/packages/hal/arm/at91/at91sam9/current/include/hal_platform_ints.h b/packages/hal/arm/at91/at91sam9/current/include/hal_platform_ints.h new file mode 100644 index 0000000..3ae9d35 --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/include/hal_platform_ints.h @@ -0,0 +1,121 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock assignments for AT91SAM9 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2006 eCosCentric Ltd +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, Oliver Munz, Andrew Lunn, John Eigelaar, Evgeniy Dushistov +// Date: 2001-07-12 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for the AT91SAM7 platform are +// defined here. +// +// Usage: #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include + +#define CYGNUM_HAL_INTERRUPT_FIQ 0 + +#define CYGNUM_HAL_INTERRUPT_SYS 1 +#define CYGNUM_HAL_INTERRUPT_PIOA 2 + +#define CYGNUM_HAL_INTERRUPT_PIOB 3 +#define CYGNUM_HAL_INTERRUPT_PIOC_TO_PIOE 4 + +#define CYGNUM_HAL_INTERRUPT_USART0 7 +#define CYGNUM_HAL_INTERRUPT_USART1 8 +#define CYGNUM_HAL_INTERRUPT_USART2 9 +#define CYGNUM_HAL_INTERRUPT_MCI0 10 +#define CYGNUM_HAL_INTERRUPT_MCI1 11 +#define CYGNUM_HAL_INTERRUPT_CAN 12 +#define CYGNUM_HAL_INTERRUPT_TWI 13 +#define CYGNUM_HAL_INTERRUPT_SPI0 14 +#define CYGNUM_HAL_INTERRUPT_SPI1 15 +#define CYGNUM_HAL_INTERRUPT_SSC0 16 +#define CYGNUM_HAL_INTERRUPT_SSC1 17 +#define CYGNUM_HAL_INTERRUPT_AC97C 18 +#define CYGNUM_HAL_INTERRUPT_TC0_TC1_TC3 19 +#define CYGNUM_HAL_INTERRUPT_PWMC 20 +#define CYGNUM_HAL_INTERRUPT_EMAC 21 +#define CYGNUM_HAL_INTERRUPT_2DGE 23 +#define CYGNUM_HAL_INTERRUPT_UDP 24 +#define CYGNUM_HAL_INTERRUPT_ISI 25 +#define CYGNUM_HAL_INTERRUPT_LCDC 26 +#define CYGNUM_HAL_INTERRUPT_DMA 27 +#define CYGNUM_HAL_INTERRUPT_UHP 29 + +#define CYGNUM_HAL_INTERRUPT_IRQ0 30 +#define CYGNUM_HAL_INTERRUPT_IRQ1 31 + +// Interrupts which are multiplexed on to the System Interrupt +#define CYGNUM_HAL_INTERRUPT_PITC 32 +#define CYGNUM_HAL_INTERRUPT_RTTC 33 +#define CYGNUM_HAL_INTERRUPT_PMC 34 +#define CYGNUM_HAL_INTERRUPT_WDTC 36 +#define CYGNUM_HAL_INTERRUPT_RSTC 37 +#define CYGNUM_HAL_INTERRUPT_DBG 38 + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 38 + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +// The vector used by the Real time clock +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_TC +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TC0 +#endif +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_PIT +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_PITC +#endif + +//---------------------------------------------------------------------------- +// Reset. +__externC void hal_at91_reset_cpu(void); +#define HAL_PLATFORM_RESET() hal_at91_reset_cpu() + +#define HAL_PLATFORM_RESET_ENTRY 0x0000000 + +#endif // CYGONCE_HAL_PLATFORM_INTS_H diff --git a/packages/hal/arm/at91/at91sam9/current/include/hal_platform_setup.h b/packages/hal/arm/at91/at91sam9/current/include/hal_platform_setup.h new file mode 100644 index 0000000..1f9b585 --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/include/hal_platform_setup.h @@ -0,0 +1,166 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2006 eCosCentric Ltd +// Copy + +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors:gthomas, asl +// Date: 2006-02-18 +// Purpose: AT91SAM7S platform specific support routines +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include +#include + +// Macro to initialise the Memory Controller + .macro _flash_init +__flash_init__: + ldr r0,=AT91_MC +#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000 + // When the clock is running faster than 60MHz we need two wait states + ldr r1,=(AT91_MC_FMR_2FWS) +#else +# if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000 + // When the clock is running faster than 30MHz we need a wait state + ldr r1,=(AT91_MC_FMR_1FWS) +# else + // We have a slow clock, no extra wait states are needed + ldr r1,=AT91_MC_FMR_0FWS +# endif +#endif + str r1,[r0,#AT91_MC_FMR] +#if defined(AT91_MC_FMR1) + // If we have a second flash controller we need to set that up as well + str r1,[r0,#AT91_MC_FMR1] +#endif + .endm + +// Macro to start the main clock. + .macro _main_clock_init +__main_clock_init__: + ldr r0,=AT91_PMC + + // Check that we have a stable clock before we start switching +wait_pmc_sr_0: + ldr r1,[r0,#AT91_PMC_SR] + ands r1,r1,#AT91_PMC_SR_MCKRDY + beq wait_pmc_sr_0 + + // Swap to the slow clock, just to be sure. + ldr r1,=(AT91_PMC_MCKR_PRES_CLK|AT91_PMC_MCKR_SLOW_CLK) + str r1,[r0,#AT91_PMC_MCKR] + +#if defined(CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_EXTCLOCK) + ldr r1,=(AT91_PMC_MOR_OSCBYPASS) +#else + ldr r1,=(AT91_PMC_MOR_OSCCOUNT(CYGNUM_HAL_ARM_AT91_PMC_MOR_OSCCOUNT)|AT91_PMC_MOR_MOSCEN) +#endif + str r1,[r0,#AT91_PMC_MOR] + + // Wait for oscilator start timeout +wait_pmc_sr_1: + ldr r1,[r0,#AT91_PMC_SR] + ands r1,r1,#AT91_PMC_SR_MOSCS + beq wait_pmc_sr_1 + + // Set the PLL multiplier and divider. 16 slow clocks go by + // before the LOCK bit is set. */ + ldr r1,=((AT91_PMC_PLLR_DIV(CYGNUM_HAL_ARM_AT91_PLL_DIVIDER))|(AT91_PMC_PLLR_PLLCOUNT(CYGNUM_HAL_ARM_AT91_PLL_COUNT))|(AT91_PMC_PLLR_MUL(CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER-1))) + str r1,[r0,#AT91_PMC_PLLR] + + // Wait for PLL locked indication +wait_pmc_sr_2: + ldr r1,[r0,#AT91_PMC_SR] + ands r1,r1,#AT91_PMC_SR_LOCK + beq wait_pmc_sr_2 + + // Enable the PLL clock and set the prescale to 2 */ + ldr r1,=(AT91_PMC_MCKR_PRES_CLK_2|AT91_PMC_MCKR_PLL_CLK) + str r1,[r0,#AT91_PMC_MCKR] + + // Wait for the MCLK ready indication +wait_pmc_sr_3: + ldr r1,[r0,#AT91_PMC_SR] + ands r1,r1,#AT91_PMC_SR_MCKRDY + beq wait_pmc_sr_3 + .endm + +// Remap the flash from address 0x0 and place RAM there instead. + .macro _remap_flash +__remap_flash: + ldr r0,=0x000004 // Use the underfined instruction exception + ldr r1,=0x200004 + ldr r2,[r0] // Save away copies so we can restore them + ldr r3,[r1] + ldr r4,=0xffffff + eor r4,r3,r4 // XOR the contents of 0x20004 + str r4,[r1] // and write it + ldr r5,[r0] // Read from low memory + cmp r5,r4 + beq remap_done + ldr r0,=AT91_MC // Need to do a remap + ldr r5,=1 + str r5,[r0,#AT91_MC_RCR] +remap_done: + str r3,[r1] // restore the value we changed + .endm + +#if defined(CYG_HAL_STARTUP_ROM) + .macro _setup + _flash_init + _main_clock_init + _remap_flash + .endm + +#define PLATFORM_SETUP1 _setup +#else +#define PLATFORM_SETUP1 +#endif + +//----------------------------------------------------------------------------- +// end of hal_platform_setup.h +#endif // CYGONCE_HAL_PLATFORM_SETUP_H diff --git a/packages/hal/arm/at91/at91sam9/current/include/pkgconf/mlt_arm_at91sam9263ek_ram.h b/packages/hal/arm/at91/at91sam9/current/include/pkgconf/mlt_arm_at91sam9263ek_ram.h new file mode 100644 index 0000000..88f0d3f --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/include/pkgconf/mlt_arm_at91sam9263ek_ram.h @@ -0,0 +1,25 @@ +// eCos memory layout - Mon Nov 10 16:00:46 MSK 2008 + +// This is a generated by hands file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0x23f00000) +#define CYGMEM_REGION_ram_SIZE (0x80000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x00100000) +#define CYGMEM_REGION_rom_SIZE (0x40000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_bootmon) []; +#endif +#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon)) +#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x23f80000 - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/packages/hal/arm/at91/at91sam9/current/include/pkgconf/mlt_arm_at91sam9263ek_ram.ldi b/packages/hal/arm/at91/at91sam9/current/include/pkgconf/mlt_arm_at91sam9263ek_ram.ldi new file mode 100644 index 0000000..e6ca3d4 --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/include/pkgconf/mlt_arm_at91sam9263ek_ram.ldi @@ -0,0 +1,29 @@ +// eCos memory layout - Mon Nov 10 16:00:46 MSK 2008 + +// This is a generated by hands file - do not edit + +#include +#include + +MEMORY +{ + ram : ORIGIN = 0x23f00000, LENGTH = 0x80000 +} + +SECTIONS +{ + SECTIONS_BEGIN +// CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000; + SECTION_rom_vectors (ram, 0x23f00400, LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x23f00600, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} \ No newline at end of file diff --git a/packages/hal/arm/at91/at91sam9/current/include/plf_io.h b/packages/hal/arm/at91/at91sam9/current/include/plf_io.h new file mode 100644 index 0000000..ec8c4ea --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/include/plf_io.h @@ -0,0 +1,190 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// AT91SAM7S board specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tkoeller +// Contributors: andrew lunn, Oliver Munz +// Date: 2005-12-31 +// Purpose: Atmel AT91SAM7S board specific registers +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include + +#define CYGARC_PHYSICAL_ADDRESS(_x_) + +//SPI - Serial Peripheral Interface +#define AT91_SPI0 0xFFFA4000 +#define AT91_SPI1 0xFFFA8000 + +#define AT91_SPI AT91_SPI0 + +// DMA registers +#define AT91_SPI_RPR 0x100 // Receive Pointer Register +#define AT91_SPI_RCR 0x104 // Receive Counter Register +#define AT91_SPI_TPR 0x108 // Transmit Pointer Register +#define AT91_SPI_TCR 0x10C // Transmit Counter Register +#define AT91_SPI_NRPR 0x110 // Next Receive Pointer Register +#define AT91_SPI_NRCR 0x114 // Next Receive Counter Register +#define AT91_SPI_NTPR 0x118 // Next Transmit Pointer Register +#define AT91_SPI_NTCR 0x11C // Next Transmit Counter Register +#define AT91_SPI_PTCR 0x120 // PDC Transfer Control Register +#define AT91_SPI_PTSR 0x124 // PDC Transfer Status Register + + +// Peripheral Input/Output Controllers +#define AT91_PIOA 0xFFFFF200 +#define AT91_PIOB 0xFFFFF400 +#define AT91_PIOC 0xFFFFF600 +#define AT91_PIOD 0xFFFFF800 +#define AT91_PIOE 0xFFFFFA00 + +#define AT91_PIO_DBGU AT91_PIOC + +// USART +#define AT91_USART0 0xFFF8C000 +#define AT91_USART1 0xFFF90000 +#define AT91_USART2 0xFFF94000 + +#define AT91_DBG 0xFFFFEE00 + +#ifndef __ASSEMBLER__ +#ifdef CYGBLD_HAL_ARM_AT91_BAUD_DYNAMIC +extern cyg_uint32 hal_at91_us_baud(cyg_uint32 baud); +#define AT91_US_BAUD(baud) hal_at91_us_baud(baud) +#endif +#endif // __ASSEMBLER__ + +#define AT91_US_RPR 0x100 // Receive Pointer Register +#define AT91_US_RCR 0x104 // Receive Counter Register +#define AT91_US_TPR 0x108 // Transmit Pointer Register +#define AT91_US_TCR 0x10C // Transmit Counter Register +#define AT91_US_NRPR 0x110 // Next Receive Pointer Register +#define AT91_US_NRCR 0x114 // Next Receive Counter Register +#define AT91_US_NTPR 0x118 // Next Transmit Pointer Register +#define AT91_US_NTCR 0x11C // Next Transmit Counter Register +#define AT91_US_PTCR 0x120 // PDC Transfer Control Register +#define AT91_US_PTSR 0x124 // PDC Transfer Status Register + +// PIO - Programmable I/O + +#define AT91_PIO AT91_PIOA + +// TC - Timer Counter + +#define AT91_TC 0xFFF7C000 + +// Power Management Controller + +#define AT91_PMC 0xFFFFFC00 + +#define AT91_PMC_MOR 0x20 // Main Oscillator Register +#define AT91_PMC_MOR_MOSCEN (1 << 0) // Main Oscillator Enable +#define AT91_PMC_MOR_OSCBYPASS (1 << 1) // Main Oscillator Bypass +#define AT91_PMC_MOR_OSCCOUNT(x) (x << 8) // Slow clocks ticks +#define AT91_PMC_MCFR 0x24 // Main Clock Frequency Register +#define AT91_PMC_PLLR 0x2c // PLL Register +#define AT91_PMC_PLLR_DIV(x) ((x) << 0) // PLL Devide +#define AT91_PMC_PLLR_PLLCOUNT(x) ((x) << 8) // PLL Count +#define AT91_PMC_PLLR_MUL(x) ((x) << 16) // PLL Devide +#define AT91_PMC_PLLR_OUT_0 (0 << 14) +#define AT91_PMC_PLLR_OUT_1 (1 << 14) +#define AT91_PMC_PLLR_OUT_2 (2 << 14) +#define AT91_PMC_PLLR_OUT_3 (3 << 14) +#define AT91_PMC_PLLR_USBDIV_0 (0 << 28) // USB clock is PLL clock / 1 +#define AT91_PMC_PLLR_USBDIV_1 (1 << 28) // USB clock is PLL clock / 2 +#define AT91_PMC_PLLR_USBDIV_2 (2 << 28) // USB clock is PLL clock / 4 +#define AT91_PMC_MCKR 0x30 // Master Clock Register +#define AT91_PMC_MCKR_SLOW_CLK (0 << 0) // Slow clock selected +#define AT91_PMC_MCKR_MAIN_CLK (1 << 0) // Main clock selected +#define AT91_PMC_MCKR_PLL_CLK (3 << 0) // PLL clock selected +#define AT91_PMC_MCKR_PRES_CLK (0 << 2) // divide by 1 +#define AT91_PMC_MCKR_PRES_CLK_2 (1 << 2) // divide by 2 +#define AT91_PMC_MCKR_PRES_CLK_4 (2 << 2) // divide by 4 +#define AT91_PMC_MCKR_PRES_CLK_8 (3 << 2) // divide by 8 +#define AT91_PMC_MCKR_PRES_CLK_16 (4 << 2) // divide by 16 +#define AT91_PMC_MCKR_PRES_CLK_32 (5 << 2) // divide by 32 +#define AT91_PMC_MCKR_PRES_CLK_64 (6 << 2) // divide by 64 +#define AT91_PMC_PCKR0 0x40 // Programmable Clock Register 0 +#define AT91_PMC_PCKR1 0x44 // Programmable Clock Register 1 +#define AT91_PMC_PCKR2 0x48 // Programmable Clock Register 2 +#define AT91_PMC_IER 0x60 // Interrupt Enable Register +#define AT91_PMC_IDR 0x64 // Interrupt Disable Register +#define AT91_PMC_SR 0x68 // Status Register +#define AT91_PMC_SR_MOSCS (1 << 0) // Main oscillator stable +#define AT91_PMC_SR_LOCK (1 << 2) // PLL Locked +#define AT91_PMC_SR_MCKRDY (1 << 3) // MCK is ready to be enabled +#define AT91_PMC_SR_PCK0RDY (1 << 8) // Pad clock 0 is ready to be enabled +#define AT91_PMC_SR_PCK1RDY (1 << 9) // Pad clock 1 is ready to be enabled +#define AT91_PMC_SR_PCK2RDY (1 << 10) // Pad clock 2 is ready to be enabled +#define AT91_PMC_SR_PCK3RDY (1 << 11) // Pad clock 3 is ready to be enabled +#define AT91_PMC_IMR 0x6c // Interrupt Mask Register + + + +// EMAC - Ethernet Medium Access Controller + +#define AT91_EMAC 0xFFFBC000 + +// CAN - Controller Area Network + +#define AT91_CAN 0xFFFAC000 + +//---------------------------------------------------------------------- +// The platform needs this initialization during the +// hal_hardware_init() function in the varient HAL. +#ifndef __ASSEMBLER__ +extern void hal_plf_hardware_init(void); +#define HAL_PLF_HARDWARE_INIT() \ + hal_plf_hardware_init() + +#ifdef CYGHWR_HAL_ARM_AT91SAM7X +extern void hal_plf_eth_init(void); +#define HAL_PLF_ETH_INIT() \ + hal_plf_eth_init() +#endif + +#endif //__ASSEMBLER__ + +#endif //CYGONCE_HAL_PLF_IO_H + diff --git a/packages/hal/arm/at91/at91sam9/current/misc/redboot_RAM.ecm b/packages/hal/arm/at91/at91sam9/current/misc/redboot_RAM.ecm new file mode 100644 index 0000000..b7f956e --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/misc/redboot_RAM.ecm @@ -0,0 +1,82 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware at91sam7s ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_AT91 current ; + package -hardware CYGPKG_DEVS_FLASH_AT91 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -16 +}; + + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_DEV_FLASH_AT91_LOCKING { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -24 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x15000 +}; + +cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { + user_value 1 +}; \ No newline at end of file diff --git a/packages/hal/arm/at91/at91sam9/current/misc/redboot_ROM.ecm b/packages/hal/arm/at91/at91sam9/current/misc/redboot_ROM.ecm new file mode 100644 index 0000000..e18ee4b --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/misc/redboot_ROM.ecm @@ -0,0 +1,90 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware at91sam7s ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_AT91 current ; + package -hardware CYGPKG_DEVS_FLASH_AT91 current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 6144 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -16 +}; + + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_DEV_FLASH_AT91_LOCKING { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -24 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x15000 +}; + +cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { + user_value 1 +}; \ No newline at end of file diff --git a/packages/hal/arm/at91/at91sam9/current/src/at91sam9_misc.c b/packages/hal/arm/at91/at91sam9/current/src/at91sam9_misc.c new file mode 100644 index 0000000..932f2d9 --- /dev/null +++ b/packages/hal/arm/at91/at91sam9/current/src/at91sam9_misc.c @@ -0,0 +1,176 @@ +/*========================================================================== +// +// at91sam9_misc.c +// +// HAL misc board support code for Atmel AT91sam9 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// Copyright (C) 2006 eCosCentric Ltd +// Copyright (C) 2006 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, nickg, tkoeller, Oliver Munz, Andrew Lunn, Evgeniy Dushistov +// Date: 2001-07-12 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include +#include + +#include // base types +#include // tracing macros +#include // assertion macros + +#include // IO macros +#include // Register state info +#include +#include // necessary? +#include +#include // calling interface +#include // helper functions +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include // HAL ISR support +#endif + +extern void hal_at91_led(int val); + +void +hal_at91_set_leds (int val) +{ + hal_at91_led(val); +} + +// ------------------------------------------------------------------------- +// Hardware init + +void hal_plf_hardware_init (void) +{ + /* Enable the Serial devices to driver the serial port pins */ + HAL_ARM_AT91_PIO_CFG(AT91_USART_RXD0); + HAL_ARM_AT91_PIO_CFG(AT91_USART_TXD0); + HAL_ARM_AT91_PIO_CFG(AT91_DBG_DTXD); + HAL_ARM_AT91_PIO_CFG(AT91_DBG_DRXD); + + /* Enable the Serial devices to driver the serial port pins */ + HAL_ARM_AT91_PIO_CFG(AT91_USART_RXD1); + HAL_ARM_AT91_PIO_CFG(AT91_USART_TXD1); + + + /* Setup the Reset controller. Allow user resets */ + HAL_WRITE_UINT32(AT91_RST+AT91_RST_RMR, + AT91_RST_RMR_URSTEN | + 10 << 8 | + AT91_RST_RMR_KEY); + +#ifdef CYGBLD_HAL_ARM_AT91_SERIAL_UART + /* Enable peripheral clocks for USART 0 and 1 if they are to be used */ + HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, + AT91_PMC_PCER_US0 | + AT91_PMC_PCER_US1); +#endif + +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_TC + /* Enable peripheral clocks for TC 0 and 1 if they are to be used */ + HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, + AT91_PMC_PCER_TC0 | + AT91_PMC_PCER_TC2); +#endif + +#ifndef CYGPKG_IO_WATCHDOG + /* Disable the watchdog. The eCos philosophy is that the watchdog is + disabled unless the watchdog driver is used to enable it. + Whoever if we disable it here we cannot re-enable it in the + watchdog driver, hence the conditional compilation. */ + HAL_WRITE_UINT32(AT91_WDTC + AT91_WDTC_WDMR, AT91_WDTC_WDMR_DIS); +#endif + +/* Perform some platform specific bits to get the Ethernet hardware + setup. Specifically if a specific phy is used and does not start in + the correct mode a function needs to be supplied as part of the plf + to do the necessary initializations. +*/ +#ifdef CYGPKG_DEVS_ETH_ARM_AT91 +#ifdef HAL_PLF_ETH_INIT + HAL_PLF_ETH_INIT(); +#endif +#endif +} + +// Calculate the baud value to be programmed into the serial port baud +// rate generators. This function will determine what the clock speed +// is that is driving the generator so it can be used in situations +// when the application dynamically changes the clock speed. +cyg_uint32 +hal_at91_us_baud(cyg_uint32 baud_rate) +{ + cyg_uint32 val, pll; + cyg_uint32 main_clock = 0; + cyg_uint32 baud_value = 0; + + HAL_READ_UINT32((AT91_PMC+AT91_PMC_MCKR), val); + switch (val & 0x03) { + /* Slow clock */ + case AT91_PMC_MCKR_SLOW_CLK: + main_clock = CYGNUM_HAL_ARM_AT91_SLOW_CLOCK; + break; + + /* Main clock */ + case AT91_PMC_MCKR_MAIN_CLK: + main_clock = CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN; + break; + /* PLL */ + case AT91_PMC_MCKR_PLL_CLK: + HAL_READ_UINT32((AT91_PMC+AT91_PMC_PLLR), pll); + main_clock = CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN * + (((pll & 0x7FF0000) >> 16) + 1) / (pll & 0xFF); + break; + } + + // Process prescale + val = (val & 0x1C) >> 2; + main_clock = main_clock >> val; + + /* Define the baud rate divisor register, (round) */ + baud_value = (main_clock/(8*baud_rate)+1)/2; + + return baud_value; +} + +//-------------------------------------------------------------------------- +// EOF at91sam7s_misc.c diff --git a/packages/hal/arm/at91/at91sam9263ek/current/cdl/hal_arm_at91sam9263ek.cdl b/packages/hal/arm/at91/at91sam9263ek/current/cdl/hal_arm_at91sam9263ek.cdl new file mode 100644 index 0000000..55b83ae --- /dev/null +++ b/packages/hal/arm/at91/at91sam9263ek/current/cdl/hal_arm_at91sam9263ek.cdl @@ -0,0 +1,69 @@ +# ==================================================================== +# +# hal_arm_at91sam9263ek.cdl +# +# ARM AT91 SAM9263 EK development board package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## Copyright (C) 2008 Evgeniy Dushistov +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Contributors: +# Date: +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_AT91SAM9263EK { + display "Atmel AT91SAM9263-EK development board" + parent CYGPKG_HAL_ARM_AT91SAM9 + define_header hal_arm_at91sam9263ek.h + include_dir cyg/hal + hardware + description " + The AT91SAM9263EK HAL package provides the support needed to run + eCos on an Atmel AT91SAM9263-EK development board." + + compile at91sam9263ek_misc.c + + requires { CYGHWR_HAL_ARM_AT91 == "AT91SAM9" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_header "/***** proc output start *****/" + puts $::cdl_header "#include " + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM926EJ-S\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Atmel (AT91SAM9263-EK)\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "/****** proc output end ******/" + } +} \ No newline at end of file diff --git a/packages/hal/arm/at91/at91sam9263ek/current/src/at91sam9263ek_misc.c b/packages/hal/arm/at91/at91sam9263ek/current/src/at91sam9263ek_misc.c new file mode 100644 index 0000000..001b3ed --- /dev/null +++ b/packages/hal/arm/at91/at91sam9263ek/current/src/at91sam9263ek_misc.c @@ -0,0 +1,27 @@ +//! \todo reaaly need this file? +#include +#include + +#include // IO macros + + +// The development board has four LEDs +void +hal_at91_led (int val) +{ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA0, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA1, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA2, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PA3, AT91_PIN_OUT); + + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA0, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA1, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA2, AT91_PIN_PULLUP_DISABLE); + HAL_ARM_AT91_GPIO_CFG_PULLUP(AT91_GPIO_PA3, AT91_PIN_PULLUP_DISABLE); + + // Set the bits. The logic is inverted + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA0, !(val & 1)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA1, !(val & 2)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA2, !(val & 4)); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PA3, !(val & 8)); +} diff --git a/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl b/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl index cf9c9f0..fcdad5d 100644 --- a/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl +++ b/packages/hal/arm/at91/var/current/cdl/hal_arm_at91.cdl @@ -65,7 +65,6 @@ cdl_package CYGPKG_HAL_ARM_AT91 { implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT - implements CYGINT_HAL_ARM_ARCH_ARM7 implements CYGINT_HAL_ARM_THUMB_ARCH # Let the architectural HAL see this variant's files @@ -79,7 +78,7 @@ cdl_package CYGPKG_HAL_ARM_AT91 { flavor data default_value {"R40807"} legal_values {"R40807" "R40008" "M42800A" "M55800A" "JTST" - "AT91SAM7S" } + "AT91SAM7S" "AT91SAM9"} description "The AT91 microcontroller family has several variants, the main differences being the amount of on-chip SRAM, peripherals and their layout. This option allows the @@ -87,6 +86,20 @@ cdl_package CYGPKG_HAL_ARM_AT91 { being used." } + cdl_option CYGHWR_HAL_ARM_AT91_ARM7 { + display "ARM7 core" + no_define + calculated { is_substr("R40807 R40008 M42800A M55800A JTST AT91SAM7S", CYGHWR_HAL_ARM_AT91) } + implements CYGINT_HAL_ARM_ARCH_ARM7 + } + + cdl_option CYGHWR_HAL_ARM_AT91_ARM9 { + display "ARM9 core" + no_define + calculated { is_substr("AT91SAM9", CYGHWR_HAL_ARM_AT91) } + implements CYGINT_HAL_ARM_ARCH_ARM9 + } + cdl_option CYGHWR_HAL_ARM_AT91_FIQ { display "handle FIQ as an IRQ" flavor bool diff --git a/packages/hal/arm/at91/var/current/include/var_arch.h b/packages/hal/arm/at91/var/current/include/var_arch.h index 4f906f3..d32fc2f 100644 --- a/packages/hal/arm/at91/var/current/include/var_arch.h +++ b/packages/hal/arm/at91/var/current/include/var_arch.h @@ -75,7 +75,8 @@ CYG_MACRO_END #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \ defined(CYGHWR_HAL_ARM_AT91_M55800A) || \ - defined(CYGHWR_HAL_ARM_AT91SAM7) + defined(CYGHWR_HAL_ARM_AT91SAM7) || \ + defined(CYGPKG_HAL_ARM_AT91SAM9263EK) \ #define HAL_IDLE_THREAD_ACTION(_count_) \ CYG_MACRO_START \ diff --git a/packages/hal/arm/at91/var/current/include/var_io.h b/packages/hal/arm/at91/var/current/include/var_io.h index 404fb68..ed7cffa 100644 --- a/packages/hal/arm/at91/var/current/include/var_io.h +++ b/packages/hal/arm/at91/var/current/include/var_io.h @@ -167,6 +167,10 @@ #define AT91_PIO 0xFFFF0000 #endif +#ifndef AT91_PIO_DBGU +#define AT91_PIO_DBGU AT91_PIO +#endif + #define AT91_PIN(_ctrl_, _periph_, _pin_) \ ((_ctrl_ << 16) | (_periph_ << 8) | (_pin_)) @@ -1142,6 +1146,21 @@ #endif // CYGHWR_HAL_ARM_AT91SAM7SE +#elif defined (CYGHWR_HAL_ARM_AT91SAM9) +#include + +#define AT91_USART_RXD0 AT91_PIN(0,0,27) // USART 0 Receive Data +#define AT91_USART_TXD0 AT91_PIN(0,0,26) // USART 0 Transmit Data +#define AT91_USART_RTS0 AT91_PIN(0,0,28) // USART 0 Ready To Send +#define AT91_USART_CTS0 AT91_PIN(0,0,29) // USART 0 Clear To Send +#define AT91_DBG_DRXD AT91_PIN(2,0,30) // Debug UART Receive +#define AT91_DBG_DTXD AT91_PIN(2,0,31) // Debug UART Transmit +#define AT91_USART_TXD1 AT91_PIN(3,0,0) // USART 1 transmit data +#define AT91_USART_RXD1 AT91_PIN(3,0,1) // USART 1 receive data +#define AT91_PIO_PSR_DRXD (1 << 30) +#define AT91_PIO_PSR_DTXD (1 << 31) + +//end #elif defined (CYGHWR_HAL_ARM_AT91SAM9) #else #define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock #define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A @@ -1213,7 +1232,7 @@ #define AT91_PIO_IMR 0x48 // Interrupt mask #define AT91_PIO_ISR 0x4C // Interrupt status -#if defined(CYGHWR_HAL_ARM_AT91SAM7) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) || defined(CYGHWR_HAL_ARM_AT91SAM9) #define AT91_PIO_MDER 0x50 // Multi-drive Enable Register #define AT91_PIO_MDDR 0x54 // Multi-drive Disable Register #define AT91_PIO_MDSR 0x58 // Multi-drive Status Register @@ -1613,7 +1632,8 @@ #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \ defined(CYGHWR_HAL_ARM_AT91_M55800A) || \ - defined(CYGHWR_HAL_ARM_AT91SAM7) + defined(CYGHWR_HAL_ARM_AT91SAM7) || \ + defined(CYGHWR_HAL_ARM_AT91SAM9) // (Advanced) Power Management @@ -1775,6 +1795,33 @@ #define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0 #define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1 #define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2 +#elif defined(CYGHWR_HAL_ARM_AT91SAM9) + +#define AT91_PMC_PCER_PIOA (1 << 2) +#define AT91_PMC_PCER_PIOB (1 << 3) +#define AT91_PMC_PCER_PIOCDE (1 << 4) +#define AT91_PMC_PCER_US0 (1 << 7) +#define AT91_PMC_PCER_US1 (1 << 8) +#define AT91_PMC_PCER_US2 (1 << 9) +#define AT91_PMC_PCER_MCI0 (1 << 10) +#define AT91_PMC_PCER_MCI1 (1 << 11) +#define AT91_PMC_PCER_CAN (1 << 12) +#define AT91_PMC_PCER_TWI (1 << 13) +#define AT91_PMC_PCER_SPI0 (1 << 14) +#define AT91_PMC_PCER_SPI1 (1 << 15) +#define AT91_PMC_PCER_SSC0 (1 << 16) +#define AT91_PMC_PCER_SSC1 (1 << 17) +#define AT91_PMC_PCER_AC97C (1 << 18) +#define AT91_PMC_PCER_TC0 (1 << 19) +#define AT91_PMC_PCER_TC1 (1 << 19) +#define AT91_PMC_PCER_TC2 (1 << 19) +#define AT91_PMC_PCER_PWMC (1 << 20) +#define AT91_PMC_PCER_EMAC (1 << 21) +#define AT91_PMC_PCER_2DGE (1 << 23) +#define AT91_PMC_PCER_UDP (1 << 24) +#define AT91_PMC_PCER_ISI (1 << 25) +#define AT91_PMC_PCER_LCDC (1 << 26) +#define AT91_PMC_PCER_DMA (1 << 27) #elif defined(CYGHWR_HAL_ARM_AT91SAM7X) #define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock @@ -1932,7 +1979,7 @@ //============================================================================= // Watchdog Timer Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) || defined(CYGHWR_HAL_ARM_AT91SAM9) #ifndef AT91_WDTC #define AT91_WDTC 0xFFFFFD40 @@ -1957,7 +2004,7 @@ //============================================================================= // Reset Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) || defined(CYGHWR_HAL_ARM_AT91SAM9) #ifndef AT91_RST #define AT91_RST 0xFFFFFD00 @@ -2085,7 +2132,7 @@ //============================================================================= // Debug Unit -#if defined(CYGHWR_HAL_ARM_AT91SAM7) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) || defined(CYGHWR_HAL_ARM_AT91SAM9) #ifndef AT91_DBG #define AT91_DBG 0xFFFFF200 @@ -2201,7 +2248,7 @@ //============================================================================= // Periodic Interval Timer Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) || defined(CYGHWR_HAL_ARM_AT91SAM9) #ifndef AT91_PITC #define AT91_PITC 0xfffffd30 @@ -2220,7 +2267,7 @@ //============================================================================= // Real Time Timer Controller -#if defined(CYGHWR_HAL_ARM_AT91SAM7) +#if defined(CYGHWR_HAL_ARM_AT91SAM7) || defined(CYGHWR_HAL_ARM_AT91SAM9) #ifndef AT91_RTTC #define AT91_RTTC 0xFFFFFD20 @@ -3187,7 +3234,7 @@ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \ CYG_MACRO_END -#else +#elif !defined(AT91_PIOD) //---------------------- // Three PIO controllers //---------------------- @@ -3247,7 +3294,62 @@ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 2, AT91_PIOC); \ CYG_MACRO_END -#endif //!AT91_PIOB +#else +#ifdef CYGHWR_HAL_ARM_AT91SAM9 +//---------------------- +// More Three PIO controllers +//---------------------- +// Configure a peripheral pin for peripheral operation +#define HAL_ARM_AT91_PIO_CFG(_pin_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_PIOX_CFG(_pin_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END + +// Configure a GPIO pin direction +#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END + +// Configure a GPIO pin pullup resistor +#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END + +// Configure a GPIO pin to generate interrupts +#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END + +// Set a GPIO pin to 1 +#define HAL_ARM_AT91_GPIO_SET(_pin_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_GPIOX_SET(_pin_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END + +// Reset a GPIO pin to 0 +#define HAL_ARM_AT91_GPIO_RESET(_pin_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_GPIOX_RESET(_pin_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END + +// Get the state of a GPIO pin +#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \ + CYG_MACRO_START \ + cyg_uint32 _pctrl_ = HAL_ARM_AT91_PIO_CTRL(_pin_); \ + HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, _pctrl_, (AT91_PIO + (_pctrl_ << 9))); \ + CYG_MACRO_END +#endif //! CYGHWR_HAL_ARM_AT91SAM9 + +#endif //!AT91_PIOD // Put a GPIO pin to a given state #define HAL_ARM_AT91_GPIO_PUT(_pin_, _state_) \ diff --git a/packages/hal/arm/at91/var/current/src/hal_diag_dbg.c b/packages/hal/arm/at91/var/current/src/hal_diag_dbg.c index 831a5f6..f1a24d7 100644 --- a/packages/hal/arm/at91/var/current/src/hal_diag_dbg.c +++ b/packages/hal/arm/at91/var/current/src/hal_diag_dbg.c @@ -86,13 +86,13 @@ cyg_hal_plf_serial_dbg_init_channel(void* __ch_data) cyg_uint32 baud_rate = ((channel_data_t*)__ch_data)->baud_rate; /* Enable pins to be driven by peripheral, using peripheral A. */ - HAL_WRITE_UINT32((AT91_PIO+AT91_PIO_ASR), + HAL_WRITE_UINT32((AT91_PIO_DBGU+AT91_PIO_ASR), (AT91_PIO_PSR_DRXD | AT91_PIO_PSR_DTXD)); /* Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). */ - HAL_WRITE_UINT32((AT91_PIO+AT91_PIO_PDR), + HAL_WRITE_UINT32((AT91_PIO_DBGU+AT91_PIO_PDR), (AT91_PIO_PSR_DRXD | AT91_PIO_PSR_DTXD));