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Re: stm32 flash size fix
- From: Nick Garnett <nickg at ecoscentric dot com>
- To: Simon Kallweit <simon dot kallweit at intefo dot ch>
- Cc: eCos Patches List <ecos-patches at ecos dot sourceware dot org>
- Date: 19 Dec 2008 19:01:51 +0000
- Subject: Re: stm32 flash size fix
- References: <494BB5FD.4050907@intefo.ch>
Simon Kallweit <simon.kallweit@intefo.ch> writes:
> As stated in the stm32 errata sheet, the debug registers (MCU_ID) is
> not readable by user software and cannot be used to detect the flash
> size. It's all fine when running in debug mode (JTAG), but not as a
> standalone application. This patch hardcodes the flash and block sizes
> based on the configuration.
I've checked this in, modified to generate a compilation error if no
valid STM32 variant is detected.
Here's the resulting patch:
Index: current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/flash/cortexm/stm32/current/ChangeLog,v
retrieving revision 1.2
diff -u -5 -r1.2 ChangeLog
--- current/ChangeLog 4 Nov 2008 10:02:15 -0000 1.2
+++ current/ChangeLog 19 Dec 2008 15:20:45 -0000
@@ -1,5 +1,11 @@
+2008-12-19 Simon Kallweit <simon.kallweit@intefo.ch>
+
+ * src/stm32_flash.c:
+ Hardcoded flash and block sizes as the debug registers are not
+ readable by user software.
+
2008-11-04 Simon Kallweit <simon.kallweit@intefo.ch>
* src/stm32_flash.c:
Fixed detection on early silicon.
Index: current/src/stm32_flash.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/flash/cortexm/stm32/current/src/stm32_flash.c,v
retrieving revision 1.2
diff -u -5 -r1.2 stm32_flash.c
--- current/src/stm32_flash.c 4 Nov 2008 10:02:15 -0000 1.2
+++ current/src/stm32_flash.c 19 Dec 2008 15:20:45 -0000
@@ -42,10 +42,11 @@
//
//####DESCRIPTIONEND####
//
//========================================================================*/
+#include <pkgconf/hal_cortexm_stm32.h>
#include <pkgconf/devs_flash_stm32.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_ass.h>
#include <cyg/infra/diag.h>
@@ -101,39 +102,49 @@
static int
stm32_flash_init(struct cyg_flash_dev* dev)
{
cyg_stm32_flash_dev *stm32_dev = (cyg_stm32_flash_dev *)dev->priv;
CYG_ADDRESS base = CYGHWR_HAL_STM32_FLASH;
- cyg_uint32 sig, id;
cyg_uint32 flash_size, block_size = 0;
// Set up the block info entries.
dev->block_info = &stm32_dev->block_info[0];
dev->num_block_infos = 1;
- // Get flash size from device signature and MCU ID
+ // As stated in the errata sheet, the debug register can only be read in
+ // debug mode and is therfore not accessible by user software.
- HAL_READ_UINT32( CYGHWR_HAL_STM32_DEV_SIG, sig );
- HAL_READ_UINT32( CYGHWR_HAL_STM32_MCU_ID, id );
+#if defined(CYGHWR_HAL_CORTEXM_STM32_F103RC) || \
+ defined(CYGHWR_HAL_CORTEXM_STM32_F103VC) || \
+ defined(CYGHWR_HAL_CORTEXM_STM32_F103ZC)
+
+ // High-density device with 256K flash (2K blocks)
+ flash_size = 0x40000;
+ block_size = 0x800;
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F103RD) || \
+ defined(CYGHWR_HAL_CORTEXM_STM32_F103VD) || \
+ defined(CYGHWR_HAL_CORTEXM_STM32_F103ZD)
+
+ // High-density device with 384K flash (2K blocks)
+ flash_size = 0x60000;
+ block_size = 0x800;
+
+#elif defined(CYGHWR_HAL_CORTEXM_STM32_F103RE) || \
+ defined(CYGHWR_HAL_CORTEXM_STM32_F103VE) || \
+ defined(CYGHWR_HAL_CORTEXM_STM32_F103ZE)
+
+ // High-density device with 512K flash (2K blocks)
+ flash_size = 0x80000;
+ block_size = 0x800;
- stf_diag("sig %08x id %08x\n", sig, id );
-
- flash_size = CYGHWR_HAL_STM32_DEV_SIG_FSIZE(sig);
-
- if( CYGHWR_HAL_STM32_MCU_ID_DEV(id) == CYGHWR_HAL_STM32_MCU_ID_DEV_MEDIUM )
- {
- block_size = 1024;
- if( flash_size == 0xFFFF ) flash_size = 128;
- }
- else if( CYGHWR_HAL_STM32_MCU_ID_DEV(id) == CYGHWR_HAL_STM32_MCU_ID_DEV_HIGH )
- {
- block_size = 2048;
- if( flash_size == 0xFFFF ) flash_size = 512;
- }
+#else
- flash_size *= 1024;
+#error Unknown STM32 microprocessor variant.
+
+#endif
stm32_dev->block_info[0].blocks = flash_size/block_size;
stm32_dev->block_info[0].block_size = block_size;
// Set end address
--
Nick Garnett eCos Kernel Architect
eCosCentric Limited http://www.eCosCentric.com The eCos experts
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