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stm32 adc driver fix
- From: Simon Kallweit <simon dot kallweit at intefo dot ch>
- To: ecos-patches at ecos dot sourceware dot org
- Date: Fri, 21 Aug 2009 15:04:33 +0200
- Subject: stm32 adc driver fix
Another patch still waiting to be committed. It fixes a problem with the
usage of the internal timer for scanning.
Simon
diff --git a/packages/devs/adc/cortexm/stm32/current/ChangeLog b/packages/devs/adc/cortexm/stm32/current/ChangeLog
index 3d7f028..61a4286 100644
--- a/packages/devs/adc/cortexm/stm32/current/ChangeLog
+++ b/packages/devs/adc/cortexm/stm32/current/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-05 Simon Kallweit <simon.kallweit@intefo.ch>
+
+ * src/adc_stm32.c:
+ Fixed a bug in setup and usage of the timer.
+
2009-02-24 Simon Kallweit <simon.kallweit@intefo.ch>
* cdl/adc_stm32.cdl:
diff --git a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
index a7790db..adb9466 100644
--- a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
+++ b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c
@@ -341,17 +341,9 @@ stm32_adc_set_rate( cyg_adc_channel *chan, cyg_uint32 rate)
HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_ARR,
period - 1);
- // Set direction = down, clock divider = 1
- cr = CYGHWR_HAL_STM32_TIM_CR1_DIR | CYGHWR_HAL_STM32_TIM_CR1_CKD_1;
- HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR1, cr);
-
// Reinitialize timer
cr = CYGHWR_HAL_STM32_TIM_EGR_UG;
HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_EGR, cr);
-
- // Enable generation of TRGO event
- cr = CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE;
- HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR2, cr);
}
//-----------------------------------------------------------------------------
@@ -367,12 +359,16 @@ stm32_dma_isr(cyg_vector_t vector, cyg_addrword_t data)
cyg_uint32 chan_active = info->chan_mask;
cyg_uint16 *sample = info->dma_buf;
cyg_adc_channel **chan = info->chan;
- cyg_uint32 res = 0;
+ cyg_uint32 isr;
+ cyg_uint32 res = CYG_ISR_HANDLED;
+
+ HAL_READ_UINT32(info->setup->dma_base + CYGHWR_HAL_STM32_DMA_ISR, isr);
+ if (!(isr & CYGHWR_HAL_STM32_DMA_ISR_MASK(info->setup->dma_channel)))
+ return 0;
while (chan_active) {
if (chan_active & 0x1)
- res |= (CYG_ISR_HANDLED |
- cyg_adc_receive_sample(*chan, *sample++ & 0xfff));
+ res |= cyg_adc_receive_sample(*chan, *sample++ & 0xfff);
chan_active >>= 1;
chan++;
}
@@ -486,7 +482,17 @@ stm32_adc_init_device(cyg_adc_device *device)
// Enable scanning
cr = CYGHWR_HAL_STM32_ADC_CR1_SCAN;
HAL_WRITE_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR1, cr);
+
+
+ // Set timer direction = down, clock divider = 1
+ cr = CYGHWR_HAL_STM32_TIM_CR1_DIR | CYGHWR_HAL_STM32_TIM_CR1_CKD_1;
+ HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR1, cr);
+
+ // Enable generation of TRGO event
+ cr = CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE;
+ HAL_WRITE_UINT32(info->setup->tim_base + CYGHWR_HAL_STM32_TIM_CR2, cr);
+
// Setup DMA channel
HAL_WRITE_UINT32(info->setup->dma_base +
CYGHWR_HAL_STM32_DMA_CPAR(info->setup->dma_channel),