Re: STRATA v2 buffered programming fix

[Edgar Grimberg <edgar dot grimberg at zylin dot com>]

Hi Kurt,


On Fri, Oct 16, 2009 at 7:01 PM, Kurt Siedenburg
<kurt.siedenburg@vicom.com> wrote:
> Edgar,
> ?a while ago I got Nymonyx 65nm P30 chips as a replacement for older
> Strata chips.

Thanks for the info. I've got the old Intel branded flash chip. The
cause of my problems was actually a cache issue. I've got a bit
confused because I got errors from different sources and I was trying
to silence them down.
Now I'm testing the flash driver by using the uncached addresses and
things look fine.
The annoying part of the problem is the CPU. It cannot just disable
all caches, it cannot invalidate all cache lines, so I need to find a
nice solution for this. I'll be reading some other HALs to see how
this was solved.

Regards,
Edgar



> ?One problem I encountered is an incompatibility to its
> predecessors: ?The buffer size for programmed operations has increased
> to 512 words (that's not yet incompatible). ?However you can only use
> the full buffer size if it is naturally aligned.
>
> The datasheet reads
>
> "The maximum buffer size would be 256-word if the misaligned address
> range is crossing a 512-word boundary during programming."
>
> Maybe this is the source of your troubles.
> It definitly took me a while to find this piece of information.
>
> I had suggested a patch for this issue a while back (Mar 5/6 2009) on
> this list.
> I didn't check/follow up on it to see if it ever made it to the
> repository.
>
> I recall vaguely that someone else contributed another patch in this
> area sometime later.
> Maybe that patch addresses the issue above as well.
>
> Best,
> ?Kurt
>
>



-- 
Edgar Grimberg
System Developer
Zylin AS
ZY1000 JTAG Debugger http://www.zylin.com/zy1000.html
Phone: (+47) 51 63 25 00