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[Bug 1001114] New port: NXP LPC17XX Variant, Olimex LPC-1766-STK platform


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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
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   Attachment #1084|0                           |1
        is obsolete|                            |

--- Comment #19 from Ilija Kocho <ilijak@siva.com.mk> 2011-02-03 17:00:52 GMT ---
Created an attachment (id=1117)
 --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1117)
Updated LPC17xx HAL for review. (Extract in packages/hal.)

Here I submit updated LPC17xx HAL for review.

Notes:

1. User defined sections

SECTION_user() macro definition moved in cortexm.ld (Bug 1001142).

2. Ethernet buffers

Ethernet buffers are placed in user defined section instead in raw memory. This
provides linker control, flexible CDL memory tuning and maximal memory
utilization if this block is placed in same section with lwIP buffers. Section
can be selected with CYGHWR_HAL_LPC_EMAC_MEM_SECTION component in
hal_cortexm_lpc17xx_lpc1766stk.cdl.

3. lwIP memory control

lwIP memory control CYGOPT_LWIP_PLF_MEM_OPT besides section selector contains
sets of memory constrains respective to section selection. There are 3 sets of
constrains corresponding to 3 cases:
  - CYGOPT_LWIP_PLF_MEM_LIMIT_SS0 (Eth and lwIP buffs are in same section)
  - CYGOPT_LWIP_PLF_MEM_LIMIT_SS1 (Eth and lwIP buffs are in different
sections)
  - CYGOPT_LWIP_PLF_MEM_LIMIT_NSS lwIP buffs are not in special section.

Constrains follow behavior proposed by John for Bug 1001125
(http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001125#c17):
   -- Constrains set activation follows lwIP (Eth) section selection.
   -- User can disable active constrains set and do fine tuning manually.

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