[Bug 1000819] Add support for Atmel AT91SAM9263

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--- Comment #22 from John Dallaway <john@dallaway.org.uk> 2011-03-22 14:13:53 GMT ---
Patch 3 is separating the PIO layout definitions for various AT91 family
processors into separate header files. Historically, these definitions have all
been placed in var_io.h within various preprocessor blocks under the control
of:

  CYGHWR_HAL_ARM_AT91_M55800A
  CYGHWR_HAL_ARM_AT91SAM7
  CYGHWR_HAL_ARM_AT91SAM7S
  CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32
  CYGHWR_HAL_ARM_AT91SAM7X
  CYGHWR_HAL_ARM_AT91SAM7SE

Patch 3 separates these out into separate header files for M55800A, SAM7S,
SAM7SE, SAM7X and other ("default") processors, all within the AT91 variant
HAL. The relevant header file is specified by CYGBLD_HAL_AT91_PIO_LAYOUT_H.

Patch 3 paves the way for the introduction of further PIO layout header files
for the AT91SAM9 processors. Evgeniy's port to AT91SAM9263 includes a PIO
layout header file dedicated to this processor (AT91SAM9263) and this is also
located within the AT91 variant HAL.

I don't think there can be any argument that the historical approach of adding
more and more preprocessor blocks to the AT91 var_io.h is not scalable. So the
issues are:

a) Is the separation of PIO layout definitions into separate header files
implemented at the correct level in this case (processor level)?

b) Does it make sense to separate the PIO layout definitions from other I/O
definitions (if any) in this way?

c) For the existing ports, would it be preferable to place the PIO layout
definitions in the processor HAL rather than in the AT91 variant HAL? This
would avoid the need to give each PIO layout header file a unique name. We need
to weigh up the risk of breaking platform ports we cannot readily test.

d) For new ports (including AT91SAM9 family), would it be preferable to place
the PIO layout definitions in the processor HAL rather than in the AT91 variant
HAL? I definitely think so.

Comments?

Any other issues relating specifically to patch 3?

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