This is the mail archive of the mailing list for the eCos project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[Bug 1001187] New port: Freescale Kinetis variant, Freescale TWR-K60N512, Freescale UART device driver

Please do not reply to this email. Use the web interface provided at:

Ilija Kocho <> changed:

           What    |Removed                     |Added
   Attachment #1198|0                           |1
        is obsolete|                            |

--- Comment #5 from Ilija Kocho <> 2011-04-19 22:24:39 BST ---
Created an attachment (id=1212)
 --> (
Kinetis HAL variant / TWR-K60N512 patform 20110419

Here is updated Kinetis HAL,

Main difference is addition of SRAM startup that enables upload of eCos in
on-chip  SRAM by means of JTAG.

Topics for consideration:

1. FLASH sections:

1.1 Kinets controllers have a special area in FLASH at addr. 0x400..0x40F that
contains flash security configuration. 
In order to meet this, a new section is ".flash_security" introduced in MLT
files. Currently this section is encoded in natural form in MLT files (in a
same way as for Freescale MAC7100 port). I tried with USER_SECTION but ld
garbage collector discars this section as it is not referenced - so needs KEEP


1.2 As a consequence of 1.1 flash area (1 KiB) below 0x400 is cut-off from main
flash body. In order to utilize this memory the USER_SECTION ".kinetis_misc" is
introduced. It currently accomodates functions from kinetis_misc.c (as well as
platform misc) but still remains about half empty. 

Please suggest candidate (functions, etc.) to fill this area.

2. SRAM Layout

Kinetis SRAM consists of two equal-size banks that occupy (consecutive) memory
blocks above and below 0x20000000. Below is example of K60N512 (2 x 64KiB)

      0x20010000    --------------
                    |    SRAM_U  |  <---> System Bus
      0x20000000 --------------------
                    |    SRAM_L  |  <---> Code bus
      0x1FFF0000    --------------

These blocks are being accessed by two separate Cortex-M buses (according to
Cortex-M architecture) allowing simultaneous access (by either Harward or
concurrent bus masters). On the other hand SRAM can also be used as flat area
allowing for better SRAM utilization.

In order to provide user a choice, the CDL option
CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED and parallel MLT files with unified and
non-unified SRAM are provided.



Configure bugmail:
------- You are receiving this mail because: -------
You are on the CC list for the bug.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]