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[Bug 1001275] Cortex-M (armV7) architecture endian instructions / Applied on lwIP

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--- Comment #23 from Sergei Gavrikov <> 2011-08-23 20:27:36 BST ---
(In reply to comment #19)
> Created an attachment (id=1348)
 --> (
> Cortex-M architecture endian 110823
> Here I re-submit Cortex-M arch integral patch, headers+CDL.

Regarding attachment 1348

hal_cortexm.cdl (CYGIMP_HAL_ARCH_ENDIAN): reformatted according CDL
coding style, fixed a typo in description (s/bute/byte) and I would
have said

+        default_value 1
+        description   "
+            Cortex-M architecture implements instructions for endian
+            manipulation (byte swapping).  If enabled, this feature
+            can produce shorter and faster code for that."


Ilija, I missed that you have used such an order for arguments in REV
macros, for example

+// Reverse word
+#define CYGARC_REV(_swapped_,_original_) \
+        __asm__ volatile ("rev %0, %1\n" : "=r"(_swapped_) : "r"(_original_))

It looks clear for ARM assembler gurus (dst <- src), and for C-guys it
looks a bit puzzled, (IMO) they are accustomed to same

#define HAL_READ_UINT32( _register_, _value_ ) \

Still, I would use prototypes where result returns in the second
argument. And if you have no objections I would use multiline variants
for those macros.

#define CYGARC_REV( _origin_, _swapped_ )       \
    asm volatile( "rev %0, %1\n"                \
                  : "=r" (_swapped_)            \
                  : "r" (_origin_)              \

You will not be against it (re-ordering the arguments)?

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