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[Bug 1001219] Ethernet driver for STM32 connectivity line with port on MMstm32f107 board.
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: ecos-patches at ecos dot sourceware dot org
- Date: Tue, 25 Dec 2012 11:33:47 +0000
- Subject: [Bug 1001219] Ethernet driver for STM32 connectivity line with port on MMstm32f107 board.
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--- Comment #43 from Ilija Kocho <firstname.lastname@example.org> 2012-12-25 11:33:45 GMT ---
(In reply to comment #42)
> Created an attachment (id=2007)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=2007) [details]
> Eth driver for STM32 family.
> Hello Ilija,
> (In reply to comment #41)
> > (In reply to comment #39)
> > > Created an attachment (id=1997)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1997) [details]
> > > Eth driver for STM32 family.
> > > After long time I've gone back to eth driver and now it's works as well on
> > > STM32F4 controller.
> > > Patch consists only from driver, few extra definitions in
> > > packages/hal/cortexm/stm32/var/current/include/var_io_eth and entry in ecos.db
> > > Disclaimer:
> > > Driver was tested only on Olimex board STM32-E407 what means different
> > > connections
> > > between PHY and MAC (RMII mode and clock 50 MHz from external generator) than
> > > on STM3240G-EVAL.
> > >
> > Jerzy, it would be of great help for testing if you provide some HAL patch for
> > STM3240G-EVAL
> I hope that I didnât miss anything. At now I couldn't find no more that type of
> MII interface requested by ETH driver - rest stuff like pins configuration,
> clocks enabling and so on is done by driver.
> Regarding CYGNUM_DEVS_ETH_CORTEXM_STM32_REMAP_PINS option is valid only for F1
> family while AFAIK it isn't any stm32_f1 board with Ethernet support in eCos
> repo. Thus I left it in driver's cdl without implementing inside the driver. If
> you think that the driver should configure it not board dependent part I will
> add it.
Thank you for the update.
I am able to run httpd_sequential on STM3240G-EVAL after I have:
1. Added CYGPKG_DEVS_ETH_CORTEXM_STM32 and CYGPKG_DEVS_ETH_PHY to target
2. Changed CYGHWR_DEVS_ETH_PHY_DP83847 to CYGHWR_DEVS_ETH_PHY_DP8384X
3. Changed J5 to select external clock.
Note: Selecting the MCO option produces conflict - needs fix.
The good thing is that I did not have to touch the driver, but the MCO conflict
implies that some fix may be needed.
On the formal side - pay attention to trailing spaces.
When posting the updated code please split the driver, HAL and ecos.db in
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