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[Bug 1001219] Ethernet driver for STM32 connectivity line with port on MMstm32f107 board.

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--- Comment #44 from Jerzy Dyrda <> 2012-12-27 17:45:12 GMT ---
Hello Ilija,

(In reply to comment #43)
> (In reply to comment #42)
> > Created an attachment (id=2007)
 --> ( [details]
> > Eth driver for STM32 family.
> > (In reply to comment #41)
> > > (In reply to comment #39)
> > > 
> > > Jerzy, it would be of great help for testing if you provide some HAL patch for
> > > STM3240G-EVAL
> > I hope that I didnât miss anything. At now I couldn't find no more that type of
> > MII interface requested by ETH driver - rest stuff like pins configuration,
> > clocks enabling and so on is done by driver.
> > Regarding CYGNUM_DEVS_ETH_CORTEXM_STM32_REMAP_PINS option is valid only for F1
> > family while AFAIK it isn't any stm32_f1 board with Ethernet support in eCos
> > repo. Thus I left it in driver's cdl without implementing inside the driver. If
> > you think that the driver should configure it not board dependent part I will
> > add it.
> Thank you for the update.
> I am able to run httpd_sequential on STM3240G-EVAL after I have:
> stm3240g_eval (ecos.db)
> (hal_cortexm_stm32_stm32x0g_eval.cdl)
Exactly. I forgot.

> 3. Changed J5 to select external clock.
> Note: Selecting the MCO option produces conflict - needs fix.
> The good thing is that I did not have to touch the driver, but the MCO 
> conflict implies that some fix may be needed.
This was my source of worryings - MCO clock for PHY. According to the conflict
in deed I faced such problem but I ignored it.

> On the formal side - pay attention to trailing spaces.
> When posting the updated code please split the driver, HAL and ecos.db in
> separate patches.
Of course.

Should I correct something or regenerate patch split into parts or
patch in current state is acceptable?

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