[Bug 1001607] Cortex-M4F architectural Floating Point Support

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001607

--- Comment #53 from Ilija Kocho <ilijak@siva.com.mk> ---
Hi Jifl

(In reply to comment #52)
> Hi Ilija,
> 

[snip]

> (In reply to comment #45)
> >     - fpinttest.c renamed fpinttestf.c.
> >     - Added fpinttestf1.c for testing of NONE context switching scheme, as
> > it normally fails fpinttestf.c
> 
> In that case fpinttestf.c should use CYG_TEST_NA if it's using the NONE
> context scheme - tests should do the right thing whatever the configuration.
> 
> So I suggest adding this to the tests in fpinttestf.c for when to be NA
> (including in the CYG_TEST_NA call itself at the bottom):
>  (!defined(CYGHWR_HAL_CORTEXM_FPU) || !defined(CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE))

I don't think we need the CYGHWR_HAL_CORTEXM_FPU test. On the other hand
fprintestsf.c is included in fpinttestf1.c which overrides FP_THREADS_N.
Therefore for the last condition I put:
(!defined(CYGHWR_HAL_CORTEXM_FPU_SWITCH_NONE) || (FP_THREADS_N == 1))

FAOD: Since we want to move tests in kernel/tests, we don't have problem with
mentioning CORTEXM macros, do we?

> 
> 
> (In reply to comment #50)
> > 
> > Here is a patch with CYGARC_CORTEXM_FPU_EXC_AUTOSAVE option removed.
> > CYGARC_CORTEXM_FPU_EXC_AUTOSAVE still lives as a macro defined in
> > fpv4_sp_d16.h.
> 
> Hmm, so I've now started wondering about saving the context in lazy mode as
> well. You already set CYGARC_REG_FPU_FPCCR_ASPEN/LSPEN for lazy mode which
> means the CPU will already be doing lazy stacking in interrupt/exception
> handlers.
> 
> So in fact, can we just change the define at the top of fpv4_sp_d16.h to:
> 
> #if defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL || \
>     defined CYGHWR_HAL_CORTEXM_FPU_SWITCH_LAZY
> #define CYGARC_CORTEXM_FPU_EXC_AUTOSAVE
> #endif
> 
> and then change the CYGHWR_HAL_CORTEXM_FPU_SWITCH_ALL test on line 158 to
> also include LAZY, and then it might just work for lazy mode too? I can't
> see anything else in the way.

Provided that that LAZY uses FPU enabled/disbled state in order to distinguish
between _FP_ and _INT_ threads, suppose that _INT_ thread is interrupted by
_FP_ ISR. Then Usage Fault VSR will enable FPU and FPU will remain enabled
after ISR returns [in thread context], effectively converting the tread to
_FP_. Gradually, this ISR "_FP_ missioner" ISR may convert all threads to _FP_
so we're not lazy any more.

There are also other problems, related to variable ISR stack frame length, that
are described in that comment #42 and/or comment #47.

[snip]

> 
> BTW don't forget at some point to either tidy up the indentations in the
> CDL, or let me know and I will do so after check-in - you've done enough
> after all!

I take it that we are a step or less to check in :)

I am trying to keep the code tidy as we apporach end of the pipeline, but
sometimes my editor tries to play smart and doesn't agree with me. I'll check
it before check-in, but if you are not happy you are welcome to edit.

Speaking of CDL cross check, I would ask you is to make language and clarity
check on larger descrioptions, especially CYGHWR_HAL_CORTEXM_FPU_SWITCH.

Thanks for the comments.

Ilija

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